rs6000-c.c (altivec_resolve_overloaded_builtin): Add support for vec_extract on vector float...
[gcc]
2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Add support for vec_extract on vector float, vector int, vector
short, and vector char vector types.
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
vector float, vector int, vector short, and vector char
optimizations on 64-bit ISA 2.07 systems for both constant and
variable element numbers.
(rs6000_split_vec_extract_var): Likewise.
* config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Allow SFmode to be
Altivec registers on ISA 2.07 and above.
(vsx_extract_v4sf): Delete alternative that hard coded element 0,
which never was matched due to the split occuring before register
allocation (and the code would not have worked on little endian
systems if it did match). Allow extracts to go to the Altivec
registers if ISA 2.07 (power8). Change from using "" around the
C++ code to using {}'s.
(vsx_extract_v4sf_<mode>_load): New insn to optimize vector float
vec_extracts when the vector is in memory.
(vsx_extract_v4sf_var): New insn to optimize vector float
vec_extracts when the element number is variable on 64-bit ISA
2.07 systems.
(vsx_extract_<mode>, VSX_EXTRACT_I iterator): Add optimizations
for 64-bit ISA 2.07 as well as ISA 3.0.
(vsx_extract_<mode>_p9, VSX_EXTRACT_I iterator): Likewise.
(vsx_extract_<mode>_p8, VSX_EXTRACT_I iterator): Likewise.
(vsx_extract_<mode>_load, VSX_EXTRACT_I iterator): New insn to
optimize vector int, vector short, and vector char vec_extracts
when the vector is in memory.
(vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): New insn to
optimize vector int, vector short, and vector char vec_extracts
when the element number is variable.
[gcc/testsuite]
2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-extract-5.c: New tests to test
vec_extract for vector float, vector int, vector short, and vector
char.
* gcc.target/powerpc/vec-extract-6.c: Likewise.
* gcc.target/powerpc/vec-extract-7.c: Likewise.
* gcc.target/powerpc/vec-extract-8.c: Likewise.
* gcc.target/powerpc/vec-extract-9.c: Likewise.
From-SVN: r238971
This commit is contained in:
Michael Meissner
parent
72a30e45c5
commit
e2a9919451
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@ -1,3 +1,37 @@
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2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
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Add support for vec_extract on vector float, vector int, vector
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short, and vector char vector types.
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* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
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vector float, vector int, vector short, and vector char
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optimizations on 64-bit ISA 2.07 systems for both constant and
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variable element numbers.
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(rs6000_split_vec_extract_var): Likewise.
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* config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Allow SFmode to be
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Altivec registers on ISA 2.07 and above.
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(vsx_extract_v4sf): Delete alternative that hard coded element 0,
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which never was matched due to the split occuring before register
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allocation (and the code would not have worked on little endian
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systems if it did match). Allow extracts to go to the Altivec
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registers if ISA 2.07 (power8). Change from using "" around the
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C++ code to using {}'s.
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(vsx_extract_v4sf_<mode>_load): New insn to optimize vector float
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vec_extracts when the vector is in memory.
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(vsx_extract_v4sf_var): New insn to optimize vector float
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vec_extracts when the element number is variable on 64-bit ISA
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2.07 systems.
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(vsx_extract_<mode>, VSX_EXTRACT_I iterator): Add optimizations
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for 64-bit ISA 2.07 as well as ISA 3.0.
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(vsx_extract_<mode>_p9, VSX_EXTRACT_I iterator): Likewise.
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(vsx_extract_<mode>_p8, VSX_EXTRACT_I iterator): Likewise.
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(vsx_extract_<mode>_load, VSX_EXTRACT_I iterator): New insn to
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optimize vector int, vector short, and vector char vec_extracts
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when the vector is in memory.
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(vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): New insn to
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optimize vector int, vector short, and vector char vec_extracts
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when the element number is variable.
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2016-08-01 Georg-Johann Lay <avr@gjlay.de>
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PR target/71948
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@ -5135,6 +5135,25 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
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case V2DImode:
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
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break;
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case V4SFmode:
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
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break;
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case V4SImode:
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if (TARGET_DIRECT_MOVE_64BIT)
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
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break;
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case V8HImode:
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if (TARGET_DIRECT_MOVE_64BIT)
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
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break;
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case V16QImode:
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if (TARGET_DIRECT_MOVE_64BIT)
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
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break;
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}
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}
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@ -5154,6 +5173,22 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
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case V2DImode:
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
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break;
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case V4SFmode:
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
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break;
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case V4SImode:
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
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break;
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case V8HImode:
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
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break;
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case V16QImode:
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call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
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break;
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}
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}
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@ -6938,7 +6938,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
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emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
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return;
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case V16QImode:
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if (TARGET_VEXTRACTUB)
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if (TARGET_DIRECT_MOVE_64BIT)
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{
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emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
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return;
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@ -6946,7 +6946,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
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else
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break;
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case V8HImode:
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if (TARGET_VEXTRACTUB)
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if (TARGET_DIRECT_MOVE_64BIT)
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{
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emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
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return;
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@ -6954,7 +6954,7 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
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else
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break;
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case V4SImode:
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if (TARGET_VEXTRACTUB)
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if (TARGET_DIRECT_MOVE_64BIT)
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{
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emit_insn (gen_vsx_extract_v4si (target, vec, elt));
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return;
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@ -6982,6 +6982,26 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
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emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
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return;
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case V4SFmode:
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if (TARGET_UPPER_REGS_SF)
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{
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emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
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return;
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}
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break;
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case V4SImode:
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emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
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return;
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case V8HImode:
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emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
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return;
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case V16QImode:
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emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
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return;
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default:
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gcc_unreachable ();
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}
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@ -7253,6 +7273,33 @@ rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
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emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
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return;
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case V4SFmode:
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{
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rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
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rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
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rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
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emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
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tmp_altivec));
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emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
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return;
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}
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case V4SImode:
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case V8HImode:
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case V16QImode:
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{
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rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
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rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
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rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
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emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
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tmp_altivec));
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emit_move_insn (tmp_gpr_di, tmp_altivec_di);
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emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
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GEN_INT (64 - (8 * scalar_size))));
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return;
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}
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default:
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gcc_unreachable ();
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}
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@ -1663,7 +1663,7 @@
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;; Same as vsx_xscvspdp, but use SF as the type
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(define_insn "vsx_xscvspdp_scalar2"
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[(set (match_operand:SF 0 "vsx_register_operand" "=f")
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[(set (match_operand:SF 0 "vsx_register_operand" "=ww")
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(unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVSPDP))]
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"VECTOR_UNIT_VSX_P (V4SFmode)"
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@ -2237,18 +2237,15 @@
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;; Extract a SF element from V4SF
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(define_insn_and_split "vsx_extract_v4sf"
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[(set (match_operand:SF 0 "vsx_register_operand" "=f,f")
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[(set (match_operand:SF 0 "vsx_register_operand" "=ww")
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(vec_select:SF
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(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
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(parallel [(match_operand:QI 2 "u5bit_cint_operand" "O,i")])))
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(clobber (match_scratch:V4SF 3 "=X,0"))]
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(match_operand:V4SF 1 "vsx_register_operand" "wa")
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(parallel [(match_operand:QI 2 "u5bit_cint_operand" "n")])))
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(clobber (match_scratch:V4SF 3 "=0"))]
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"VECTOR_UNIT_VSX_P (V4SFmode)"
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"@
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xscvspdp %x0,%x1
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#"
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""
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"#"
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"&& 1"
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[(const_int 0)]
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"
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{
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rtx op0 = operands[0];
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rtx op1 = operands[1];
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@ -2268,10 +2265,46 @@
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}
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emit_insn (gen_vsx_xscvspdp_scalar2 (op0, tmp));
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DONE;
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}"
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[(set_attr "length" "4,8")
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}
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[(set_attr "length" "8")
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(set_attr "type" "fp")])
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(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
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[(set (match_operand:SF 0 "register_operand" "=f,wv,wb,?r")
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(vec_select:SF
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(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
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(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
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(clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
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"VECTOR_MEM_VSX_P (V4SFmode)"
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (match_dup 4))]
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{
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operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
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operands[3], SFmode);
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}
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[(set_attr "type" "fpload,fpload,fpload,load")
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(set_attr "length" "8")])
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;; Variable V4SF extract
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(define_insn_and_split "vsx_extract_v4sf_var"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=ww,ww,?r")
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(unspec:SF [(match_operand:V4SF 1 "input_operand" "v,m,m")
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(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
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UNSPEC_VSX_EXTRACT))
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(clobber (match_scratch:DI 3 "=r,&b,&b"))
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(clobber (match_scratch:V2DI 4 "=&v,X,X"))]
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"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT
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&& TARGET_UPPER_REGS_SF"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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rs6000_split_vec_extract_var (operands[0], operands[1], operands[2],
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operands[3], operands[4]);
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DONE;
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})
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;; Expand the builtin form of xxpermdi to canonical rtl.
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(define_expand "vsx_xxpermdi_<mode>"
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[(match_operand:VSX_L 0 "vsx_register_operand" "")
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@ -2370,7 +2403,21 @@
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;; Extraction of a single element in a small integer vector. None of the small
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;; types are currently allowed in a vector register, so we extract to a DImode
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;; and either do a direct move or store.
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(define_insn_and_split "vsx_extract_<mode>"
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(define_expand "vsx_extract_<mode>"
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[(parallel [(set (match_operand:<VS_scalar> 0 "nonimmediate_operand")
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(vec_select:<VS_scalar>
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(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand")
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(parallel [(match_operand:QI 2 "const_int_operand")])))
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(clobber (match_dup 3))])]
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"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
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{
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operands[3] = gen_rtx_SCRATCH ((TARGET_VEXTRACTUB) ? DImode : <MODE>mode);
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})
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;; Under ISA 3.0, we can use the byte/half-word/word integer stores if we are
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;; extracting a vector element and storing it to memory, rather than using
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;; direct move to a GPR and a GPR store.
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(define_insn_and_split "*vsx_extract_<mode>_p9"
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[(set (match_operand:<VS_scalar> 0 "nonimmediate_operand" "=r,Z")
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(vec_select:<VS_scalar>
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(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "<VSX_EX>,<VSX_EX>")
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@ -2438,6 +2485,95 @@
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}
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[(set_attr "type" "vecsimple")])
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(define_insn_and_split "*vsx_extract_<mode>_p8"
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[(set (match_operand:<VS_scalar> 0 "nonimmediate_operand" "=r")
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(vec_select:<VS_scalar>
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(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v")
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(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
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(clobber (match_scratch:VSX_EXTRACT_I 3 "=v"))]
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"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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rtx dest = operands[0];
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rtx src = operands[1];
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rtx element = operands[2];
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rtx vec_tmp = operands[3];
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int value;
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if (!VECTOR_ELT_ORDER_BIG)
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element = GEN_INT (GET_MODE_NUNITS (<MODE>mode) - 1 - INTVAL (element));
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/* If the value is in the correct position, we can avoid doing the VSPLT<x>
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instruction. */
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value = INTVAL (element);
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if (<MODE>mode == V16QImode)
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{
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if (value != 7)
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emit_insn (gen_altivec_vspltb_direct (vec_tmp, src, element));
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else
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vec_tmp = src;
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}
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else if (<MODE>mode == V8HImode)
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{
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if (value != 3)
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emit_insn (gen_altivec_vsplth_direct (vec_tmp, src, element));
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else
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vec_tmp = src;
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}
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else if (<MODE>mode == V4SImode)
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{
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if (value != 1)
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emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element));
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else
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vec_tmp = src;
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}
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else
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gcc_unreachable ();
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emit_move_insn (gen_rtx_REG (DImode, REGNO (dest)),
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gen_rtx_REG (DImode, REGNO (vec_tmp)));
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DONE;
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}
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[(set_attr "type" "mftgpr")])
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;; Optimize extracting a single scalar element from memory.
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(define_insn_and_split "*vsx_extract_<mode>_load"
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[(set (match_operand:<VS_scalar> 0 "register_operand" "=r")
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(vec_select:<VS_scalar>
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(match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
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(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
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(clobber (match_scratch:DI 3 "=&b"))]
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"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
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||||
"#"
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (match_dup 4))]
|
||||
{
|
||||
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
|
||||
operands[3], <VS_scalar>mode);
|
||||
}
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Variable V16QI/V8HI/V4SI extract
|
||||
(define_insn_and_split "vsx_extract_<mode>_var"
|
||||
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r")
|
||||
(unspec:<VS_scalar>
|
||||
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "v,m")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
|
||||
UNSPEC_VSX_EXTRACT))
|
||||
(clobber (match_scratch:DI 3 "=r,&b"))
|
||||
(clobber (match_scratch:V2DI 4 "=&v,X"))]
|
||||
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(const_int 0)]
|
||||
{
|
||||
rs6000_split_vec_extract_var (operands[0], operands[1], operands[2],
|
||||
operands[3], operands[4]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Expanders for builtins
|
||||
(define_expand "vsx_mergel_<mode>"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,17 @@
|
|||
2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
|
||||
|
||||
* gcc.target/powerpc/vec-extract-5.c: New tests to test
|
||||
vec_extract for vector float, vector int, vector short, and vector
|
||||
char.
|
||||
* gcc.target/powerpc/vec-extract-6.c: Likewise.
|
||||
* gcc.target/powerpc/vec-extract-7.c: Likewise.
|
||||
* gcc.target/powerpc/vec-extract-8.c: Likewise.
|
||||
* gcc.target/powerpc/vec-extract-9.c: Likewise.
|
||||
|
||||
2016-08-01 Wilco Dijkstra <wdijkstr@arm.com>
|
||||
|
||||
* gcc.target/aarch64/test_frame_10.c: Fix test to check for a
|
||||
single stack adjustment, no writeback.
|
||||
single stack adjustment, no writeback.
|
||||
* gcc.target/aarch64/test_frame_12.c: Likewise.
|
||||
* gcc.target/aarch64/test_frame_13.c: Likewise.
|
||||
* gcc.target/aarch64/test_frame_15.c: Likewise.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-O2 -mcpu=power8" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
signed char
|
||||
add_signed_char_0 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 0) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_1 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 1) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_2 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 2) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_3 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 3) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_4 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 4) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_5 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 5) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_6 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 6) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_7 (vector signed char *p)
|
||||
{
|
||||
return vec_extract (*p, 7) + 1;
|
||||
}
|
||||
|
||||
signed char
|
||||
add_signed_char_n (vector signed char *p, int n)
|
||||
{
|
||||
return vec_extract (*p, n) + 1;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "lxvd2x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvw4x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvx" } } */
|
||||
/* { dg-final { scan-assembler-not "lxv" } } */
|
||||
/* { dg-final { scan-assembler-not "lvx" } } */
|
||||
/* { dg-final { scan-assembler-not "xxpermdi" } } */
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-O2 -mcpu=power8" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_0 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 0) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_1 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 1) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_2 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 2) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_3 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 3) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_4 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 4) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_5 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 5) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_6 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 6) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_7 (vector unsigned char *p)
|
||||
{
|
||||
return vec_extract (*p, 7) + 1;
|
||||
}
|
||||
|
||||
unsigned char
|
||||
add_unsigned_char_n (vector unsigned char *p, int n)
|
||||
{
|
||||
return vec_extract (*p, n) + 1;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "lxvd2x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvw4x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvx" } } */
|
||||
/* { dg-final { scan-assembler-not "lxv" } } */
|
||||
/* { dg-final { scan-assembler-not "lvx" } } */
|
||||
/* { dg-final { scan-assembler-not "xxpermdi" } } */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-O2 -mcpu=power8" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
float
|
||||
add_float_0 (vector float *p)
|
||||
{
|
||||
return vec_extract (*p, 0) + 1.0f;
|
||||
}
|
||||
|
||||
float
|
||||
add_float_1 (vector float *p)
|
||||
{
|
||||
return vec_extract (*p, 1) + 1.0f;
|
||||
}
|
||||
|
||||
float
|
||||
add_float_2 (vector float *p)
|
||||
{
|
||||
return vec_extract (*p, 2) + 1.0f;
|
||||
}
|
||||
|
||||
float
|
||||
add_float_3 (vector float *p)
|
||||
{
|
||||
return vec_extract (*p, 3) + 1.0f;
|
||||
}
|
||||
|
||||
float
|
||||
add_float_n (vector float *p, long n)
|
||||
{
|
||||
return vec_extract (*p, n) + 1.0f;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "lxvd2x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvw4x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvx" } } */
|
||||
/* { dg-final { scan-assembler-not "lxv" } } */
|
||||
/* { dg-final { scan-assembler-not "lvx" } } */
|
||||
/* { dg-final { scan-assembler-not "xxpermdi" } } */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-O2 -mcpu=power8" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
int
|
||||
add_int_0 (vector int *p)
|
||||
{
|
||||
return vec_extract (*p, 0) + 1;
|
||||
}
|
||||
|
||||
int
|
||||
add_int_1 (vector int *p)
|
||||
{
|
||||
return vec_extract (*p, 1) + 1;
|
||||
}
|
||||
|
||||
int
|
||||
add_int_2 (vector int *p)
|
||||
{
|
||||
return vec_extract (*p, 2) + 1;
|
||||
}
|
||||
|
||||
int
|
||||
add_int_3 (vector int *p)
|
||||
{
|
||||
return vec_extract (*p, 3) + 1;
|
||||
}
|
||||
|
||||
int
|
||||
add_int_n (vector int *p, int n)
|
||||
{
|
||||
return vec_extract (*p, n) + 1;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "lxvd2x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvw4x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvx" } } */
|
||||
/* { dg-final { scan-assembler-not "lxv" } } */
|
||||
/* { dg-final { scan-assembler-not "lvx" } } */
|
||||
/* { dg-final { scan-assembler-not "xxpermdi" } } */
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-O2 -mcpu=power8" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
short
|
||||
add_short_0 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 0) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_1 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 1) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_2 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 2) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_3 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 3) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_4 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 4) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_5 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 5) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_6 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 6) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_7 (vector short *p)
|
||||
{
|
||||
return vec_extract (*p, 7) + 1;
|
||||
}
|
||||
|
||||
short
|
||||
add_short_n (vector short *p, int n)
|
||||
{
|
||||
return vec_extract (*p, n) + 1;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-not "lxvd2x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvw4x" } } */
|
||||
/* { dg-final { scan-assembler-not "lxvx" } } */
|
||||
/* { dg-final { scan-assembler-not "lxv" } } */
|
||||
/* { dg-final { scan-assembler-not "lvx" } } */
|
||||
/* { dg-final { scan-assembler-not "xxpermdi" } } */
|
||||
Loading…
Reference in New Issue