arm.c (thumb1_reorg): New function.
* config/arm/arm.c (thumb1_reorg): New function. (arm_reorg): Call thumb1_reorg. (thumb1_final_prescan_insn): Record src operand in thumb1_cc_op0. * config/arm/arm.md : Remove peephole2 patterns which rewrite move into subtract of ZERO. From-SVN: r193841
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@ -1,3 +1,11 @@
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2012-11-27 Bin Cheng <bin.cheng@arm.com>
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* config/arm/arm.c (thumb1_reorg): New function.
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(arm_reorg): Call thumb1_reorg.
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(thumb1_final_prescan_insn): Record src operand in thumb1_cc_op0.
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* config/arm/arm.md : Remove peephole2 patterns which rewrite move
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into subtract of ZERO.
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2012-11-27 Richard Biener <rguenther@suse.de>
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2012-11-27 Richard Biener <rguenther@suse.de>
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PR middle-end/55331
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PR middle-end/55331
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@ -13396,6 +13396,62 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
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return;
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return;
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}
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}
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/* Rewrite move insn into subtract of 0 if the condition codes will
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be useful in next conditional jump insn. */
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static void
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thumb1_reorg (void)
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{
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basic_block bb;
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FOR_EACH_BB (bb)
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{
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rtx set, dest, src;
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rtx pat, op0;
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rtx prev, insn = BB_END (bb);
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while (insn != BB_HEAD (bb) && DEBUG_INSN_P (insn))
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insn = PREV_INSN (insn);
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/* Find the last cbranchsi4_insn in basic block BB. */
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if (INSN_CODE (insn) != CODE_FOR_cbranchsi4_insn)
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continue;
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/* Find the first non-note insn before INSN in basic block BB. */
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gcc_assert (insn != BB_HEAD (bb));
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prev = PREV_INSN (insn);
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while (prev != BB_HEAD (bb) && (NOTE_P (prev) || DEBUG_INSN_P (prev)))
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prev = PREV_INSN (prev);
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set = single_set (prev);
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if (!set)
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continue;
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dest = SET_DEST (set);
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src = SET_SRC (set);
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if (!low_register_operand (dest, SImode)
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|| !low_register_operand (src, SImode))
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continue;
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pat = PATTERN (insn);
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op0 = XEXP (XEXP (SET_SRC (pat), 0), 0);
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/* Rewrite move into subtract of 0 if its operand is compared with ZERO
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in INSN. Don't need to check dest since cprop_hardreg pass propagates
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src into INSN. */
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if (REGNO (op0) == REGNO (src))
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{
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dest = copy_rtx (dest);
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src = copy_rtx (src);
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src = gen_rtx_MINUS (SImode, src, const0_rtx);
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PATTERN (prev) = gen_rtx_SET (VOIDmode, dest, src);
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INSN_CODE (prev) = -1;
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/* Set test register in INSN to dest. */
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XEXP (XEXP (SET_SRC (pat), 0), 0) = copy_rtx (dest);
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INSN_CODE (insn) = -1;
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}
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}
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}
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/* Convert instructions to their cc-clobbering variant if possible, since
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/* Convert instructions to their cc-clobbering variant if possible, since
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that allows us to use smaller encodings. */
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that allows us to use smaller encodings. */
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@ -13592,7 +13648,9 @@ arm_reorg (void)
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HOST_WIDE_INT address = 0;
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HOST_WIDE_INT address = 0;
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Mfix * fix;
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Mfix * fix;
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if (TARGET_THUMB2)
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if (TARGET_THUMB1)
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thumb1_reorg ();
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else if (TARGET_THUMB2)
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thumb2_reorg ();
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thumb2_reorg ();
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/* Ensure all insns that must be split have been split at this point.
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/* Ensure all insns that must be split have been split at this point.
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@ -22155,6 +22213,12 @@ thumb1_final_prescan_insn (rtx insn)
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if (src1 == const0_rtx)
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if (src1 == const0_rtx)
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cfun->machine->thumb1_cc_mode = CCmode;
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cfun->machine->thumb1_cc_mode = CCmode;
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}
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}
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else if (REG_P (SET_DEST (set)) && REG_P (SET_SRC (set)))
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{
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/* Record the src register operand instead of dest because
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cprop_hardreg pass propagates src. */
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cfun->machine->thumb1_cc_op0 = SET_SRC (set);
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}
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}
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}
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else if (conds != CONDS_NOCOND)
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else if (conds != CONDS_NOCOND)
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cfun->machine->thumb1_cc_insn = NULL_RTX;
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cfun->machine->thumb1_cc_insn = NULL_RTX;
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@ -7166,43 +7166,6 @@
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(const_int 8))))]
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(const_int 8))))]
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)
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)
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;; Two peepholes to generate subtract of 0 instead of a move if the
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;; condition codes will be useful.
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(define_peephole2
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[(set (match_operand:SI 0 "low_register_operand" "")
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(match_operand:SI 1 "low_register_operand" ""))
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(set (pc)
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(if_then_else (match_operator 2 "arm_comparison_operator"
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[(match_dup 1) (const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"TARGET_THUMB1"
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[(set (match_dup 0) (minus:SI (match_dup 1) (const_int 0)))
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(set (pc)
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(if_then_else (match_op_dup 2 [(match_dup 0) (const_int 0)])
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(label_ref (match_dup 3))
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(pc)))]
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"")
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;; Sigh! This variant shouldn't be needed, but combine often fails to
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;; merge cases like this because the op1 is a hard register in
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;; arm_class_likely_spilled_p.
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(define_peephole2
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[(set (match_operand:SI 0 "low_register_operand" "")
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(match_operand:SI 1 "low_register_operand" ""))
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(set (pc)
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(if_then_else (match_operator 2 "arm_comparison_operator"
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[(match_dup 0) (const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"TARGET_THUMB1"
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[(set (match_dup 0) (minus:SI (match_dup 1) (const_int 0)))
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(set (pc)
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(if_then_else (match_op_dup 2 [(match_dup 0) (const_int 0)])
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(label_ref (match_dup 3))
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(pc)))]
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"")
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(define_insn "*negated_cbranchsi4"
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(define_insn "*negated_cbranchsi4"
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[(set (pc)
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[(set (pc)
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(if_then_else
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(if_then_else
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