sve: combine inverted masks into NOTs
The following example
void f10(double * restrict z, double * restrict w, double * restrict x,
double * restrict y, int n)
{
for (int i = 0; i < n; i++) {
z[i] = (w[i] > 0) ? x[i] + w[i] : y[i] - w[i];
}
}
generates currently:
ld1d z1.d, p1/z, [x1, x5, lsl 3]
fcmgt p2.d, p1/z, z1.d, #0.0
fcmgt p0.d, p3/z, z1.d, #0.0
ld1d z2.d, p2/z, [x2, x5, lsl 3]
bic p0.b, p3/z, p1.b, p0.b
ld1d z0.d, p0/z, [x3, x5, lsl 3]
where a BIC is generated between p1 and p0 where a NOT would be better here
since we won't require the use of p3 and opens the pattern up to being CSEd.
After this patch using a 2 -> 2 split we generate:
ld1d z1.d, p0/z, [x1, x5, lsl 3]
fcmgt p2.d, p0/z, z1.d, #0.0
not p1.b, p0/z, p2.b
The additional scratch is needed such that we can CSE the two operations. If
both statements wrote to the same register then CSE won't be able to CSE the
values if there are other statements in between that use the register.
A second pattern is needed to capture the nor case as combine will match the
longest sequence first. So without this pattern we end up de-optimizing nor
and instead emit two nots. I did not find a better way to do this.
gcc/ChangeLog:
* config/aarch64/aarch64-sve.md (*fcm<cmp_op><mode>_bic_combine,
*fcm<cmp_op><mode>_nor_combine, *fcmuo<mode>_bic_combine,
*fcmuo<mode>_nor_combine): New.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pred-not-gen-1.c: New test.
* gcc.target/aarch64/sve/pred-not-gen-2.c: New test.
* gcc.target/aarch64/sve/pred-not-gen-3.c: New test.
* gcc.target/aarch64/sve/pred-not-gen-4.c: New test.
This commit is contained in:
Tamar Christina
parent
a1a7d09430
commit
e36206c994
@ -8126,6 +8126,160 @@
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UNSPEC_COND_FCMUO))]
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)
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;; Similar to *fcm<cmp_op><mode>_and_combine, but for BIC rather than AND.
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;; In this case, we still need a separate NOT/BIC operation, but predicating
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;; the comparison on the BIC operand removes the need for a PTRUE.
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(define_insn_and_split "*fcm<cmp_op><mode>_bic_combine"
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[(set (match_operand:<VPRED> 0 "register_operand" "=Upa")
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(and:<VPRED>
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(and:<VPRED>
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(not:<VPRED>
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(unspec:<VPRED>
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[(match_operand:<VPRED> 1)
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(const_int SVE_KNOWN_PTRUE)
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(match_operand:SVE_FULL_F 2 "register_operand" "w")
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(match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")]
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SVE_COND_FP_CMP_I0))
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(match_operand:<VPRED> 4 "register_operand" "Upa"))
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(match_dup:<VPRED> 1)))
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(clobber (match_scratch:<VPRED> 5 "=&Upl"))]
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"TARGET_SVE"
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"#"
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"&& 1"
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[(set (match_dup 5)
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(unspec:<VPRED>
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[(match_dup 4)
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(const_int SVE_MAYBE_NOT_PTRUE)
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(match_dup 2)
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(match_dup 3)]
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SVE_COND_FP_CMP_I0))
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(set (match_dup 0)
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(and:<VPRED>
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(not:<VPRED>
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(match_dup 5))
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(match_dup 4)))]
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{
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (<VPRED>mode);
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}
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)
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;; Make sure that we expand to a nor when the operand 4 of
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;; *fcm<cmp_op><mode>_bic_combine is a not.
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(define_insn_and_split "*fcm<cmp_op><mode>_nor_combine"
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[(set (match_operand:<VPRED> 0 "register_operand" "=Upa")
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(and:<VPRED>
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(and:<VPRED>
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(not:<VPRED>
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(unspec:<VPRED>
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[(match_operand:<VPRED> 1)
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(const_int SVE_KNOWN_PTRUE)
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(match_operand:SVE_FULL_F 2 "register_operand" "w")
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(match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")]
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SVE_COND_FP_CMP_I0))
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(not:<VPRED>
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(match_operand:<VPRED> 4 "register_operand" "Upa")))
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(match_dup:<VPRED> 1)))
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(clobber (match_scratch:<VPRED> 5 "=&Upl"))]
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"TARGET_SVE"
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"#"
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"&& 1"
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[(set (match_dup 5)
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(unspec:<VPRED>
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[(match_dup 1)
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(const_int SVE_KNOWN_PTRUE)
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(match_dup 2)
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(match_dup 3)]
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SVE_COND_FP_CMP_I0))
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(set (match_dup 0)
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(and:<VPRED>
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(and:<VPRED>
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(not:<VPRED>
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(match_dup 5))
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(not:<VPRED>
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(match_dup 4)))
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(match_dup 1)))]
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{
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (<VPRED>mode);
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}
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)
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(define_insn_and_split "*fcmuo<mode>_bic_combine"
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[(set (match_operand:<VPRED> 0 "register_operand" "=Upa")
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(and:<VPRED>
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(and:<VPRED>
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(not:<VPRED>
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(unspec:<VPRED>
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[(match_operand:<VPRED> 1)
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(const_int SVE_KNOWN_PTRUE)
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(match_operand:SVE_FULL_F 2 "register_operand" "w")
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(match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")]
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UNSPEC_COND_FCMUO))
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(match_operand:<VPRED> 4 "register_operand" "Upa"))
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(match_dup:<VPRED> 1)))
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(clobber (match_scratch:<VPRED> 5 "=&Upl"))]
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"TARGET_SVE"
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"#"
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"&& 1"
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[(set (match_dup 5)
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(unspec:<VPRED>
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[(match_dup 4)
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(const_int SVE_MAYBE_NOT_PTRUE)
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(match_dup 2)
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(match_dup 3)]
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UNSPEC_COND_FCMUO))
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(set (match_dup 0)
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(and:<VPRED>
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(not:<VPRED>
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(match_dup 5))
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(match_dup 4)))]
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{
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (<VPRED>mode);
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}
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)
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;; Same for unordered comparisons.
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(define_insn_and_split "*fcmuo<mode>_nor_combine"
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[(set (match_operand:<VPRED> 0 "register_operand" "=Upa")
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(and:<VPRED>
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(and:<VPRED>
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(not:<VPRED>
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(unspec:<VPRED>
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[(match_operand:<VPRED> 1)
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(const_int SVE_KNOWN_PTRUE)
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(match_operand:SVE_FULL_F 2 "register_operand" "w")
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(match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")]
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UNSPEC_COND_FCMUO))
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(not:<VPRED>
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(match_operand:<VPRED> 4 "register_operand" "Upa")))
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(match_dup:<VPRED> 1)))
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(clobber (match_scratch:<VPRED> 5 "=&Upl"))]
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"TARGET_SVE"
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"#"
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"&& 1"
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[(set (match_dup 5)
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(unspec:<VPRED>
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[(match_dup 1)
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(const_int SVE_KNOWN_PTRUE)
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(match_dup 2)
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(match_dup 3)]
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UNSPEC_COND_FCMUO))
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(set (match_dup 0)
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(and:<VPRED>
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(and:<VPRED>
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(not:<VPRED>
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(match_dup 5))
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(not:<VPRED>
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(match_dup 4)))
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(match_dup 1)))]
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{
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if (can_create_pseudo_p ())
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operands[5] = gen_reg_rtx (<VPRED>mode);
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}
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)
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;; -------------------------------------------------------------------------
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;; ---- [FP] Absolute comparisons
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;; -------------------------------------------------------------------------
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23
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c
Normal file
23
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-1.c
Normal file
@ -0,0 +1,23 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O3 --save-temps" } */
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/*
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** f10:
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** ...
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** ld1d z1.d, p0/z, \[x1, x5, lsl 3\]
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** fcmgt p2.d, p0/z, z1.d, #0.0
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** ld1d z2.d, p2/z, \[x2, x5, lsl 3\]
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** not p1.b, p0/z, p2.b
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** ld1d z0.d, p1/z, \[x3, x5, lsl 3\]
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** ...
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*/
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void f10(double * restrict z, double * restrict w, double * restrict x, double * restrict y, int n)
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{
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for (int i = 0; i < n; i++) {
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z[i] = (w[i] > 0) ? x[i] + w[i] : y[i] - w[i];
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}
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}
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/* { dg-final { scan-assembler-not {\tbic\t} } } */
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/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */
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23
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-2.c
Normal file
23
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-2.c
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@ -0,0 +1,23 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O3 --save-temps" } */
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/*
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** f11:
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** ...
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** ld1d z0.d, p0/z, \[x1, x2, lsl 3\]
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** fcmgt p2.d, p3/z, z0.d, #0.0
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** fcmgt p1.d, p0/z, z0.d, #0.0
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** not p1.b, p0/z, p1.b
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** ld1d z1.d, p1/z, \[x3, x2, lsl 3\]
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** ...
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*/
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void f11(double * restrict z, double * restrict w, double * restrict x, double * restrict y, int n)
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{
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for (int i = 0; i < n; i++) {
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z[i] = (w[i] > 0) ? w[i] : y[i];
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}
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}
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/* { dg-final { scan-assembler-not {\tbic\t} } } */
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/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */
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21
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-3.c
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21
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-3.c
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@ -0,0 +1,21 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O3 --save-temps" } */
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/*
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** f12:
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** ...
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** ld1w z1.s, p0/z, \[x1, x2, lsl 2\]
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** cmple p1.s, p0/z, z1.s, #0
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** ld1w z0.s, p1/z, \[x3, x2, lsl 2\]
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** ...
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*/
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void f12(int * restrict z, int * restrict w, int * restrict x, int * restrict y, int n)
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{
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for (int i = 0; i < n; i++) {
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z[i] = (w[i] > 0) ? w[i] : y[i];
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}
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}
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/* { dg-final { scan-assembler-not {\tbic\t} } } */
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/* { dg-final { scan-assembler-not {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} } } */
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14
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c
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14
gcc/testsuite/gcc.target/aarch64/sve/pred-not-gen-4.c
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@ -0,0 +1,14 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O3 --save-temps" } */
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#include <math.h>
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void f13(double * restrict z, double * restrict w, double * restrict x, double * restrict y, int n)
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{
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for (int i = 0; i < n; i++) {
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z[i] = (isunordered(w[i], 0)) ? x[i] + w[i] : y[i] - w[i];
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}
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}
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/* { dg-final { scan-assembler-not {\tbic\t} } } */
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/* { dg-final { scan-assembler-times {\tnot\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b\n} 1 } } */
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