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backport: target-supports.exp (check_sse_os_support_available): New proc. 

Backport from mainline:
	2010-07-19  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	* lib/target-supports.exp (check_sse_os_support_available): New
	proc.
	(check_sse_hw_available): New proc.
	(check_effective_target_sse_runtime): New proc.
	(check_effective_target_sse2_runtime): New proc.
	* lib/fortran-torture.exp (get-fortran-torture-options): Only add
	-msse2 if check_sse_os_support_available.
	* g++.dg/vect/vect.exp: Only run -msse2 tests if
	check_sse_os_support_available.
	* gcc.dg/vect/vect.exp: Likewise.
	* gfortran.dg/vect/vect.exp: Likewise.
	* gcc.target/i386/sol2-check: Renamed to ...
	* gcc.target/i386/sse-os-support.h: ... this.
	(sol2_check): Renamed to ...
	(sse_os_support): ... this.
	Only test movss with xmm registers.
	* gcc.target/i386/sse-check.h: Reflect new header and function names.
	Removed ILL_INSN, ILL_INSN_LEN.
	* gcc.target/i386/sse2-check.h: Likewise.
	* gcc.target/i386/sse3-check.h: Likewise.
	* gcc.dg/pr40550.c: Use dg-require-effective-target sse_runtime.
	Removed cpuid.h, __get_cpuid test.
	* g++.dg/other/i386-1.C: Use dg-require-effective-target sse2_runtime.
	Removed cpuid.h, __get_cpuid test.
	* g++.dg/other/pr40446.C: Likewise.
	* gcc.dg/compat/union-m128-1_main.c: Likewise.
	* gcc.dg/compat/vector-1a_main.c: Likewise.
	* gcc.dg/compat/vector-2a_main.c: Likewise.
	* gcc.dg/pr36584.c: Likewise.
	* gcc.dg/pr37544.c: Likewise.
	* gcc.dg/torture/pr16104-1.c: Likewise.
	* gcc.dg/torture/stackalign/alloca-2.c: Likewise.
	* gcc.dg/torture/stackalign/alloca-3.c: Likewise.
	* gcc.dg/torture/stackalign/push-1.c: Likewise.
	* gcc.dg/torture/stackalign/vararg-3.c: Likewise.
	* gcc.dg/torture/pr35771.h: Removed cpuid.h, __get_cpuid test.
	* gcc.dg/torture/pr35771-1.c: Use dg-require-effective-target
	sse2_runtime.
	* gcc.dg/torture/pr35771-2.c: Likewise.
	* gcc.dg/torture/pr35771-3.c: Likewise.

From-SVN: r162376
This commit is contained in:
Rainer Orth 2010-07-21 14:37:33 +00:00 committed by Rainer Orth
parent 5dfd37c784
commit e3a8dd06bb
27 changed files with 166 additions and 192 deletions
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46
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,49 @@
2010-07-21 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
Backport from mainline:
2010-07-19 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* lib/target-supports.exp (check_sse_os_support_available): New
proc.
(check_sse_hw_available): New proc.
(check_effective_target_sse_runtime): New proc.
(check_effective_target_sse2_runtime): New proc.
* lib/fortran-torture.exp (get-fortran-torture-options): Only add
-msse2 if check_sse_os_support_available.
* g++.dg/vect/vect.exp: Only run -msse2 tests if
check_sse_os_support_available.
* gcc.dg/vect/vect.exp: Likewise.
* gfortran.dg/vect/vect.exp: Likewise.
* gcc.target/i386/sol2-check: Renamed to ...
* gcc.target/i386/sse-os-support.h: ... this.
(sol2_check): Renamed to ...
(sse_os_support): ... this.
Only test movss with xmm registers.
* gcc.target/i386/sse-check.h: Reflect new header and function names.
Removed ILL_INSN, ILL_INSN_LEN.
* gcc.target/i386/sse2-check.h: Likewise.
* gcc.target/i386/sse3-check.h: Likewise.
* gcc.dg/pr40550.c: Use dg-require-effective-target sse_runtime.
Removed cpuid.h, __get_cpuid test.
* g++.dg/other/i386-1.C: Use dg-require-effective-target sse2_runtime.
Removed cpuid.h, __get_cpuid test.
* g++.dg/other/pr40446.C: Likewise.
* gcc.dg/compat/union-m128-1_main.c: Likewise.
* gcc.dg/compat/vector-1a_main.c: Likewise.
* gcc.dg/compat/vector-2a_main.c: Likewise.
* gcc.dg/pr36584.c: Likewise.
* gcc.dg/pr37544.c: Likewise.
* gcc.dg/torture/pr16104-1.c: Likewise.
* gcc.dg/torture/stackalign/alloca-2.c: Likewise.
* gcc.dg/torture/stackalign/alloca-3.c: Likewise.
* gcc.dg/torture/stackalign/push-1.c: Likewise.
* gcc.dg/torture/stackalign/vararg-3.c: Likewise.
* gcc.dg/torture/pr35771.h: Removed cpuid.h, __get_cpuid test.
* gcc.dg/torture/pr35771-1.c: Use dg-require-effective-target
sse2_runtime.
* gcc.dg/torture/pr35771-2.c: Likewise.
* gcc.dg/torture/pr35771-3.c: Likewise.
2010-07-21 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
Backport from mainline:

13
gcc/testsuite/g++.dg/other/i386-1.C
View File

@ -1,11 +1,10 @@
/* { dg-do run { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
#include <xmmintrin.h>
#include "cpuid.h"
static void
sse2_test (void)
{
@ -25,14 +24,6 @@ sse2_test (void)
int
main ()
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
sse2_test ();
sse2_test ();
return 0;
}

12
gcc/testsuite/g++.dg/other/pr40446.C
View File

@ -2,9 +2,9 @@
// { dg-do run { target i?86-*-* x86_64-*-* } }
// { dg-options "-O1 -msse2" }
// { dg-require-effective-target sse2 }
// { dg-require-effective-target sse2_runtime }
#include <emmintrin.h>
#include "cpuid.h"
extern "C" void abort ();
@ -34,14 +34,6 @@ sse2_test ()
int
main ()
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
sse2_test ();
sse2_test ();
return 0;
}

2
gcc/testsuite/g++.dg/vect/vect.exp
View File

@ -75,7 +75,7 @@ if [istarget "powerpc-*paired*"] {
return
}
lappend DEFAULT_VECTCFLAGS "-msse2"
if [check_sse2_hw_available] {
if { [check_sse2_hw_available] && [check_sse_os_support_available] } {
set dg-do-what-default run
} else {
set dg-do-what-default compile

13
gcc/testsuite/gcc.dg/compat/union-m128-1_main.c
View File

@ -1,8 +1,7 @@
/* { dg-skip-if "test SSE2 support" { ! { i?86-*-* x86_64-*-* } } } */
/* { dg-options "-O" } */
/* { dg-require-effective-target sse2 } */
#include "cpuid.h"
/* { dg-require-effective-target sse2_runtime } */
/* Test function argument passing. PR target/15301. */
@ -12,14 +11,6 @@ extern void exit (int);
int
main ()
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE vector test only if host has SSE2 support. */
if (edx & bit_SSE2)
union_m128_1_x ();
union_m128_1_x ();
exit (0);
}

13
gcc/testsuite/gcc.dg/compat/vector-1a_main.c
View File

@ -1,12 +1,11 @@
/* { dg-skip-if "test SSE2 vector" { ! { i?86-*-* x86_64-*-* } } } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
/* Test compatibility of vector types: layout between separately-compiled
modules, parameter passing, and function return. This test uses
vectors of integer values. */
#include "cpuid.h"
extern void vector_1_x (void);
extern void exit (int);
int fails;
@ -14,14 +13,6 @@ int fails;
int
main ()
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE vector test only if host has SSE2 support. */
if (edx & bit_SSE2)
vector_1_x ();
vector_1_x ();
exit (0);
}

13
gcc/testsuite/gcc.dg/compat/vector-2a_main.c
View File

@ -1,12 +1,11 @@
/* { dg-skip-if "test SSE2 support" { ! { i?86-*-* x86_64-*-* } } } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
/* Test compatibility of vector types: layout between separately-compiled
modules, parameter passing, and function return. This test uses
vectors of floating points values. */
#include "cpuid.h"
extern void vector_2_x (void);
extern void exit (int);
int fails;
@ -14,14 +13,6 @@ int fails;
int
main ()
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE vector test only if host has SSE2 support. */
if (edx & bit_SSE2)
vector_2_x ();
vector_2_x ();
exit (0);
}

15
gcc/testsuite/gcc.dg/pr36584.c
View File

@ -2,10 +2,7 @@
/* { dg-options "-O2 -lm" } */
/* { dg-options "-O2 -msse2 -mfpmath=sse" { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
/* { dg-require-effective-target sse2 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
#ifdef __i386__
#include "cpuid.h"
#endif
/* { dg-require-effective-target sse2_runtime { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
extern double fabs (double);
extern void abort (void);
@ -263,16 +260,6 @@ main ()
double roots[7];
int nroots;
#ifdef __i386__
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
if (!(edx & bit_SSE2))
return 0;
#endif
nroots = sbisect (6, sseq, 0.0, 10000000.0, 5, 1, roots);
if (nroots != 4)
abort ();

16
gcc/testsuite/gcc.dg/pr37544.c
View File

@ -2,10 +2,7 @@
/* { dg-options "-O2" } */
/* { dg-options "-O2 -msse2 -mtune=core2 -mfpmath=387" { target { i?86-*-* x86_64-*-* } } } */
/* { dg-require-effective-target sse2 { target { i?86-*-* x86_64-*-* } } } */
#ifdef __i386__
#include "cpuid.h"
#endif
/* { dg-require-effective-target sse2_runtime { target { i?86-*-* x86_64-*-* } } } */
extern void abort (void);
@ -16,17 +13,6 @@ int main(void)
int i;
#ifdef __i386__
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (!(edx & bit_SSE2))
return 0;
#endif
for (i = 0; i < 1000; i++)
arr[i] = 4294967296.0 + (double)i;

17
gcc/testsuite/gcc.dg/pr40550.c
View File

@ -1,10 +1,7 @@
/* { dg-do run } */
/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
/* { dg-require-effective-target sse { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
#ifdef __i386__
#include "cpuid.h"
#endif
/* { dg-require-effective-target sse_runtime { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
typedef float v2sf __attribute__ ((vector_size (2 * sizeof(float))));
@ -18,18 +15,6 @@ static void test (void)
int main ()
{
#ifdef __i386__
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
if (!(edx & bit_SSE))
return 0;
#endif
test ();
return 0;
}

13
gcc/testsuite/gcc.dg/torture/pr16104-1.c
View File

@ -2,8 +2,7 @@
/* { dg-do run { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
#include "cpuid.h"
/* { dg-require-effective-target sse2_runtime } */
extern void abort (void);
@ -76,14 +75,6 @@ do_test (void)
int
main (void)
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
do_test ();
do_test ();
return 0;
}

1
gcc/testsuite/gcc.dg/torture/pr35771-1.c
View File

@ -1,6 +1,7 @@
/* { dg-do run { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));

1
gcc/testsuite/gcc.dg/torture/pr35771-2.c
View File

@ -1,6 +1,7 @@
/* { dg-do run { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));

1
gcc/testsuite/gcc.dg/torture/pr35771-3.c
View File

@ -1,6 +1,7 @@
/* { dg-do run { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));

12
gcc/testsuite/gcc.dg/torture/pr35771.h
View File

@ -1,7 +1,5 @@
typedef TYPE __attribute__((aligned(1))) unaligned;
#include "cpuid.h"
extern void abort (void);
@ -27,14 +25,6 @@ do_test (void)
int
main (void)
{
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
do_test ();
do_test ();
return 0;
}

11
gcc/testsuite/gcc.dg/torture/stackalign/alloca-2.c
View File

@ -2,9 +2,9 @@
/* { dg-do run { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
#include <emmintrin.h>
#include "cpuid.h"
#include "check.h"
#ifndef ALIGNMENT
@ -44,14 +44,7 @@ int
main (void)
{
__m128 x = { 1.0 };
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
foo (x, x, x, 5);
foo (x, x, x, 5);
return 0;
}

11
gcc/testsuite/gcc.dg/torture/stackalign/alloca-3.c
View File

@ -2,9 +2,9 @@
/* { dg-do run { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
#include <emmintrin.h>
#include "cpuid.h"
#include "check.h"
#ifndef ALIGNMENT
@ -44,14 +44,7 @@ int
main (void)
{
__m128 x = { 1.0 };
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
foo (x, x, x, x, 5);
foo (x, x, x, x, 5);
return 0;
}

16
gcc/testsuite/gcc.dg/torture/stackalign/push-1.c
View File

@ -2,9 +2,9 @@
/* { dg-do run { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
/* { dg-options "-msse2 -mpreferred-stack-boundary=2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
#include <emmintrin.h>
#include "cpuid.h"
typedef __PTRDIFF_TYPE__ ptrdiff_t;
typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
@ -42,19 +42,11 @@ int
main (void)
{
__m128 x = { 1.0 };
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
{
foo (x, x, x, x, 5);
foo (x, x, x, x, 5);
if (__builtin_memcmp (&r, &x, sizeof (r)))
abort ();
}
if (__builtin_memcmp (&r, &x, sizeof (r)))
abort ();
return 0;
}

10
gcc/testsuite/gcc.dg/torture/stackalign/vararg-3.c
View File

@ -2,10 +2,10 @@
/* { dg-do run { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
/* { dg-options "-msse2" } */
/* { dg-require-effective-target sse2 } */
/* { dg-require-effective-target sse2_runtime } */
#include <stdarg.h>
#include <emmintrin.h>
#include "cpuid.h"
#include "check.h"
#ifndef ALIGNMENT
@ -72,14 +72,8 @@ int
main (void)
{
__m128 x = { 1.0 };
unsigned int eax, ebx, ecx, edx;
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if (edx & bit_SSE2)
foo ("foo", 5, 5.0, x);
foo ("foo", 5, 5.0, x);
return 0;
}

2
gcc/testsuite/gcc.dg/vect/vect.exp
View File

@ -67,7 +67,7 @@ if [istarget "powerpc-*paired*"] {
return
}
lappend DEFAULT_VECTCFLAGS "-msse2"
if [check_sse2_hw_available] {
if { [check_sse2_hw_available] && [check_sse_os_support_available] } {
set dg-do-what-default run
} else {
set dg-do-what-default compile

10
gcc/testsuite/gcc.target/i386/sse-check.h
View File

@ -1,13 +1,7 @@
#include <stdlib.h>
#include "m128-check.h"
#include "cpuid.h"
/* We need a single SSE instruction here so the handler can safely skip
over it. */
#define ILL_INSN __asm__ volatile ("movss %xmm2,%xmm1")
#define ILL_INSN_LEN 4
#include "sol2-check.h"
#include "sse-os-support.h"
static void sse_test (void);
@ -20,7 +14,7 @@ main ()
return 0;
/* Run SSE test only if host has SSE support. */
if ((edx & bit_SSE) && sol2_check ())
if ((edx & bit_SSE) && sse_os_support ())
sse_test ();
return 0;

19
gcc/testsuite/gcc.target/i386/sol2-check.h → gcc/testsuite/gcc.target/i386/sse-os-support.h
View File

@ -14,18 +14,23 @@ sigill_hdlr (int sig __attribute((unused)),
sigill_caught = 1;
/* Set PC to the instruction after the faulting one to skip over it,
otherwise we enter an infinite loop. */
ucp->uc_mcontext.gregs[EIP] += ILL_INSN_LEN;
ucp->uc_mcontext.gregs[EIP] += 4;
setcontext (ucp);
}
#endif
/* Solaris 2 before Solaris 9 4/04 cannot execute SSE/SSE2 instructions
even if the CPU supports them. Programs receive SIGILL instead, so
check for that at runtime. */
/* Check if the OS supports executing SSE instructions. This function is
only used in sse-check.h, sse2-check.h, and sse3-check.h so far since
Solaris 8 and 9 won't run on newer CPUs anyway. */
static int
sol2_check (void)
sse_os_support (void)
{
#if defined(__sun__) && defined(__svr4__)
/* Solaris 2 before Solaris 9 4/04 cannot execute SSE instructions
even if the CPU supports them. Programs receive SIGILL instead, so
check for that at runtime. */
struct sigaction act, oact;
act.sa_handler = sigill_hdlr;
@ -34,7 +39,9 @@ sol2_check (void)
act.sa_flags = SA_SIGINFO;
sigaction (SIGILL, &act, &oact);
ILL_INSN;
/* We need a single SSE instruction here so the handler can safely skip
over it. */
__asm__ volatile ("movss %xmm2,%xmm1");
sigaction (SIGILL, &oact, NULL);

9
gcc/testsuite/gcc.target/i386/sse2-check.h
View File

@ -1,12 +1,7 @@
#include <stdlib.h>
#include "cpuid.h"
#include "m128-check.h"
/* We need a single SSE2 instruction here so the handler can safely skip
over it. */
#define ILL_INSN __asm__ volatile ("unpcklpd %xmm0,%xmm2")
#define ILL_INSN_LEN 4
#include "sol2-check.h"
#include "sse-os-support.h"
static void sse2_test (void);
@ -19,7 +14,7 @@ main ()
return 0;
/* Run SSE2 test only if host has SSE2 support. */
if ((edx & bit_SSE2) && sol2_check ())
if ((edx & bit_SSE2) && sse_os_support ())
sse2_test ();
return 0;

10
gcc/testsuite/gcc.target/i386/sse3-check.h
View File

@ -1,13 +1,7 @@
#include <stdio.h>
#include <stdlib.h>
#include "cpuid.h"
/* We need a single SSE3 instruction here so the handler can safely skip
over it. */
#define ILL_INSN __asm__ volatile ("movddup %xmm1,%xmm2")
#define ILL_INSN_LEN 4
#include "sol2-check.h"
#include "sse-os-support.h"
static void sse3_test (void);
@ -20,7 +14,7 @@ main ()
return 0;
/* Run SSE3 test only if host has SSE3 support. */
if ((ecx & bit_SSE3) && sol2_check ())
if ((ecx & bit_SSE3) && sse_os_support ())
sse3_test ();
return 0;

2
gcc/testsuite/gfortran.dg/vect/vect.exp
View File

@ -68,7 +68,7 @@ if [istarget "powerpc-*paired*"] {
return
}
lappend DEFAULT_VECTCFLAGS "-msse2"
if [check_sse2_hw_available] {
if { [check_sse2_hw_available] && [check_sse_os_support_available] } {
set dg-do-what-default run
} else {
set dg-do-what-default compile

3
gcc/testsuite/lib/fortran-torture.exp
View File

@ -46,7 +46,8 @@ proc get-fortran-torture-options { } {
set test_tree_vectorize 1
} elseif { ( [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] )
&& [check_effective_target_sse2]
&& [check_sse2_hw_available] } {
&& [check_sse2_hw_available]
&& [check_sse_os_support_available] } {
lappend vectorizer_options "-msse2"
set test_tree_vectorize 1
} elseif { [istarget "mips*-*-*"]

67
gcc/testsuite/lib/target-supports.exp
View File

@ -856,6 +856,53 @@ proc check_750cl_hw_available { } {
}]
}
# Return 1 if the target OS supports running SSE executables, 0
# otherwise. Cache the result.
proc check_sse_os_support_available { } {
return [check_cached_effective_target sse_os_support_available {
# If this is not the right target then we can skip the test.
if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
expr 0
} elseif { [istarget i?86-*-solaris2*] } {
# The Solaris 2 kernel doesn't save and restore SSE registers
# before Solaris 9 4/04. Before that, executables die with SIGILL.
check_runtime_nocache sse_os_support_available {
int main ()
{
__asm__ volatile ("movss %xmm2,%xmm1");
return 0;
}
} "-msse"
} else {
expr 1
}
}]
}
# Return 1 if the target supports executing SSE instructions, 0
# otherwise. Cache the result.
proc check_sse_hw_available { } {
return [check_cached_effective_target sse_hw_available {
# If this is not the right target then we can skip the test.
if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
expr 0
} else {
check_runtime_nocache sse_hw_available {
#include "cpuid.h"
int main ()
{
unsigned int eax, ebx, ecx, edx = 0;
if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
return !(edx & bit_SSE);
return 1;
}
} ""
}
}]
}
# Return 1 if the target supports executing SSE2 instructions, 0
# otherwise. Cache the result.
@ -879,6 +926,26 @@ proc check_sse2_hw_available { } {
}]
}
# Return 1 if the target supports running SSE executables, 0 otherwise.
proc check_effective_target_sse_runtime { } {
if { [check_sse_hw_available] && [check_sse_os_support_available] } {
return 1
} else {
return 0
}
}
# Return 1 if the target supports running SSE2 executables, 0 otherwise.
proc check_effective_target_sse2_runtime { } {
if { [check_sse2_hw_available] && [check_sse_os_support_available] } {
return 1
} else {
return 0
}
}
# Return 1 if the target supports executing AltiVec instructions, 0
# otherwise. Cache the result.