tilegx.md (insn_mnz_<mode>): Replaced by ...
* config/tilegx/tilegx.md (insn_mnz_<mode>): Replaced by ... (insn_mnz_v8qi): ... this ... (insn_mnz_v4hi): ... and this. Replace (const_int 0) with the vector equivalent. (insn_v<n>mnz): Replaced by ... (insn_v1mnz): ... this ... (insn_v2mnz): ... and this. Replace (const_int 0) with the vector equivalent. (insn_mz_<mode>): Replaced by ... (insn_mz_v8qi): ... this ... (insn_mz_v4hi): ... and this. Replace (const_int 0) with the vector equivalent. (insn_v<n>mz): Replaced by ... (insn_v1mz): ... this ... (insn_v2mz): ... and this. Replace (const_int 0) with the vector equivalent. From-SVN: r197135
This commit is contained in:
Walter Lee
Walter Lee
parent
591cb3cfed
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e3b51eeba1
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2013-03-27 Walter Lee <walt@tilera.com>
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* config/tilegx/tilegx.md (insn_mnz_<mode>): Replaced by ...
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(insn_mnz_v8qi): ... this ...
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(insn_mnz_v4hi): ... and this. Replace (const_int 0) with the
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vector equivalent.
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(insn_v<n>mnz): Replaced by ...
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(insn_v1mnz): ... this ...
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(insn_v2mnz): ... and this. Replace (const_int 0) with the vector
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equivalent.
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(insn_mz_<mode>): Replaced by ...
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(insn_mz_v8qi): ... this ...
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(insn_mz_v4hi): ... and this. Replace (const_int 0) with the
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vector equivalent.
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(insn_v<n>mz): Replaced by ...
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(insn_v1mz): ... this ...
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(insn_v2mz): ... and this. Replace (const_int 0) with the vector
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equivalent.
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2013-03-26 Eric Botcazou <ebotcazou@adacore.com>
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* doc/invoke.texi (SPARC options): Remove -mlittle-endian.
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@ -4597,57 +4597,147 @@
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;; insn_v1mz
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;; insn_v2mnz
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;; insn_v2mz
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(define_insn "insn_mnz_<mode>"
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[(set (match_operand:VEC48MODE 0 "register_operand" "=r")
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(if_then_else:VEC48MODE
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(ne:VEC48MODE
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(match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
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(const_int 0))
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(match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")
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(const_int 0)))]
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(define_insn "insn_mnz_v8qi"
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[(set (match_operand:V8QI 0 "register_operand" "=r")
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(if_then_else:V8QI
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(ne:V8QI
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(match_operand:V8QI 1 "reg_or_0_operand" "rO")
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)]))
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(match_operand:V8QI 2 "reg_or_0_operand" "rO")
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])))]
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""
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"v<n>mnz\t%0, %r1, %r2"
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"v1mnz\t%0, %r1, %r2"
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[(set_attr "type" "X01")])
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(define_expand "insn_v<n>mnz"
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(define_expand "insn_v1mnz"
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[(set (match_operand:DI 0 "register_operand" "")
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(if_then_else:VEC48MODE
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(ne:VEC48MODE
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(if_then_else:V8QI
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(ne:V8QI
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(match_operand:DI 1 "reg_or_0_operand" "")
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(const_int 0))
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])
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)
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(match_operand:DI 2 "reg_or_0_operand" "")
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(const_int 0)))]
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])))]
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""
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{
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tilegx_expand_builtin_vector_binop (gen_insn_mnz_<mode>, <MODE>mode,
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operands[0], <MODE>mode, operands[1],
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tilegx_expand_builtin_vector_binop (gen_insn_mnz_v8qi, V8QImode,
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operands[0], V8QImode, operands[1],
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operands[2], true);
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DONE;
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})
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(define_insn "insn_mz_<mode>"
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[(set (match_operand:VEC48MODE 0 "register_operand" "=r")
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(if_then_else:VEC48MODE
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(ne:VEC48MODE
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(match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
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(const_int 0))
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(const_int 0)
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(match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")))]
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(define_insn "insn_mz_v8qi"
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[(set (match_operand:V8QI 0 "register_operand" "=r")
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(if_then_else:V8QI
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(ne:V8QI
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(match_operand:V8QI 1 "reg_or_0_operand" "rO")
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)]))
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])
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(match_operand:V8QI 2 "reg_or_0_operand" "rO")))]
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""
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"v<n>mz\t%0, %r1, %r2"
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"v1mz\t%0, %r1, %r2"
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[(set_attr "type" "X01")])
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(define_expand "insn_v<n>mz"
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(define_expand "insn_v1mz"
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[(set (match_operand:DI 0 "register_operand" "")
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(if_then_else:VEC48MODE
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(ne:VEC48MODE
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(if_then_else:V8QI
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(ne:V8QI
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(match_operand:DI 1 "reg_or_0_operand" "")
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(const_int 0))
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(const_int 0)
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)]))
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(const_vector:V8QI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])
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(match_operand:DI 2 "reg_or_0_operand" "")))]
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""
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{
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tilegx_expand_builtin_vector_binop (gen_insn_mz_<mode>, <MODE>mode,
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operands[0], <MODE>mode, operands[1],
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tilegx_expand_builtin_vector_binop (gen_insn_mz_v8qi, V8QImode,
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operands[0], V8QImode, operands[1],
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operands[2], true);
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DONE;
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})
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(define_insn "insn_mnz_v4hi"
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[(set (match_operand:V4HI 0 "register_operand" "=r")
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(if_then_else:V4HI
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(ne:V4HI
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(match_operand:V4HI 1 "reg_or_0_operand" "rO")
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)]))
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(match_operand:V4HI 2 "reg_or_0_operand" "rO")
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])))]
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""
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"v2mnz\t%0, %r1, %r2"
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[(set_attr "type" "X01")])
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(define_expand "insn_v2mnz"
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[(set (match_operand:DI 0 "register_operand" "")
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(if_then_else:V4HI
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(ne:V4HI
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(match_operand:DI 1 "reg_or_0_operand" "")
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)]))
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(match_operand:DI 2 "reg_or_0_operand" "")
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])))]
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""
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{
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tilegx_expand_builtin_vector_binop (gen_insn_mnz_v4hi, V4HImode,
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operands[0], V4HImode, operands[1],
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operands[2], true);
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DONE;
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})
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(define_insn "insn_mz_v4hi"
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[(set (match_operand:V4HI 0 "register_operand" "=r")
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(if_then_else:V4HI
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(ne:V4HI
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(match_operand:V4HI 1 "reg_or_0_operand" "rO")
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)]))
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])
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(match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
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""
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"v2mz\t%0, %r1, %r2"
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[(set_attr "type" "X01")])
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(define_expand "insn_v2mz"
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[(set (match_operand:DI 0 "register_operand" "")
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(if_then_else:V4HI
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(ne:V4HI
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(match_operand:DI 1 "reg_or_0_operand" "")
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)]))
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(const_vector:V4HI [(const_int 0) (const_int 0)
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(const_int 0) (const_int 0)])
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(match_operand:DI 2 "reg_or_0_operand" "")))]
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""
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{
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tilegx_expand_builtin_vector_binop (gen_insn_mz_v4hi, V4HImode,
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operands[0], V4HImode, operands[1],
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operands[2], true);
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DONE;
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})
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