[PATCH] Fix undefined behaviour in SH port
* config/sh/sh.c (gen_shl_and): Fix undefined left shift behaviour. (gen_shl_sext): Likewise. * config/sh/sh.md (divsi3): Likewise. (imm->ext_dest_operand splitter): Likewise. From-SVN: r228257
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2015-09-29 Jeff Law <law@redhat.com>
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* config/sh/sh.c (gen_shl_and): Fix undefined left shift
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behaviour.
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(gen_shl_sext): Likewise.
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* config/sh/sh.md (divsi3): Likewise.
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(imm->ext_dest_operand splitter): Likewise.
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2015-09-29 Sebastian Pop <s.pop@samsung.com>
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2015-09-29 Sebastian Pop <s.pop@samsung.com>
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Aditya Kumar <aditya.k7@samsung.com>
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Aditya Kumar <aditya.k7@samsung.com>
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@ -4342,7 +4342,7 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
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that don't matter. This way, we might be able to get a shorter
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that don't matter. This way, we might be able to get a shorter
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signed constant. */
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signed constant. */
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if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
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if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
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mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
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mask |= (HOST_WIDE_INT) ((HOST_WIDE_INT_M1U) << (31 - total_shift));
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case 2:
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case 2:
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/* Don't expand fine-grained when combining, because that will
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/* Don't expand fine-grained when combining, because that will
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make the pattern fail. */
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make the pattern fail. */
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@ -4626,7 +4626,7 @@ gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
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}
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}
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emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
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emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
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emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
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emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
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emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
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emit_insn (gen_addsi3 (dest, dest, GEN_INT (HOST_WIDE_INT_M1U << (insize - 1))));
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operands[0] = dest;
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operands[0] = dest;
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operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
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operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
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gen_shifty_op (ASHIFT, operands);
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gen_shifty_op (ASHIFT, operands);
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@ -3052,7 +3052,7 @@
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tab_base = force_reg (DImode, tab_base);
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tab_base = force_reg (DImode, tab_base);
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}
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}
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if (TARGET_DIVIDE_INV20U)
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if (TARGET_DIVIDE_INV20U)
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i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
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i2p27 = force_reg (DImode, GEN_INT ((unsigned HOST_WIDE_INT)-2 << 27));
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else
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else
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i2p27 = GEN_INT (0);
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i2p27 = GEN_INT (0);
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if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
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if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
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@ -7875,7 +7875,7 @@ label:
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break;
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break;
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}
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}
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/* Try movi / mshflo.l w/ r63. */
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/* Try movi / mshflo.l w/ r63. */
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val2 = val + ((HOST_WIDE_INT) -1 << 32);
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val2 = val + ((HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 32));
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if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
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if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
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{
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{
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operands[1] = gen_mshflo_l_di (operands[0], operands[0],
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operands[1] = gen_mshflo_l_di (operands[0], operands[0],
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