re PR target/80799 (x86-32 bits generates MMX without EMMS)
PR target/80799 * config/i386/mmx.md (*mov<mode>_internal): Enable alternatives 11, 12, 13 and 14 also for 32bit targets. Remove alternatives 15, 16, 17 and 18. * config/i386/sse.md (vec_concatv2di): Change alternative (!x, *y) to (x, ?!*Yn). testsuite/ChangeLog: PR target/80799 * g++.dg/other/i386-11.C: New test. From-SVN: r248246
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Uros Bizjak
Uros Bizjak
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@ -1,3 +1,12 @@
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2017-05-18 Uros Bizjak <ubizjak@gmail.com>
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PR target/80799
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* config/i386/mmx.md (*mov<mode>_internal): Enable
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alternatives 11, 12, 13 and 14 also for 32bit targets.
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Remove alternatives 15, 16, 17 and 18.
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* config/i386/sse.md (vec_concatv2di): Change
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alternative (!x, *y) to (x, ?!*Yn).
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2017-05-18 Paolo Carlini <paolo.carlini@oracle.com>
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* dumpfile.h (enum dump_kind): Remove stray comma.
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@ -280,7 +289,7 @@
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2017-05-16 Uros Bizjak <ubizjak@gmail.com>
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* config/i386.i386.md (*movsi_internal): Split (?rm,*y) alternative
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* config/i386/i386.md (*movsi_internal): Split (?rm,*y) alternative
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to (?r,*Yn) and (?m,*y) alternatives, and (?*y,rm) to (?*Ym,r)
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and (?*y,m). Update insn attributes.
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@ -78,9 +78,9 @@
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(define_insn "*mov<mode>_internal"
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[(set (match_operand:MMXMODE 0 "nonimmediate_operand"
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"=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!Ym,v,v,v,m,*x,*x,*x,m ,r ,Yi,!Ym,*Yi")
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"=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!Ym,v,v,v,m,r ,Yi,!Ym,*Yi")
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(match_operand:MMXMODE 1 "vector_move_operand"
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"rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!Yn,r ,C,v,m,v,C ,*x,m ,*x,Yj,r ,*Yj,!Yn"))]
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"rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!Yn,r ,C,v,m,v,Yj,r ,*Yj,!Yn"))]
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"TARGET_MMX
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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@ -146,7 +146,7 @@
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "nox64")
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(eq_attr "alternative" "2,3,4,9,10,11,12,13,14,19,20")
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(eq_attr "alternative" "2,3,4,9,10,15,16")
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(const_string "x64")
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]
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(const_string "*")))
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@ -159,14 +159,14 @@
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(const_string "mmx")
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(eq_attr "alternative" "6,7,8,9,10")
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(const_string "mmxmov")
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(eq_attr "alternative" "11,15")
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(eq_attr "alternative" "11")
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(const_string "sselog1")
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(eq_attr "alternative" "21,22")
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(eq_attr "alternative" "17,18")
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(const_string "ssecvt")
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]
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(const_string "ssemov")))
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(set (attr "prefix_rex")
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(if_then_else (eq_attr "alternative" "9,10,19,20")
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(if_then_else (eq_attr "alternative" "9,10,15,16")
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix")
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@ -181,7 +181,7 @@
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(set (attr "mode")
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(cond [(eq_attr "alternative" "2")
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(const_string "SI")
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(eq_attr "alternative" "11,12,15,16")
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(eq_attr "alternative" "11,12")
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(cond [(ior (match_operand 0 "ext_sse_reg_operand")
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(match_operand 1 "ext_sse_reg_operand"))
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(const_string "XI")
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@ -197,7 +197,7 @@
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]
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(const_string "TI"))
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(and (eq_attr "alternative" "13,14,17,18")
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(and (eq_attr "alternative" "13,14")
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(ior (match_test "<MODE>mode == V2SFmode")
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(not (match_test "TARGET_SSE2"))))
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(const_string "V2SF")
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@ -13863,10 +13863,10 @@
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;; movd instead of movq is required to handle broken assemblers.
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(define_insn "vec_concatv2di"
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[(set (match_operand:V2DI 0 "register_operand"
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"=Yr,*x,x ,v ,Yi,v ,!x,x,v ,x,x,v")
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"=Yr,*x,x ,v ,Yi,v ,x ,x,v ,x,x,v")
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(vec_concat:V2DI
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(match_operand:DI 1 "nonimmediate_operand"
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" 0, 0,x ,Yv,r ,vm,*y,0,Yv,0,0,v")
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" 0, 0,x ,Yv,r ,vm,?!*Yn,0,Yv,0,0,v")
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(match_operand:DI 2 "vector_move_operand"
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"*rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))]
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"TARGET_SSE"
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@ -1,3 +1,8 @@
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2017-05-18 Uros Bizjak <ubizjak@gmail.com>
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PR target/80799
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* g++.dg/other/i386-11.C: New test.
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2017-05-18 Will Schmidt <will_schmidt@vnet.ibm.com>
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* fold-vec-div-float.c: Update dg-requires and dg-options statements.
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57
gcc/testsuite/g++.dg/other/i386-11.C
Normal file
57
gcc/testsuite/g++.dg/other/i386-11.C
Normal file
@ -0,0 +1,57 @@
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// PR target/80799
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// { dg-do compile { target i?86-*-* x86_64-*-* } }
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// { dg-require-effective-target c++11 }
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// { dg-options "-O2 -msse2" }
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#include <xmmintrin.h>
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#include <emmintrin.h>
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class alignas(16) GSVector4i
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{
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public:
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__m128i m;
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explicit GSVector4i(__m128i m)
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{
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this->m = m;
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}
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static void storel(void* p, const GSVector4i& v)
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{
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_mm_storel_epi64((__m128i*)p, v.m);
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}
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static GSVector4i loadl(const void* p)
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{
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return GSVector4i(_mm_loadl_epi64((__m128i*)p));
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}
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bool eq(const GSVector4i& v) const
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{
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return _mm_movemask_epi8(_mm_cmpeq_epi32(m, v.m)) == 0xffff;
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}
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};
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union GIFRegTRXPOS
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{
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unsigned long long u64;
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void operator = (const GSVector4i& v) {GSVector4i::storel(this, v);}
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bool operator != (const union GIFRegTRXPOS& r) const {return !((GSVector4i)r).eq(*this);}
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operator GSVector4i() const {return GSVector4i::loadl(this);}
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};
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extern void dummy_call();
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extern GIFRegTRXPOS TRXPOS;
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void GIFRegHandlerTRXPOS(const GIFRegTRXPOS& p)
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{
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if(p != TRXPOS)
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{
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dummy_call();
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}
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TRXPOS = (GSVector4i)p;
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}
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// { dg-final { scan-assembler-not "%mm" } }
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