This patch improves the accuracy of the Cortex-A53 integer scheduler...
This patch improves the accuracy of the Cortex-A53 integer scheduler, resulting in performance gains across a wide range of benchmarks. gcc/ * config/arm/cortex-a53.md: Use final_presence_set for in-order. (cortex_a53_shift): Add mov_shift. (cortex_a53_shift_reg): Add new reservation for register shifts. (cortex_a53_alu): Remove bfm. (cortex_a53_alu_shift): Add bfm, remove mov_shift. (cortex_a53_alu_extr): Add new reservation for EXTR. (bypasses): Improve bypass modelling. From-SVN: r238048
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@ -1,3 +1,13 @@
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2016-07-06 Wilco Dijkstra <wdijkstr@arm.com>
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* config/arm/cortex-a53.md: Use final_presence_set for in-order.
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(cortex_a53_shift): Add mov_shift.
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(cortex_a53_shift_reg): Add new reservation for register shifts.
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(cortex_a53_alu): Remove bfm.
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(cortex_a53_alu_shift): Add bfm, remove mov_shift.
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(cortex_a53_alu_extr): Add new reservation for EXTR.
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(bypasses): Improve bypass modelling.
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2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
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PR target/50739
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@ -30,6 +30,7 @@
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(define_cpu_unit "cortex_a53_slot0" "cortex_a53")
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(define_cpu_unit "cortex_a53_slot1" "cortex_a53")
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(final_presence_set "cortex_a53_slot1" "cortex_a53_slot0")
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(define_reservation "cortex_a53_slot_any"
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"cortex_a53_slot0\
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@ -71,41 +72,43 @@
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(define_insn_reservation "cortex_a53_shift" 2
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(and (eq_attr "tune" "cortexa53")
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(eq_attr "type" "adr,shift_imm,shift_reg,mov_imm,mvn_imm"))
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(eq_attr "type" "adr,shift_imm,mov_imm,mvn_imm,mov_shift"))
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"cortex_a53_slot_any")
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(define_insn_reservation "cortex_a53_alu_rotate_imm" 2
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(define_insn_reservation "cortex_a53_shift_reg" 2
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(and (eq_attr "tune" "cortexa53")
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(eq_attr "type" "rotate_imm"))
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"(cortex_a53_slot1)
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| (cortex_a53_single_issue)")
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(eq_attr "type" "shift_reg,mov_shift_reg"))
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"cortex_a53_slot_any+cortex_a53_hazard")
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(define_insn_reservation "cortex_a53_alu" 3
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(and (eq_attr "tune" "cortexa53")
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(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,
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alu_sreg,alus_sreg,logic_reg,logics_reg,
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adc_imm,adcs_imm,adc_reg,adcs_reg,
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bfm,csel,clz,rbit,rev,alu_dsp_reg,
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mov_reg,mvn_reg,
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mrs,multiple,no_insn"))
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csel,clz,rbit,rev,alu_dsp_reg,
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mov_reg,mvn_reg,mrs,multiple,no_insn"))
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"cortex_a53_slot_any")
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(define_insn_reservation "cortex_a53_alu_shift" 3
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(and (eq_attr "tune" "cortexa53")
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(eq_attr "type" "alu_shift_imm,alus_shift_imm,
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crc,logic_shift_imm,logics_shift_imm,
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alu_ext,alus_ext,
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extend,mov_shift,mvn_shift"))
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alu_ext,alus_ext,bfm,extend,mvn_shift"))
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"cortex_a53_slot_any")
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(define_insn_reservation "cortex_a53_alu_shift_reg" 3
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(and (eq_attr "tune" "cortexa53")
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(eq_attr "type" "alu_shift_reg,alus_shift_reg,
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logic_shift_reg,logics_shift_reg,
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mov_shift_reg,mvn_shift_reg"))
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mvn_shift_reg"))
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"cortex_a53_slot_any+cortex_a53_hazard")
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(define_insn_reservation "cortex_a53_mul" 3
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(define_insn_reservation "cortex_a53_alu_extr" 3
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(and (eq_attr "tune" "cortexa53")
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(eq_attr "type" "rotate_imm"))
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"cortex_a53_slot1|cortex_a53_single_issue")
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(define_insn_reservation "cortex_a53_mul" 4
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(and (eq_attr "tune" "cortexa53")
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(ior (eq_attr "mul32" "yes")
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(eq_attr "mul64" "yes")))
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@ -189,49 +192,43 @@
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(define_insn_reservation "cortex_a53_branch" 0
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(and (eq_attr "tune" "cortexa53")
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(eq_attr "type" "branch,call"))
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"cortex_a53_slot_any,cortex_a53_branch")
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"cortex_a53_slot_any+cortex_a53_branch")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; General-purpose register bypasses
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Model bypasses for unshifted operands to ALU instructions.
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;; Model bypasses for ALU to ALU instructions.
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(define_bypass 1 "cortex_a53_shift"
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"cortex_a53_shift")
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(define_bypass 1 "cortex_a53_alu,
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cortex_a53_alu_shift*,
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cortex_a53_alu_rotate_imm,
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cortex_a53_shift"
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(define_bypass 0 "cortex_a53_shift*"
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"cortex_a53_alu")
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(define_bypass 2 "cortex_a53_alu,
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cortex_a53_alu_shift*"
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(define_bypass 1 "cortex_a53_shift*"
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"cortex_a53_shift*,cortex_a53_alu_*")
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(define_bypass 1 "cortex_a53_alu*"
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"cortex_a53_alu")
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(define_bypass 1 "cortex_a53_alu*"
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"cortex_a53_alu_shift*"
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"aarch_forward_to_shift_is_not_shifted_reg")
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;; In our model, we allow any general-purpose register operation to
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;; bypass to the accumulator operand of an integer MADD-like operation.
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(define_bypass 2 "cortex_a53_alu*"
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"cortex_a53_alu_*,cortex_a53_shift*")
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(define_bypass 1 "cortex_a53_alu*,
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cortex_a53_load*,
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cortex_a53_mul"
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;; Model a bypass from MUL/MLA to MLA instructions.
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(define_bypass 1 "cortex_a53_mul"
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"cortex_a53_mul"
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"aarch_accumulator_forwarding")
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;; Model a bypass from MLA/MUL to many ALU instructions.
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;; Model a bypass from MUL/MLA to ALU instructions.
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(define_bypass 2 "cortex_a53_mul"
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"cortex_a53_alu,
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cortex_a53_alu_shift*")
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"cortex_a53_alu")
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;; We get neater schedules by allowing an MLA/MUL to feed an
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;; early load address dependency to a load.
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(define_bypass 2 "cortex_a53_mul"
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"cortex_a53_load*"
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"arm_early_load_addr_dep")
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(define_bypass 3 "cortex_a53_mul"
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"cortex_a53_alu_*,cortex_a53_shift*")
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;; Model bypasses for loads which are to be consumed by the ALU.
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"cortex_a53_alu")
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(define_bypass 3 "cortex_a53_load1"
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"cortex_a53_alu_shift*")
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"cortex_a53_alu_*,cortex_a53_shift*")
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(define_bypass 3 "cortex_a53_load2"
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"cortex_a53_alu")
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;; Model a bypass for ALU instructions feeding stores.
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(define_bypass 1 "cortex_a53_alu*"
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"cortex_a53_store1,
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cortex_a53_store2,
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cortex_a53_store3plus"
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(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
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"cortex_a53_store*"
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"arm_no_early_store_addr_dep")
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;; Model a bypass for load and multiply instructions feeding stores.
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(define_bypass 2 "cortex_a53_mul,
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cortex_a53_load1,
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cortex_a53_load2,
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cortex_a53_load3plus"
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"cortex_a53_store1,
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cortex_a53_store2,
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cortex_a53_store3plus"
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(define_bypass 1 "cortex_a53_mul,
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cortex_a53_load*"
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"cortex_a53_store*"
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"arm_no_early_store_addr_dep")
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;; Model a GP->FP register move as similar to stores.
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(define_bypass 1 "cortex_a53_alu*"
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(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
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"cortex_a53_r2f")
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(define_bypass 2 "cortex_a53_mul,
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cortex_a53_load1,
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cortex_a53_load2,
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cortex_a53_load3plus"
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(define_bypass 1 "cortex_a53_mul,
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cortex_a53_load*"
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"cortex_a53_r2f")
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;; Shifts feeding Load/Store addresses may not be ready in time.
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;; Model flag forwarding to branches.
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(define_bypass 3 "cortex_a53_shift"
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"cortex_a53_load*"
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"arm_early_load_addr_dep")
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(define_bypass 3 "cortex_a53_shift"
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"cortex_a53_store*"
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"arm_early_store_addr_dep")
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(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
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"cortex_a53_branch")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Floating-point/Advanced SIMD.
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