builtins-3.c: Remove ISA 3.0 word variant builtin test cases for vec_mule, and vec_mulo.
gcc/testsuite/ChangeLog: 2017-08-04 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-3.c: Remove ISA 3.0 word variant builtin test cases for vec_mule, and vec_mulo. * gcc.target/powerpc/builtins-3-p8.c: Add ISA 3.0 word variant builtin test cases for vec_mule, and vec_mulo. From-SVN: r250876
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@ -1,3 +1,10 @@
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2017-08-04 Carl Love <cel@us.ibm.com>
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* gcc.target/powerpc/builtins-3.c: Remove ISA 3.0 word variant
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builtin test cases for vec_mule, and vec_mulo.
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* gcc.target/powerpc/builtins-3-p8.c: Add ISA 3.0 word variant
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builtin test cases for vec_mule, and vec_mulo.
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2017-08-04 H.J. Lu <hongjiu.lu@intel.com>
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PR target/81590
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@ -85,6 +85,30 @@ test_vss_mradds_vss_vss (vector signed short x, vector signed short y,
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return vec_mradds (x, y, z);
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}
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vector signed long long
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test_vsll_mule_vsi_vsi (vector signed int x, vector signed int y)
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{
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return vec_mule (x, y);
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}
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vector unsigned long long
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test_vull_mule_vui_vui (vector unsigned int x, vector unsigned int y)
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{
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return vec_mule (x, y);
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}
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vector signed long long
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test_vsll_mulo_vsi_vsi (vector signed int x, vector signed int y)
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{
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return vec_mulo (x, y);
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}
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vector unsigned long long
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test_vull_mulo_vui_vui (vector unsigned int x, vector unsigned int y)
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{
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return vec_mulo (x, y);
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}
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/* Expected test results:
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test_eq_long_long 1 vcmpequd inst
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@ -98,7 +122,12 @@ test_vss_mradds_vss_vss (vector signed short x, vector signed short y,
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test_unsigned_int_popcnt_signed_int 2 vpopcntw
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test_unsigned_int_popcnt_unsigned_int 1 vpopcntd
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test_unsigned_long_long_popcnt_unsigned_long 1 vpopcntd
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test_vss_mradds_vss_vsss 1 vmhraddshs */
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test_vss_mradds_vss_vsss 1 vmhraddshs
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test_vsll_mulo_vsi_vsi 1 vmulosw
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test_vull_mulo_vui_vui 1 vmulouw
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test_vsll_mule_vsi_vsi 1 vmulesw
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test_vull_mule_vui_vui 1 vmuleuw
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*/
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/* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
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/* { dg-final { scan-assembler-times "vpkudum" 1 } } */
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@ -109,3 +138,7 @@ test_vss_mradds_vss_vss (vector signed short x, vector signed short y,
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/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */
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/* { dg-final { scan-assembler-times "vpopcntd" 2 } } */
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/* { dg-final { scan-assembler-times "vmhraddshs" 1 } } */
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/* { dg-final { scan-assembler-times "vmulosw" 1 } } */
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/* { dg-final { scan-assembler-times "vmulouw" 1 } } */
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/* { dg-final { scan-assembler-times "vmulesw" 1 } } */
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/* { dg-final { scan-assembler-times "vmuleuw" 1 } } */
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@ -112,30 +112,6 @@ test_vull_slo_vull_vuc (vector unsigned long long x, vector unsigned char y)
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return vec_slo (x, y);
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}
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vector signed long long
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test_vsll_mule_vsi_vsi (vector signed int x, vector signed int y)
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{
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return vec_mule (x, y);
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}
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vector unsigned long long
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test_vull_mule_vui_vui (vector unsigned int x, vector unsigned int y)
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{
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return vec_mule (x, y);
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}
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vector signed long long
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test_vsll_mulo_vsi_vsi (vector signed int x, vector signed int y)
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{
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return vec_mulo (x, y);
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}
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vector unsigned long long
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test_vull_mulo_vui_vui (vector unsigned int x, vector unsigned int y)
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{
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return vec_mulo (x, y);
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}
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vector signed char
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test_vsc_sldw_vsc_vsc (vector signed char x, vector signed char y)
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{
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@ -207,10 +183,6 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
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test_vsll_slo_vsll_vuc 1 vslo
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test_vull_slo_vsll_vsc 1 vslo
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test_vull_slo_vsll_vuc 1 vslo
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test_vsll_mulo_vsi_vsi 1 vmulosw
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test_vull_mulo_vui_vui 1 vmulouw
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test_vsll_mule_vsi_vsi 1 vmulesw
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test_vull_mule_vui_vui 1 vmuleuw
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test_vsc_mulo_vsc_vsc 1 xxsldwi
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test_vuc_mulo_vuc_vuc 1 xxsldwi
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test_vssi_mulo_vssi_vssi 1 xxsldwi
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@ -236,8 +208,4 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
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/* { dg-final { scan-assembler-times "xvnegsp" 1 } } */
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/* { dg-final { scan-assembler-times "xvnegdp" 1 } } */
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/* { dg-final { scan-assembler-times "vslo" 4 } } */
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/* { dg-final { scan-assembler-times "vmulosw" 1 } } */
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/* { dg-final { scan-assembler-times "vmulouw" 1 } } */
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/* { dg-final { scan-assembler-times "vmulesw" 1 } } */
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/* { dg-final { scan-assembler-times "vmuleuw" 1 } } */
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/* { dg-final { scan-assembler-times "xxsldwi" 8 } } */
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