re PR target/92962 (Documentation: x86 Options - znver2 missing RDPID and WBNOINVD)
PR target/92962 * common/config/i386/i386-common.c (processor_alias_table): Formatting fixes. * doc/invoke.texi (bdver3, bdver4, znver1): Add missing closing paren. (znver2): Likewise. Add RDPID and WBNOINVD, remove spurious comma before CLWB. From-SVN: r279455
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@ -1,3 +1,12 @@
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2019-12-17 Jakub Jelinek <jakub@redhat.com>
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PR target/92962
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* common/config/i386/i386-common.c (processor_alias_table): Formatting
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fixes.
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* doc/invoke.texi (bdver3, bdver4, znver1): Add missing closing paren.
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(znver2): Likewise. Add RDPID and WBNOINVD, remove spurious comma
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before CLWB.
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2019-12-17 Hongyu Wang <hongyu.wang@intel.com>
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2019-12-17 Hongyu Wang <hongyu.wang@intel.com>
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PR target/92651
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PR target/92651
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@ -1617,7 +1617,7 @@ const pta processor_alias_table[] =
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{"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
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{"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
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PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
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PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
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{"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
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{"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
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PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
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PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
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{"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
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{"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
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PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
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PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
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{"prescott", PROCESSOR_NOCONA, CPU_NONE,
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{"prescott", PROCESSOR_NOCONA, CPU_NONE,
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@ -1775,12 +1775,12 @@ const pta processor_alias_table[] =
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| PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
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| PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
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| PTA_WBNOINVD},
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| PTA_WBNOINVD},
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{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
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{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
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| PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
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| PTA_FXSR | PTA_XSAVE},
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| PTA_FXSR | PTA_XSAVE},
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{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
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{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
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| PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
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| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
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| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
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| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
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| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
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| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
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| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
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@ -27767,35 +27767,38 @@ instruction set extensions.)
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CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This
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CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This
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supersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
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supersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
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SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
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SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
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@item bdver2
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@item bdver2
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AMD Family 15h core based CPUs with x86-64 instruction set support. (This
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AMD Family 15h core based CPUs with x86-64 instruction set support. (This
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supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX,
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supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX,
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SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
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SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
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extensions.)
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extensions.)
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@item bdver3
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@item bdver3
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AMD Family 15h core based CPUs with x86-64 instruction set support. (This
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AMD Family 15h core based CPUs with x86-64 instruction set support. (This
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supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,
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supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,
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PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and
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PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and
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64-bit instruction set extensions.
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64-bit instruction set extensions.)
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@item bdver4
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@item bdver4
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AMD Family 15h core based CPUs with x86-64 instruction set support. (This
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AMD Family 15h core based CPUs with x86-64 instruction set support. (This
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supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,
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supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,
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AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,
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AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,
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SSE4.2, ABM and 64-bit instruction set extensions.
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SSE4.2, ABM and 64-bit instruction set extensions.)
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@item znver1
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@item znver1
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AMD Family 17h core based CPUs with x86-64 instruction set support. (This
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AMD Family 17h core based CPUs with x86-64 instruction set support. (This
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supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX,
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supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX,
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SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3,
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SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3,
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SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
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SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
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instruction set extensions.
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@item znver2
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AMD Family 17h core based CPUs with x86-64 instruction set support. (This
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supersets BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,
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MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
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SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
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instruction set extensions.)
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instruction set extensions.)
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@item znver2
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AMD Family 17h core based CPUs with x86-64 instruction set support. (This
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supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,
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MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
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SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,
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WBNOINVD, and 64-bit instruction set extensions.)
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@item btver1
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@item btver1
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CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
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CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
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