ia64.c (emit_insn_group_barriers): Special case epilogue_deallocate_stack.
* config/ia64/ia64.c (emit_insn_group_barriers): Special case epilogue_deallocate_stack. * config/ia64/ia64.c (ia64_print_operand) [case D]: Emit completers for UNORDERED and ORDERED as well. * config/ia64/ia64.md (bunordered, bordered): New. (sunordered, sordered): New. From-SVN: r34734
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@ -1,3 +1,13 @@
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2000-06-27 Richard Henderson <rth@cygnus.com>
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* config/ia64/ia64.c (emit_insn_group_barriers): Special case
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epilogue_deallocate_stack.
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* config/ia64/ia64.c (ia64_print_operand) [case D]: Emit
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completers for UNORDERED and ORDERED as well.
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* config/ia64/ia64.md (bunordered, bordered): New.
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(sunordered, sordered): New.
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Tue Jun 27 12:14:12 MET DST 2000 Jan Hubicka <jh@suse.cz>
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* genattrtab.c (write_attr_value): Do not abort for CONST_INT operands.
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@ -1777,6 +1777,8 @@ ia64_print_operand (file, x, code)
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rtx x;
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int code;
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{
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const char *str;
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switch (code)
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{
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case 0:
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@ -1796,7 +1798,22 @@ ia64_print_operand (file, x, code)
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}
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case 'D':
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fputs (GET_CODE (x) == NE ? "neq" : GET_RTX_NAME (GET_CODE (x)), file);
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switch (GET_CODE (x))
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{
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case NE:
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str = "neq";
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break;
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case UNORDERED:
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str = "unord";
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break;
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case ORDERED:
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str = "ord";
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break;
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default:
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str = GET_RTX_NAME (GET_CODE (x));
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break;
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}
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fputs (str, file);
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return;
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case 'E':
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@ -1805,13 +1822,14 @@ ia64_print_operand (file, x, code)
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case 'F':
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if (x == CONST0_RTX (GET_MODE (x)))
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fputs (reg_names [FR_REG (0)], file);
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str = reg_names [FR_REG (0)];
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else if (x == CONST1_RTX (GET_MODE (x)))
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fputs (reg_names [FR_REG (1)], file);
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str = reg_names [FR_REG (1)];
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else if (GET_CODE (x) == REG)
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fputs (reg_names [REGNO (x)], file);
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str = reg_names [REGNO (x)];
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else
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abort ();
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fputs (str, file);
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return;
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case 'I':
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@ -2834,8 +2852,15 @@ emit_insn_group_barriers (insns)
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break;
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else
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{
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rtx pat = PATTERN (insn);
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/* We play dependency tricks with the epilogue in order to
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get proper schedules. Undo this for dv analysis. */
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if (INSN_CODE (insn) == CODE_FOR_epilogue_deallocate_stack)
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pat = XVECEXP (pat, 0, 0);
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memset (rws_insn, 0, sizeof (rws_insn));
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need_barrier |= rtx_needs_barrier (PATTERN (insn), flags, 0);
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need_barrier |= rtx_needs_barrier (pat, flags, 0);
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/* Check to see if the previous instruction was a volatile
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asm. */
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@ -2153,6 +2153,40 @@
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operands[3] = ia64_compare_op1;
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}")
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(define_expand "bunordered"
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[(set (match_dup 1)
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(unordered:CC (match_dup 2)
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(match_dup 3)))
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(set (pc)
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(if_then_else (ne:CC (match_dup 1)
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"
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{
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operands[1] = gen_reg_rtx (CCmode);
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operands[2] = ia64_compare_op0;
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operands[3] = ia64_compare_op1;
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}")
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(define_expand "bordered"
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[(set (match_dup 1)
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(ordered:CC (match_dup 2)
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(match_dup 3)))
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(set (pc)
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(if_then_else (ne:CC (match_dup 1)
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"
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{
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operands[1] = gen_reg_rtx (CCmode);
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operands[2] = ia64_compare_op0;
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operands[3] = ia64_compare_op1;
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}")
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(define_insn "*br_true"
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[(set (pc)
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(if_then_else (match_operator 0 "predicate_operator"
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@ -2323,6 +2357,34 @@
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operands[3] = ia64_compare_op1;
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}")
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(define_expand "sunordered"
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[(set (match_dup 1)
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(unordered:CC (match_dup 2)
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(match_dup 3)))
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(set (match_operand:DI 0 "register_operand" "")
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(ne:DI (match_dup 1) (const_int 0)))]
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""
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"
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{
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operands[1] = gen_reg_rtx (CCmode);
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operands[2] = ia64_compare_op0;
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operands[3] = ia64_compare_op1;
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}")
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(define_expand "sordered"
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[(set (match_dup 1)
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(ordered:CC (match_dup 2)
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(match_dup 3)))
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(set (match_operand:DI 0 "register_operand" "")
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(ne:DI (match_dup 1) (const_int 0)))]
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""
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"
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{
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operands[1] = gen_reg_rtx (CCmode);
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operands[2] = ia64_compare_op0;
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operands[3] = ia64_compare_op1;
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}")
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;; Don't allow memory as destination here, because cmov/cmov/st is more
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;; efficient than mov/mov/cst/cst.
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