alias.c: Fix comment formatting.
* alias.c: Fix comment formatting. * recog.c: Likewise. * config/cris/cris.c: Likewise. * config/cris/cris.h: Likewise. * config/i960/i960.c: Likewise. * config/i960/i960.h: Likewise. From-SVN: r46640
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
bc70506b60
commit
e5837c07d5
@ -1,3 +1,12 @@
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2001-10-30 Kazu Hirata <kazu@hxi.com>
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* alias.c: Fix comment formatting.
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* recog.c: Likewise.
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* config/cris/cris.c: Likewise.
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* config/cris/cris.h: Likewise.
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* config/i960/i960.c: Likewise.
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* config/i960/i960.h: Likewise.
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2001-10-30 Kazu Hirata <kazu@hxi.com>
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* config/arm/arm.c: Fix a comment typo.
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@ -510,7 +510,7 @@ get_alias_set (t)
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if (decl && DECL_POINTER_ALIAS_SET_KNOWN_P (decl))
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{
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/* If we haven't computed the actual alias set, do it now. */
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/* If we haven't computed the actual alias set, do it now. */
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if (DECL_POINTER_ALIAS_SET (decl) == -2)
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{
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/* No two restricted pointers can point at the same thing.
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@ -665,7 +665,7 @@ cris_target_asm_function_prologue (file, size)
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cfa_write_offset -= size;
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/* Get a contiguous sequence of registers, starting with r0, that need
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to be saved. */
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to be saved. */
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for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
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{
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if ((((regs_ever_live[regno]
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@ -774,7 +774,7 @@ cris_target_asm_function_prologue (file, size)
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else
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{
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/* Avoid printing multiple subsequent sub:s for sp. FIXME:
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Clean up the conditional expression. */
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Clean up the conditional expression. */
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fprintf (file, "\tsub%s %d,$sp\n",
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ADDITIVE_SIZE_MODIFIER ((last_movem_reg + 1) * 4 + size),
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(last_movem_reg + 1) * 4 + size);
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@ -849,7 +849,7 @@ saved_regs_mentioned (x)
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const char *fmt;
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RTX_CODE code;
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/* Mainly stolen from refers_to_regno_p in rtlanal.c. */
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/* Mainly stolen from refers_to_regno_p in rtlanal.c. */
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code = GET_CODE (x);
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@ -1166,7 +1166,7 @@ cris_target_asm_function_epilogue (file, size)
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them. */
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if (pretend)
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{
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/* Since srp is stored on the way, we need to restore it first. */
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/* Since srp is stored on the way, we need to restore it first. */
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if (return_address_on_stack)
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{
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if (*save_last && file)
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@ -1184,7 +1184,7 @@ cris_target_asm_function_epilogue (file, size)
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ADDITIVE_SIZE_MODIFIER (pretend), pretend);
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}
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/* Here's where we have a delay-slot we need to fill. */
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/* Here's where we have a delay-slot we need to fill. */
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if (file && current_function_epilogue_delay_list)
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{
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/* If gcc has allocated an insn for the epilogue delay slot, but
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@ -1442,7 +1442,7 @@ cris_print_operand (file, x, code)
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return;
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case 0:
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/* No code, print as usual. */
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/* No code, print as usual. */
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break;
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default:
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@ -1454,7 +1454,7 @@ cris_print_operand (file, x, code)
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}
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}
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/* Print an operand as without a modifier letter. */
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/* Print an operand as without a modifier letter. */
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switch (GET_CODE (operand))
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{
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case REG:
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@ -1675,7 +1675,7 @@ cris_initial_elimination_offset (fromreg, toreg)
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&& toreg == STACK_POINTER_REGNUM)
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return fp_sp_offset;
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/* We need to balance out the frame pointer here. */
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/* We need to balance out the frame pointer here. */
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if (fromreg == ARG_POINTER_REGNUM
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&& toreg == STACK_POINTER_REGNUM)
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return ap_fp_offset + fp_sp_offset - 4;
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@ -1779,13 +1779,13 @@ cris_notice_update_cc (exp, insn)
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return;
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/* Record CC0 changes, so we do not have to output multiple
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test insns. */
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test insns. */
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if (SET_DEST (exp) == cc0_rtx)
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{
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cc_status.value1 = SET_SRC (exp);
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cc_status.value2 = 0;
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/* Handle flags for the special btstq on one bit. */
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/* Handle flags for the special btstq on one bit. */
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if (GET_CODE (SET_SRC (exp)) == ZERO_EXTRACT
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&& XEXP (SET_SRC (exp), 1) == const1_rtx)
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{
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@ -1805,7 +1805,7 @@ cris_notice_update_cc (exp, insn)
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&& XEXP (SET_SRC (exp), 1) != const0_rtx)
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/* For some reason gcc will not canonicalize compare
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operations, reversing the sign by itself if
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operands are in wrong order. */
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operands are in wrong order. */
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/* (But NOT inverted; eq is still eq.) */
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cc_status.flags = CC_REVERSED;
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@ -1823,14 +1823,14 @@ cris_notice_update_cc (exp, insn)
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&& REG_P (XEXP (SET_DEST (exp), 0))))
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{
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/* A register is set; normally CC is set to show that no
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test insn is needed. Catch the exceptions. */
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test insn is needed. Catch the exceptions. */
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/* If not to cc0, then no "set"s in non-natural mode give
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ok cc0... */
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if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
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|| GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
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{
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/* ... except add:s and sub:s in DImode. */
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/* ... except add:s and sub:s in DImode. */
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if (GET_MODE (SET_DEST (exp)) == DImode
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&& (GET_CODE (SET_SRC (exp)) == PLUS
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|| GET_CODE (SET_SRC (exp)) == MINUS))
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@ -264,7 +264,7 @@ extern int target_flags;
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/* If to use condition-codes generated by insns other than the
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immediately preceding compare/test insn.
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Used to check for errors in notice_update_cc. */
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Used to check for errors in notice_update_cc. */
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#define TARGET_MASK_CCINIT 2
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#define TARGET_CCINIT (target_flags & TARGET_MASK_CCINIT)
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@ -519,11 +519,11 @@ extern int target_flags;
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#define FUNCTION_BOUNDARY 16
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/* Do not change BIGGEST_ALIGNMENT (when optimizing), as it will affect
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strange places, at least in 2.1. */
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strange places, at least in 2.1. */
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#define BIGGEST_ALIGNMENT 8
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/* If -m16bit, -m16-bit, -malign or -mdata-align,
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align everything to 16 bit. */
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align everything to 16 bit. */
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#define DATA_ALIGNMENT(TYPE, BASIC_ALIGN) \
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(TARGET_DATA_ALIGN \
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? (TARGET_ALIGN_BY_32 \
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@ -735,7 +735,7 @@ enum reg_class {NO_REGS, ALL_REGS, LIM_REG_CLASSES};
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0)
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/* It is really simple to make up a 0.0; it is the same as int-0 in
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IEEE754. */
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IEEE754. */
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#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \
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|| (VALUE) == CONST0_RTX (SFmode)))
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@ -873,7 +873,7 @@ enum reg_class {NO_REGS, ALL_REGS, LIM_REG_CLASSES};
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#define STACK_POINTER_REGNUM 14
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/* Register used for frame pointer. This is also the last of the saved
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registers, when a frame pointer is not used. */
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registers, when a frame pointer is not used. */
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#define FRAME_POINTER_REGNUM 8
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/* Faked register, is always eliminated. We need it to eliminate
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@ -1078,7 +1078,7 @@ struct cum_args {int regs;};
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Anyway, trampolines are rare enough that we can cope with this
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somewhat lack of elegance.
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(Do not be tempted to "straighten up" whitespace in the asms; the
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assembler #NO_APP state mandates strict spacing). */
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assembler #NO_APP state mandates strict spacing). */
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#define TRAMPOLINE_TEMPLATE(FILE) \
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do \
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{ \
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@ -1099,7 +1099,7 @@ struct cum_args {int regs;};
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/* CRIS wants instructions on word-boundary.
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Note that due to a bug (reported) in 2.7.2 and earlier, this is
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actually treated as alignment in _bytes_, not _bits_. (Obviously
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this is not fatal, only a slight waste of stack space). */
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this is not fatal, only a slight waste of stack space). */
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#define TRAMPOLINE_ALIGNMENT 16
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#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
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@ -1296,7 +1296,7 @@ struct cum_args {int regs;};
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\
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if (REGNO (XEXP (X, 1)) >= FIRST_PSEUDO_REGISTER) \
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{ \
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/* Second reg is pseudo, reload it. */ \
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/* Second reg is pseudo, reload it. */ \
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push_reload (XEXP (X, 1), NULL_RTX, &XEXP (X, 1), \
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NULL, \
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GENERAL_REGS, GET_MODE (X), VOIDmode, 0, 0, \
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@ -1308,7 +1308,7 @@ struct cum_args {int regs;};
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&& (REGNO (XEXP (XEXP (X, 0), 0)) \
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>= FIRST_PSEUDO_REGISTER)) \
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{ \
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/* First one is a pseudo - reload that. */ \
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/* First one is a pseudo - reload that. */ \
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push_reload (XEXP (XEXP (X, 0), 0), NULL_RTX, \
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&XEXP (XEXP (X, 0), 0), NULL, \
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GENERAL_REGS, \
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@ -1543,7 +1543,7 @@ struct cum_args {int regs;};
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while (0)
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/* This is what is used by gcc for 64-bit floats,
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not the "long double" one. */
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not the "long double" one. */
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#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
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ASM_OUTPUT_LONG_DOUBLE (FILE, VALUE)
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@ -1585,7 +1585,7 @@ struct cum_args {int regs;};
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#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) (C) == '@'
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/* FIXME: These are undocumented. */
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/* FIXME: These are undocumented. */
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/* We need to define these, since the 2byte, 4byte, 8byte op:s are only
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available in ELF. These "normal" pseudos do not have any alignment
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constraints or side-effects. */
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@ -1812,7 +1812,7 @@ struct cum_args {int regs;};
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/* Node: DBX Options */
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/* Is this correct? Check later. */
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/* Is this correct? Check later. */
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#define DBX_NO_XREFS
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#define DBX_CONTIN_LENGTH 0
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@ -507,7 +507,7 @@ i960_address_cost (x)
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Return 1 if we have written out everything that needs to be done to
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do the move. Otherwise, return 0 and the caller will emit the move
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normally. */
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normally. */
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int
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emit_move_sequence (operands, mode)
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@ -520,7 +520,7 @@ emit_move_sequence (operands, mode)
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&& (operands[1] != const0_rtx || current_function_args_size
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|| current_function_varargs || current_function_stdarg
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|| rtx_equal_function_value_matters))
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/* Here we use the same test as movsi+1 pattern -- see i960.md. */
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/* Here we use the same test as movsi+1 pattern -- see i960.md. */
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operands[1] = force_reg (mode, operands[1]);
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/* Storing multi-word values in unaligned hard registers to memory may
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@ -1031,7 +1031,7 @@ i960_function_name_declare (file, name, fndecl)
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leaf_proc_ok = 0;
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}
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/* See if caller passes in an address to return value. */
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/* See if caller passes in an address to return value. */
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if (aggregate_value_p (DECL_RESULT (fndecl)))
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{
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@ -1173,7 +1173,7 @@ compute_frame_size (size)
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}
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/* Here register group is range of registers which can be moved by
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one i960 instruction. */
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one i960 instruction. */
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struct reg_group
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{
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@ -1189,7 +1189,7 @@ static void i960_arg_size_and_align PARAMS ((enum machine_mode, tree, int *, int
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/* The following functions forms the biggest as possible register
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groups with registers in STATE. REGS contain states of the
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registers in range [start, finish_reg). The function returns the
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number of groups formed. */
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number of groups formed. */
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static int
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i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
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int start_reg;
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@ -1223,7 +1223,7 @@ i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
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return nw;
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}
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/* We sort register winodws in descending order by length. */
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/* We sort register winodws in descending order by length. */
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static int
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i960_reg_group_compare (group1, group2)
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const void *group1;
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@ -1242,7 +1242,7 @@ i960_reg_group_compare (group1, group2)
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/* Split the first register group in REG_GROUPS on subgroups one of
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which will contain SUBGROUP_LENGTH registers. The function
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returns new number of winodws. */
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returns new number of winodws. */
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static int
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i960_split_reg_group (reg_groups, nw, subgroup_length)
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struct reg_group *reg_groups;
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@ -1253,11 +1253,11 @@ i960_split_reg_group (reg_groups, nw, subgroup_length)
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/* This guarantees correct alignments of the two subgroups for
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i960 (see spliting for the group length 2, 3, 4). More
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generalized algorithm would require splitting the group more
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two subgroups. */
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two subgroups. */
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subgroup_length = reg_groups->length - subgroup_length;
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/* More generalized algorithm would require to try merging
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subgroups here. But in case i960 it always results in failure
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because of register group alignment. */
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because of register group alignment. */
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reg_groups[nw].length = reg_groups->length - subgroup_length;
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reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length;
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nw++;
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@ -1284,9 +1284,9 @@ i960_output_function_prologue (file, size)
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/* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
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somewhere. */
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int regs[FIRST_PSEUDO_REGISTER];
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/* All global registers (which must be saved) divided by groups. */
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/* All global registers (which must be saved) divided by groups. */
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struct reg_group global_reg_groups [16];
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/* All local registers (which are available) divided by groups. */
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/* All local registers (which are available) divided by groups. */
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struct reg_group local_reg_groups [16];
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@ -2132,7 +2132,7 @@ legitimize_address (x, oldx, mode)
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#if 0
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/* Return the most stringent alignment that we are willing to consider
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objects of size SIZE and known alignment ALIGN as having. */
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objects of size SIZE and known alignment ALIGN as having. */
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int
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i960_alignment (size, align)
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@ -2244,7 +2244,7 @@ i960_expr_alignment (x, size)
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case SYMBOL_REF:
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/* If this is a valid program, objects are guaranteed to be
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correctly aligned for whatever size the reference actually is. */
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correctly aligned for whatever size the reference actually is. */
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align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
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break;
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@ -2556,7 +2556,7 @@ i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
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If there are no stack arguments but there are exactly NPARM_REGS
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registers, either there were no extra arguments or the caller
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allocated an argument block. */
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allocated an argument block. */
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if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
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{
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@ -100,7 +100,7 @@ Boston, MA 02111-1307, USA. */
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that -O means FP elimination. Addressing through sp requires
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negative offset and more one word addressing in the most cases
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(offsets except for 0-4095 require one more word). Therefore we've
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not defined the macro. */
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not defined the macro. */
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/*#define CAN_DEBUG_WITHOUT_FP*/
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/* Do leaf procedure and tail call optimizations for -O2 and higher. */
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@ -154,7 +154,7 @@ extern int i960_last_maxbitalignment;
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/* The following three are mainly used to provide a little sanity checking
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against the -mARCH flags given. The Jx series, for the purposes of
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gcc, is a Kx with a data cache. */
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gcc, is a Kx with a data cache. */
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/* Nonzero if we should generate code for the KA and similar processors.
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No FPU, no microcode instructions. */
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@ -422,7 +422,7 @@ extern int target_flags;
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#define POINTER_SIZE 32
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/* Width in bits of a long double. Define to 96, and let
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ROUND_TYPE_ALIGN adjust the alignment for speed. */
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ROUND_TYPE_ALIGN adjust the alignment for speed. */
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#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)
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/* ??? This must be a constant, because real.c and real.h test it with #if. */
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@ -634,7 +634,7 @@ extern int target_flags;
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This is an array of structures. Each structure initializes one pair
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of eliminable registers. The "from" register number is given first,
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followed by "to". Eliminations of the same "from" register are listed
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in order of preference.. */
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in order of preference.. */
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#define ELIMINABLE_REGS {{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
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@ -1118,7 +1118,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
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In each case, scale can be 1, 2, 4, 8, or 16. */
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/* Returns 1 if the scale factor of an index term is valid. */
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/* Returns 1 if the scale factor of an index term is valid. */
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#define SCALE_TERM_P(X) \
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(GET_CODE (X) == CONST_INT \
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&& (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
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@ -1167,7 +1167,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
|
||||
/* Define as C expression which evaluates to nonzero if the tablejump
|
||||
instruction expects the table to contain offsets from the address of the
|
||||
table.
|
||||
Do not define this if the table should contain absolute addresses. */
|
||||
Do not define this if the table should contain absolute addresses. */
|
||||
/* #define CASE_VECTOR_PC_RELATIVE 1 */
|
||||
|
||||
/* Specify the tree operation to be used to convert reals to integers. */
|
||||
@ -1198,7 +1198,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
|
||||
|
||||
/* Nonzero if access to memory by bytes is no faster than for words.
|
||||
Value changed to 1 after reports of poor bitfield code with g++.
|
||||
Indications are that code is usually as good, sometimes better. */
|
||||
Indications are that code is usually as good, sometimes better. */
|
||||
|
||||
#define SLOW_BYTE_ACCESS 1
|
||||
|
||||
@ -1213,7 +1213,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
|
||||
#define STORE_FLAG_VALUE 1
|
||||
|
||||
/* Define this to be nonzero if shift instructions ignore all but the low-order
|
||||
few bits. */
|
||||
few bits. */
|
||||
#define SHIFT_COUNT_TRUNCATED 0
|
||||
|
||||
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
||||
@ -1345,7 +1345,7 @@ extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
|
||||
#define DBX_CONTIN_LENGTH 1500
|
||||
|
||||
/* This is how to output a note to DBX telling it the line number
|
||||
to which the following sequence of instructions corresponds. */
|
||||
to which the following sequence of instructions corresponds. */
|
||||
|
||||
#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
|
||||
{ if (write_symbols == SDB_DEBUG) { \
|
||||
@ -1370,7 +1370,7 @@ extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
|
||||
assemble_name (FILE, NAME); \
|
||||
fputs ("\n", FILE); }
|
||||
|
||||
/* The prefix to add to user-visible assembler symbols. */
|
||||
/* The prefix to add to user-visible assembler symbols. */
|
||||
|
||||
#define USER_LABEL_PREFIX "_"
|
||||
|
||||
|
||||
@ -3121,7 +3121,7 @@ peephole2_optimize (dump_file)
|
||||
XEXP (note, 0),
|
||||
REG_NOTES (new_insn));
|
||||
default:
|
||||
/* Discard all other reg notes. */
|
||||
/* Discard all other reg notes. */
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user