(movdi matchers): Rewrite.
(store_unaligned_di_reg): New pattern. (movti matchers): Rewrite. (store_unaligned_ti_reg): New pattern. From-SVN: r10553
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@ -821,41 +821,12 @@
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switch (which_alternative)
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{
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case 0:
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if ((REGNO (operands[0]) & 1)
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|| (REGNO (operands[1]) & 1))
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{
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/* We normally copy the low-numbered register first. However, if
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the second source register is the same as the first destination
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register, we must copy in the opposite order. */
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if (REGNO (operands[1]) + 1 == REGNO (operands[0]))
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return \"mov %D1,%D0\;mov %1,%0\";
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else
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return \"mov %1,%0\;mov %D1,%D0\";
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}
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else
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return \"movl %1,%0\";
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case 1:
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if (REGNO (operands[0]) & 1)
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return \"mov %1,%0\;mov 0,%D0\";
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else
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return \"movl %1,%0\";
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case 3:
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case 4:
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return i960_output_move_double (operands[0], operands[1]);
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case 2:
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return i960_output_ldconst (operands[0], operands[1]);
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case 3:
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if (REGNO (operands[0]) & 1)
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{
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/* One can optimize a few cases here, but you have to be
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careful of clobbering registers used in the address and
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edge conditions. */
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operands[2] = gen_rtx (REG, Pmode, REGNO (operands[0]) + 1);
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operands[3] = gen_rtx (MEM, word_mode, operands[2]);
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operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
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return \"lda %1,%2\;ld %3,%0\;ld %4,%D0\";
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}
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else
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return \"ldl %1,%0\";
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case 4:
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return \"stl %1,%0\";
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case 5:
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operands[1] = adj_offsettable_operand (operands[0], 4);
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return \"st g14,%0\;st g14,%1\";
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@ -878,45 +849,29 @@
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switch (which_alternative)
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{
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case 0:
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if ((REGNO (operands[0]) & 1)
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|| (REGNO (operands[1]) & 1))
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{
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/* We normally copy the low-numbered register first. However, if
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the second source register is the same as the first destination
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register, we must copy in the opposite order. */
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if (REGNO (operands[1]) + 1 == REGNO (operands[0]))
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return \"mov %D1,%D0\;mov %1,%0\";
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else
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return \"mov %1,%0\;mov %D1,%D0\";
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}
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else
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return \"movl %1,%0\";
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case 1:
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if (REGNO (operands[0]) & 1)
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return \"mov %1,%0\;mov 0,%D0\";
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else
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return \"movl %1,%0\";
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case 3:
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case 4:
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return i960_output_move_double (operands[0], operands[1]);
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case 2:
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return i960_output_ldconst (operands[0], operands[1]);
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case 3:
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if (REGNO (operands[0]) & 1)
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{
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/* One can optimize a few cases here, but you have to be
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careful of clobbering registers used in the address and
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edge conditions. */
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operands[2] = gen_rtx (REG, Pmode, REGNO (operands[0]) + 1);
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operands[3] = gen_rtx (MEM, word_mode, operands[2]);
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operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
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return \"lda %1,%2\;ld %3,%0\;ld %4,%D0\";
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}
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else
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return \"ldl %1,%0\";
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case 4:
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return \"stl %1,%0\";
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}
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}"
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[(set_attr "type" "move,move,load,load,store")])
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(define_insn "*store_unaligned_di_reg"
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[(set (match_operand:DI 0 "memory_operand" "=m")
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(match_operand:DI 1 "register_operand" "d"))
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(clobber (match_scratch:SI 2 "=&d"))]
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""
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"*
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{
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operands[3] = gen_rtx (MEM, word_mode, operands[2]);
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operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
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return \"lda %0,%2\;st %1,%3\;st %D1,%4\";
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}"
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[(set_attr "type" "store")])
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(define_expand "movti"
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[(set (match_operand:TI 0 "general_operand" "")
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(match_operand:TI 1 "general_operand" ""))]
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@ -929,8 +884,8 @@
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;; The store case can not be separate. See comment above.
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(define_insn ""
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[(set (match_operand:TI 0 "general_operand" "=d,d,d,m,o")
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(match_operand:TI 1 "general_operand" "dI,i,m,d,J"))]
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[(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m,o")
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(match_operand:TI 1 "general_operand" "d,I,i,m,d,J"))]
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"(current_function_args_size == 0
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&& current_function_varargs == 0
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&& current_function_stdarg == 0
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@ -943,26 +898,25 @@
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switch (which_alternative)
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{
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case 0:
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return \"movq %1,%0\";
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case 1:
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return i960_output_ldconst (operands[0], operands[1]);
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case 2:
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return \"ldq %1,%0\";
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case 3:
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return \"stq %1,%0\";
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case 4:
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return i960_output_move_quad (operands[0], operands[1]);
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case 2:
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return i960_output_ldconst (operands[0], operands[1]);
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case 5:
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operands[1] = adj_offsettable_operand (operands[0], 4);
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operands[2] = adj_offsettable_operand (operands[0], 8);
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operands[3] = adj_offsettable_operand (operands[0], 12);
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return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\";
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}
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}"
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[(set_attr "type" "move,load,load,store,store")])
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[(set_attr "type" "move,move,load,load,store,store")])
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;; The store case can not be separate. See comment above.
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(define_insn ""
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[(set (match_operand:TI 0 "general_operand" "=d,d,d,m")
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(match_operand:TI 1 "general_operand" "dI,i,m,d"))]
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[(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m")
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(match_operand:TI 1 "general_operand" "d,I,i,m,d"))]
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"(current_function_args_size != 0
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|| current_function_varargs != 0
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|| current_function_stdarg != 0
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@ -974,16 +928,30 @@
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switch (which_alternative)
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{
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case 0:
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return \"movq %1,%0\";
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case 1:
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return i960_output_ldconst (operands[0], operands[1]);
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case 2:
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return \"ldq %1,%0\";
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case 3:
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return \"stq %1,%0\";
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case 4:
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return i960_output_move_quad (operands[0], operands[1]);
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case 2:
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return i960_output_ldconst (operands[0], operands[1]);
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}
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}"
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[(set_attr "type" "move,load,load,store")])
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[(set_attr "type" "move,move,load,load,store")])
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(define_insn "*store_unaligned_ti_reg"
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[(set (match_operand:TI 0 "memory_operand" "=m")
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(match_operand:TI 1 "register_operand" "d"))
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(clobber (match_scratch:SI 2 "=&d"))]
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""
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"*
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{
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operands[3] = gen_rtx (MEM, word_mode, operands[2]);
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operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
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operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
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operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
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return \"lda %0,%2\;st %1,%3\;st %D1,%4\;st %E1,%5\;st %F1,%6\";
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}"
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[(set_attr "type" "store")])
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(define_expand "store_multiple"
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[(set (match_operand:SI 0 "" "") ;;- dest
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