diff --git a/gcc/ChangeLog b/gcc/ChangeLog index abbe63737cb..b2c7bae6c31 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2019-06-04 Segher Boessenkool + + * config/rs6000/constraints.md (define_register_constraint "wi"): + Delete. + (define_register_constraint "wt"): Delete. + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. + (rs6000_init_hard_regno_mode_ok): Adjust. + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete + RS6000_CONSTRAINT_wi and RS6000_CONSTRAINT_wt. + * config/rs6000/rs6000.md: Adjust. + * config/rs6000/vsx.md: Adjust. + * doc/md.texi (Machine Constraints): Adjust. + 2019-06-04 Szabolcs Nagy * config/aarch64/aarch64-protos.h (aarch64_asm_output_external): Remove diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 844e947ece6..edf825d8557 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -68,9 +68,6 @@ (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" "VSX vector register to hold vector float data or NO_REGS.") -(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" - "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") - ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use ;; direct move directly, and movsf can't to move between the register sets. ;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode @@ -88,9 +85,6 @@ (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" "VSX vector register to hold scalar double values or NO_REGS.") -(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" - "VSX vector register to hold 128 bit integer or NO_REGS.") - (define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]" "Altivec register to use for double loads/stores or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 95cf9d66017..0d2c2e17f4d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2511,12 +2511,10 @@ rs6000_debug_reg_global (void) "wd reg_class = %s\n" "we reg_class = %s\n" "wf reg_class = %s\n" - "wi reg_class = %s\n" "wp reg_class = %s\n" "wq reg_class = %s\n" "wr reg_class = %s\n" "ws reg_class = %s\n" - "wt reg_class = %s\n" "wv reg_class = %s\n" "ww reg_class = %s\n" "wx reg_class = %s\n" @@ -2529,12 +2527,10 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], @@ -3148,11 +3144,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wc - Reserved to represent individual CR bits (used in LLVM). wd - Preferred register class for V2DFmode. wf - Preferred register class for V4SFmode. - wi - FP or VSX register to hold 64-bit integers for VSX insns. wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. ws - Register class to do ISA 2.06 DF operations. - wt - VSX register for TImode in VSX registers. wv - Altivec register for ISA 2.06 VSX DF/DI load/stores. ww - Register class to do SF conversions in with VSX operations. wx - Float register if we can do 32-bit int stores. */ @@ -3170,8 +3164,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */ - rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */ - rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */ } /* Add conditional constraints based on various options, to allow us to diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 32011520739..6cfb0adf22d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1259,12 +1259,10 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ - RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ RS6000_CONSTRAINT_ws, /* VSX register for DF */ - RS6000_CONSTRAINT_wt, /* VSX register for TImode */ RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c49614c237d..07c27a12d60 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -526,12 +526,12 @@ ; ISA 2.06 (power7). This includes instructions that normally target DF mode, ; but are used on SFmode, since internally SFmode values are kept in the DFmode ; format. -(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wi")]) +(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wa")]) ; SF/DF constraint for arithmetic on VSX registers. This is intended to be ; used for DFmode instructions added in ISA 2.06 (power7) and SFmode ; instructions added in ISA 2.07 (power8) -(define_mode_attr Fv2 [(SF "wa") (DF "ws") (DI "wi")]) +(define_mode_attr Fv2 [(SF "wa") (DF "ws") (DI "wa")]) ; Which isa is needed for those float instructions? (define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")]) @@ -656,7 +656,7 @@ ;; either. ;; Mode attribute for boolean operation register constraints for output -(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v") +(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v") (PTI "&r,r,r") (V16QI "wa,v,&?r,?r,?r") (V8HI "wa,v,&?r,?r,?r") @@ -667,7 +667,7 @@ (V1TI "wa,v,&?r,?r,?r")]) ;; Mode attribute for boolean operation register constraints for operand1 -(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v") +(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v") (PTI "r,0,r") (V16QI "wa,v,r,0,r") (V8HI "wa,v,r,0,r") @@ -678,7 +678,7 @@ (V1TI "wa,v,r,0,r")]) ;; Mode attribute for boolean operation register constraints for operand2 -(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v") +(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v") (PTI "r,r,0") (V16QI "wa,v,r,r,0") (V8HI "wa,v,r,r,0") @@ -691,7 +691,7 @@ ;; Mode attribute for boolean operation register constraints for operand1 ;; for one_cmpl. To simplify things, we repeat the constraint where 0 ;; is used for operand1 or operand2 -(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v") +(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v") (PTI "r,0,0") (V16QI "wa,v,r,0,0") (V8HI "wa,v,r,0,0") @@ -835,7 +835,7 @@ (define_insn "zero_extendsi2" - [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wi,r,wa") + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa") (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))] "" "@ @@ -1020,7 +1020,7 @@ (define_insn "extendsi2" [(set (match_operand:EXTSI 0 "gpc_reg_operand" - "=r, r, d, wa, wi, v, v, wr") + "=r, r, d, wa, wa, v, v, wr") (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "YZ, r, Z, Z, r, v, v, ?wa")))] "" @@ -5234,7 +5234,7 @@ ; We don't define lfiwax/lfiwzx with the normal definition, because we ; don't want to support putting SImode in FPR registers. (define_insn "lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,v") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa,wa,v") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,v")] UNSPEC_LFIWAX))] "TARGET_HARD_FLOAT && TARGET_LFIWAX" @@ -5254,7 +5254,7 @@ (define_insn_and_split "floatsi2_lfiwax" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) - (clobber (match_scratch:DI 2 "=wi"))] + (clobber (match_scratch:DI 2 "=wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWAX && && can_create_pseudo_p ()" "#" @@ -5295,7 +5295,7 @@ (float:SFDF (sign_extend:DI (match_operand:SI 1 "indexed_or_indirect_operand" "Z")))) - (clobber (match_scratch:DI 2 "=wi"))] + (clobber (match_scratch:DI 2 "=wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWAX && " "#" "" @@ -5315,7 +5315,7 @@ (set_attr "type" "fpload")]) (define_insn "lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,wa") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa,wa,wa") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")] UNSPEC_LFIWZX))] "TARGET_HARD_FLOAT && TARGET_LFIWZX" @@ -5330,7 +5330,7 @@ (define_insn_and_split "floatunssi2_lfiwzx" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) - (clobber (match_scratch:DI 2 "=wi"))] + (clobber (match_scratch:DI 2 "=wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWZX && " "#" "" @@ -5370,7 +5370,7 @@ (unsigned_float:SFDF (zero_extend:DI (match_operand:SI 1 "indexed_or_indirect_operand" "Z")))) - (clobber (match_scratch:DI 2 "=wi"))] + (clobber (match_scratch:DI 2 "=wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWZX && " "#" "" @@ -5569,7 +5569,7 @@ [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=,,") (float:FP_ISA3 (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z"))) - (clobber (match_scratch:DI 2 "=v,wi,v")) + (clobber (match_scratch:DI 2 "=v,wa,v")) (clobber (match_scratch:DI 3 "=X,r,X")) (clobber (match_scratch: 4 "=X,X,v"))] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" @@ -5622,7 +5622,7 @@ [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=,,") (unsigned_float:FP_ISA3 (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z"))) - (clobber (match_scratch:DI 2 "=v,wi,wa")) + (clobber (match_scratch:DI 2 "=v,wa,wa")) (clobber (match_scratch:DI 3 "=X,r,X"))] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" "#" @@ -5748,7 +5748,7 @@ "") (define_insn "*fix_truncdi2_fctidz" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET_HARD_FLOAT && TARGET_FCFID" "@ @@ -5765,7 +5765,7 @@ (define_insn_and_split "fix_trunc2" [(set (match_operand: 0 "gpc_reg_operand" "=d,wa,r") (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa"))) - (clobber (match_scratch:SI 2 "=X,X,wi"))] + (clobber (match_scratch:SI 2 "=X,X,wa"))] "TARGET_DIRECT_MOVE" "@ fctiwz %0,%1 @@ -5867,7 +5867,7 @@ (set_attr "type" "fp")]) (define_insn "fixuns_truncdi2" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET_HARD_FLOAT && TARGET_FCTIDUZ" "@ @@ -6002,7 +6002,7 @@ ;; because the first makes it clear that operand 0 is not live ;; before the instruction. (define_insn "fctiwz_" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ","))] UNSPEC_FCTIWZ))] @@ -6013,7 +6013,7 @@ [(set_attr "type" "fp")]) (define_insn "fctiwuz_" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") (unspec:DI [(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ","))] UNSPEC_FCTIWUZ))] @@ -6224,7 +6224,7 @@ (define_insn "floatdidf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") - (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] + (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))] "TARGET_FCFID && TARGET_HARD_FLOAT" "@ fcfid %0,%1 @@ -6239,7 +6239,7 @@ (define_insn_and_split "*floatdidf2_mem" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") (float:DF (match_operand:DI 1 "memory_operand" "m,Z"))) - (clobber (match_scratch:DI 2 "=d,wi"))] + (clobber (match_scratch:DI 2 "=d,wa"))] "TARGET_HARD_FLOAT && TARGET_FCFID" "#" "&& reload_completed" @@ -6258,7 +6258,7 @@ (define_insn "*floatunsdidf2_fcfidu" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") - (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] + (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT && TARGET_FCFIDU" "@ fcfidu %0,%1 @@ -6268,7 +6268,7 @@ (define_insn_and_split "*floatunsdidf2_mem" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z"))) - (clobber (match_scratch:DI 2 "=d,wi"))] + (clobber (match_scratch:DI 2 "=d,wa"))] "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))" "#" "&& reload_completed" @@ -6301,7 +6301,7 @@ (define_insn "floatdisf2_fcfids" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa") - (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] + (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT && TARGET_FCFIDS" "@ fcfids %0,%1 @@ -6312,7 +6312,7 @@ (define_insn_and_split "*floatdisf2_mem" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa") (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z"))) - (clobber (match_scratch:DI 2 "=d,d,wi"))] + (clobber (match_scratch:DI 2 "=d,d,wa"))] "TARGET_HARD_FLOAT && TARGET_FCFIDS" "#" "&& reload_completed" @@ -6382,7 +6382,7 @@ (define_insn "floatunsdisf2_fcfidus" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa") - (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))] + (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT && TARGET_FCFIDUS" "@ fcfidus %0,%1 @@ -6393,7 +6393,7 @@ (define_insn_and_split "*floatunsdisf2_mem" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa") (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z"))) - (clobber (match_scratch:DI 2 "=d,d,wi"))] + (clobber (match_scratch:DI 2 "=d,d,wa"))] "TARGET_HARD_FLOAT && TARGET_FCFIDUS" "#" "&& reload_completed" @@ -8742,12 +8742,12 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, m, ^d, ^d, - r, wY, Z, ^v, $wv, ^wi, - wa, wa, wv, wi, *i, wv, + r, wY, Z, ^v, $wv, ^wa, + wa, wa, wv, wa, *i, wv, wv") (match_operand:DI 1 "input_operand" "r, Y, r, ^d, m, ^d, - IJKnF, ^v, $wv, wY, Z, ^wi, + IJKnF, ^v, $wv, wY, Z, ^wa, Oj, wM, OjwM, Oj, wM, wS, wB"))] "! TARGET_POWERPC64 @@ -8826,15 +8826,15 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, r, r, r, m, ^d, ^d, wY, Z, $v, - $wv, ^wi, wa, wa, wv, wi, - wi, wv, wv, r, *h, *h, - ?r, ?wi") + $wv, ^wa, wa, wa, wv, wa, + wa, wv, wv, r, *h, *h, + ?r, ?wa") (match_operand:DI 1 "input_operand" "r, YZ, r, I, L, nF, ^d, m, ^d, ^v, $wv, wY, - Z, ^wi, Oj, wM, OjwM, Oj, + Z, ^wa, Oj, wM, OjwM, Oj, wM, wS, wB, *h, r, 0, - wi, r"))] + wa, r"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -12654,7 +12654,7 @@ (const_int 1)) (label_ref (match_operand 0)) (pc))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*c*l") (plus:P (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) @@ -12730,7 +12730,7 @@ (const_int 0)])) (label_ref (match_operand 0)) (pc))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*c*l") (plus:P (match_dup 1) (const_int -1))) (clobber (match_scratch:P 5 "=X,X,&r,r")) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 6108451014b..f5ef5b8afa4 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -114,13 +114,13 @@ (V4SF "wf") (V2DI "wd") (V2DF "wd") - (DI "wi") + (DI "wa") (DF "ws") (SF "ww") (TF "wp") (KF "wq") (V1TI "v") - (TI "wt")]) + (TI "wa")]) ;; Map the register class used for float<->int conversions (floating point side) ;; VSr2 is the preferred register class, VSr3 is any register class that will @@ -129,7 +129,7 @@ (V4SF "wf") (DF "ws") (SF "ww") - (DI "wi") + (DI "wa") (KF "wq") (TF "wp")]) @@ -137,7 +137,7 @@ (V4SF "wa") (DF "ws") (SF "ww") - (DI "wi") + (DI "wa") (KF "wq") (TF "wp")]) @@ -162,11 +162,11 @@ (V4SF "wa") (V2DI "wa") (V2DF "wa") - (DI "wi") + (DI "wa") (DF "ws") (SF "ww") (V1TI "wa") - (TI "wt") + (TI "wa") (TF "wp") (KF "wq")]) @@ -278,7 +278,7 @@ ;; Map register class for 64-bit element in 128-bit vector for normal register ;; to register moves (define_mode_attr VS_64reg [(V2DF "ws") - (V2DI "wi")]) + (V2DI "wa")]) ;; Iterators for loading constants with xxspltib (define_mode_iterator VSINT_84 [V4SI V2DI DI SI]) @@ -4151,7 +4151,7 @@ [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we") (vec_duplicate:V4SI (truncate:SI - (match_operand:DI 1 "gpc_reg_operand" "wi,r"))))] + (match_operand:DI 1 "gpc_reg_operand" "wa,r"))))] "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT" "@ xxspltw %x0,%x1,1 diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index cf513261d78..ccab18b511e 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3196,10 +3196,8 @@ Altivec vector register @item wa Any VSX register if the @option{-mvsx} option was used or NO_REGS. -When using any of the register constraints (@code{wa}, @code{wd}, -@code{wf}, @code{wi}, -@code{wp}, @code{wq}, @code{ws}, -@code{wt}, @code{wv}, or @code{ww}) +When using any of the register constraints (@code{wa}, @code{wd}, @code{wf}, +@code{wp}, @code{wq}, @code{ws}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so that the correct register is used. Otherwise the register number output in the assembly file will be incorrect if an Altivec register @@ -3256,9 +3254,6 @@ were used or NO_REGS. @item wf VSX vector register to hold vector float data or NO_REGS. -@item wi -FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. - @item wn No register (NO_REGS). @@ -3274,9 +3269,6 @@ General purpose register if 64-bit instructions are enabled or NO_REGS. @item ws VSX vector register to hold scalar double values or NO_REGS. -@item wt -VSX vector register to hold 128 bit integer or NO_REGS. - @item wv Altivec register to use for double loads/stores or NO_REGS.