From e767da23de12ceb1bf3aece4dae0ae20bf605b04 Mon Sep 17 00:00:00 2001
From: Hongyu Wang <hongyu.wang@intel.com>
Date: Fri, 18 Mar 2022 23:47:35 +0800
Subject: [PATCH] AVX512FP16: Fix masm=intel output for vfc?(madd|mul)csh [PR
 104977]

Fix typo in subst for scalar complex mask_round operand.

gcc/ChangeLog:

	PR target/104977
	* config/i386/sse.md
	(avx512fp16_fma<complexopname>sh_v8hf<mask_scalarcz_name><round_scalarcz_name>):
	Correct round operand for intel dialect.

gcc/testsuite/ChangeLog:

	PR target/104977
	* gcc.target/i386/pr104977.c: New test.
---
 gcc/config/i386/sse.md                   |  2 +-
 gcc/testsuite/gcc.target/i386/pr104977.c | 13 +++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr104977.c

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ed98120be59..21bf3c55c95 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -6723,7 +6723,7 @@
 	  (match_dup 2)
 	  (const_int 3)))]
   "TARGET_AVX512FP16"
-  "v<complexopname>sh\t{<round_scalarcz_mask_op4>%2, %1, %0<mask_scalarcz_operand4>|%0<mask_scalarcz_operand4>, %1, %2<round_scalarcz_maskcz_mask_op4>}"
+  "v<complexopname>sh\t{<round_scalarcz_mask_op4>%2, %1, %0<mask_scalarcz_operand4>|%0<mask_scalarcz_operand4>, %1, %2<round_scalarcz_mask_op4>}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "V8HF")])
 
diff --git a/gcc/testsuite/gcc.target/i386/pr104977.c b/gcc/testsuite/gcc.target/i386/pr104977.c
new file mode 100644
index 00000000000..9faa4db3b0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104977.c
@@ -0,0 +1,13 @@
+/* PR target/104977 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mavx512fp16 -masm=intel" } */
+/* { dg-require-effective-target avx512fp16 } */
+/* { dg-require-effective-target masm_intel } */
+
+#include<immintrin.h>
+
+__m128h
+foo (__m128h a, __m128h b, __m128h c, __mmask8 m)
+{
+  return _mm_fcmadd_round_sch (a, b, c, 8);
+}