alpha.md (*add<mode>3_ieee): Merge to add<mode>3 using enabled attribute.
* config/alpha/alpha.md (*add<mode>3_ieee): Merge to add<mode>3 using enabled attribute. (*sub<mode>3_ieee): Merge to sub<mode>3 using enabled attribute. (*mul<mode>3_ieee): Merge to mul<mode>3 using enabled attribute. (*div<mode>3_ieee): Merge to div<mode>3 using enabled attribute. (*sqrt<mode>2_ieee): Merge to sqrt<mode>2 using enabled attribute. (*fix_truncdfdi_ieee): Merge to *fix_truncdfdi2 using enabled attribute. (*fix_truncsfdi_ieee): Merge to *fix_truncsfdi2 using enabled attribute. (*floatdisf_ieee): Merge to floatdisf2 using enabled attribute. (*floatdidf_ieee): Merge to floatdidf2 using enabled attribute. (*truncdfsf2_ieee): Merge to truncdfsf2 using enabled attribute. (*cmpdf_ieee): Merge to *cmpdf_internal using enabled attribute. From-SVN: r247490
This commit is contained in:
parent
0b1053b270
commit
e7c54c8ecb
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@ -1,3 +1,18 @@
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2017-05-02 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.md (*add<mode>3_ieee): Merge to add<mode>3
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using enabled attribute.
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(*sub<mode>3_ieee): Merge to sub<mode>3 using enabled attribute.
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(*mul<mode>3_ieee): Merge to mul<mode>3 using enabled attribute.
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(*div<mode>3_ieee): Merge to div<mode>3 using enabled attribute.
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(*sqrt<mode>2_ieee): Merge to sqrt<mode>2 using enabled attribute.
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(*fix_truncdfdi_ieee): Merge to *fix_truncdfdi2 using enabled attribute.
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(*fix_truncsfdi_ieee): Merge to *fix_truncsfdi2 using enabled attribute.
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(*floatdisf_ieee): Merge to floatdisf2 using enabled attribute.
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(*floatdidf_ieee): Merge to floatdidf2 using enabled attribute.
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(*truncdfsf2_ieee): Merge to truncdfsf2 using enabled attribute.
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(*cmpdf_ieee): Merge to *cmpdf_internal using enabled attribute.
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2017-05-02 Uros Bizjak <ubizjak@gmail.com>
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2017-05-02 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.c (ix86_code_end): Use {FIRST,LAST}_INT_REG.
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* config/i386/i386.c (ix86_code_end): Use {FIRST,LAST}_INT_REG.
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@ -1671,27 +1671,21 @@
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"cpysn %R2,%R1,%0"
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"cpysn %R2,%R1,%0"
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[(set_attr "type" "fadd")])
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[(set_attr "type" "fadd")])
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(define_insn "*add<mode>3_ieee"
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[(set (match_operand:FMODE 0 "register_operand" "=&f")
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(plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"add<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(define_insn "add<mode>3"
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(define_insn "add<mode>3"
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[(set (match_operand:FMODE 0 "register_operand" "=f")
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[(set (match_operand:FMODE 0 "register_operand" "=f,&f")
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(plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
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(plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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(match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
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"TARGET_FP"
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"TARGET_FP"
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"add<modesuffix>%/ %R1,%R2,%0"
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"add<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fadd")
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(set_attr "trap_suffix" "u_su_sui")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
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]
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(symbol_ref "true")))])
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(define_insn "*adddf_ext1"
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(define_insn "*adddf_ext1"
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[(set (match_operand:DF 0 "register_operand" "=f")
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[(set (match_operand:DF 0 "register_operand" "=f")
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@ -1725,27 +1719,21 @@
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"TARGET_HAS_XFLOATING_LIBS"
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"TARGET_HAS_XFLOATING_LIBS"
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"alpha_emit_xfloating_arith (PLUS, operands); DONE;")
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"alpha_emit_xfloating_arith (PLUS, operands); DONE;")
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(define_insn "*sub<mode>3_ieee"
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[(set (match_operand:FMODE 0 "register_operand" "=&f")
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(minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"sub<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(define_insn "sub<mode>3"
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(define_insn "sub<mode>3"
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[(set (match_operand:FMODE 0 "register_operand" "=f")
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[(set (match_operand:FMODE 0 "register_operand" "=f,&f")
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(minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
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(minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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(match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
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"TARGET_FP"
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"TARGET_FP"
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"sub<modesuffix>%/ %R1,%R2,%0"
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"sub<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fadd")
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(set_attr "trap_suffix" "u_su_sui")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
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]
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(symbol_ref "true")))])
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(define_insn "*subdf_ext1"
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(define_insn "*subdf_ext1"
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[(set (match_operand:DF 0 "register_operand" "=f")
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[(set (match_operand:DF 0 "register_operand" "=f")
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@ -1791,27 +1779,21 @@
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"TARGET_HAS_XFLOATING_LIBS"
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"TARGET_HAS_XFLOATING_LIBS"
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"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
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"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
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(define_insn "*mul<mode>3_ieee"
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[(set (match_operand:FMODE 0 "register_operand" "=&f")
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(mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"mul<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fmul")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(define_insn "mul<mode>3"
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(define_insn "mul<mode>3"
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[(set (match_operand:FMODE 0 "register_operand" "=f")
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[(set (match_operand:FMODE 0 "register_operand" "=f,&f")
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(mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
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(mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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(match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
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"TARGET_FP"
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"TARGET_FP"
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"mul<modesuffix>%/ %R1,%R2,%0"
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"mul<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fmul")
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[(set_attr "type" "fmul")
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(set_attr "trap" "yes")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(set_attr "trap_suffix" "u_su_sui")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
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]
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(symbol_ref "true")))])
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(define_insn "*muldf_ext1"
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(define_insn "*muldf_ext1"
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[(set (match_operand:DF 0 "register_operand" "=f")
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[(set (match_operand:DF 0 "register_operand" "=f")
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@ -1845,29 +1827,22 @@
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"TARGET_HAS_XFLOATING_LIBS"
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"TARGET_HAS_XFLOATING_LIBS"
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"alpha_emit_xfloating_arith (MULT, operands); DONE;")
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"alpha_emit_xfloating_arith (MULT, operands); DONE;")
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(define_insn "*div<mode>3_ieee"
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[(set (match_operand:FMODE 0 "register_operand" "=&f")
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(div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"div<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fdiv")
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(set_attr "opsize" "<opmode>")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(define_insn "div<mode>3"
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(define_insn "div<mode>3"
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[(set (match_operand:FMODE 0 "register_operand" "=f")
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[(set (match_operand:FMODE 0 "register_operand" "=f,&f")
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(div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
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(div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")
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(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
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(match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))]
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"TARGET_FP"
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"TARGET_FP"
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"div<modesuffix>%/ %R1,%R2,%0"
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"div<modesuffix>%/ %R1,%R2,%0"
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[(set_attr "type" "fdiv")
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[(set_attr "type" "fdiv")
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(set_attr "opsize" "<opmode>")
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(set_attr "opsize" "<opmode>")
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(set_attr "trap" "yes")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(set_attr "trap_suffix" "u_su_sui")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
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]
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(symbol_ref "true")))])
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(define_insn "*divdf_ext1"
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(define_insn "*divdf_ext1"
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[(set (match_operand:DF 0 "register_operand" "=f")
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[(set (match_operand:DF 0 "register_operand" "=f")
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@ -1912,27 +1887,21 @@
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"TARGET_HAS_XFLOATING_LIBS"
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"TARGET_HAS_XFLOATING_LIBS"
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"alpha_emit_xfloating_arith (DIV, operands); DONE;")
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"alpha_emit_xfloating_arith (DIV, operands); DONE;")
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(define_insn "*sqrt<mode>2_ieee"
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[(set (match_operand:FMODE 0 "register_operand" "=&f")
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(sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
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"TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
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"sqrt<modesuffix>%/ %R1,%0"
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[(set_attr "type" "fsqrt")
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(set_attr "opsize" "<opmode>")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(define_insn "sqrt<mode>2"
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(define_insn "sqrt<mode>2"
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[(set (match_operand:FMODE 0 "register_operand" "=f")
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[(set (match_operand:FMODE 0 "register_operand" "=f,&f")
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(sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
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(sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")))]
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"TARGET_FP && TARGET_FIX"
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"TARGET_FP && TARGET_FIX"
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"sqrt<modesuffix>%/ %R1,%0"
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"sqrt<modesuffix>%/ %R1,%0"
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[(set_attr "type" "fsqrt")
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[(set_attr "type" "fsqrt")
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(set_attr "opsize" "<opmode>")
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(set_attr "opsize" "<opmode>")
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(set_attr "trap" "yes")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "normal")
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "u_su_sui")])
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(set_attr "trap_suffix" "u_su_sui")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
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]
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(symbol_ref "true")))])
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;; Define conversion operators between DFmode and SImode, using the cvtql
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;; Define conversion operators between DFmode and SImode, using the cvtql
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;; instruction. To allow combine et al to do useful things, we keep the
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;; instruction. To allow combine et al to do useful things, we keep the
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@ -1991,27 +1960,21 @@
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[(set_attr "type" "fadd")
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
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(set_attr "trap" "yes")])
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|
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(define_insn "*fix_truncdfdi_ieee"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
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(match_operator:DI 2 "fix_operator"
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[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"cvt%-q%/ %R1,%0"
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")
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(set_attr "round_suffix" "c")
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(set_attr "trap_suffix" "v_sv_svi")])
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|
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(define_insn "*fix_truncdfdi2"
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(define_insn "*fix_truncdfdi2"
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f")
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(match_operator:DI 2 "fix_operator"
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(match_operator:DI 2 "fix_operator"
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[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
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[(match_operand:DF 1 "reg_or_0_operand" "fG,fG")]))]
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"TARGET_FP"
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"TARGET_FP"
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||||||
"cvt%-q%/ %R1,%0"
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"cvt%-q%/ %R1,%0"
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||||||
[(set_attr "type" "fadd")
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[(set_attr "type" "fadd")
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||||||
(set_attr "trap" "yes")
|
(set_attr "trap" "yes")
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||||||
(set_attr "round_suffix" "c")
|
(set_attr "round_suffix" "c")
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||||||
(set_attr "trap_suffix" "v_sv_svi")])
|
(set_attr "trap_suffix" "v_sv_svi")
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||||||
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(set (attr "enabled")
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|
(cond [(eq_attr "alternative" "0")
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||||||
|
(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
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]
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||||||
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(symbol_ref "true")))])
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|
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||||||
(define_expand "fix_truncdfdi2"
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(define_expand "fix_truncdfdi2"
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||||||
[(set (match_operand:DI 0 "reg_no_subreg_operand")
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[(set (match_operand:DI 0 "reg_no_subreg_operand")
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||||||
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@ -2063,27 +2026,21 @@
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[(set_attr "type" "fadd")
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
|
(set_attr "trap" "yes")])
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||||||
|
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||||||
(define_insn "*fix_truncsfdi_ieee"
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|
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[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
|
|
||||||
(match_operator:DI 2 "fix_operator"
|
|
||||||
[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
|
|
||||||
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
||||||
"cvt%-q%/ %R1,%0"
|
|
||||||
[(set_attr "type" "fadd")
|
|
||||||
(set_attr "trap" "yes")
|
|
||||||
(set_attr "round_suffix" "c")
|
|
||||||
(set_attr "trap_suffix" "v_sv_svi")])
|
|
||||||
|
|
||||||
(define_insn "*fix_truncsfdi2"
|
(define_insn "*fix_truncsfdi2"
|
||||||
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
|
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f")
|
||||||
(match_operator:DI 2 "fix_operator"
|
(match_operator:DI 2 "fix_operator"
|
||||||
[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
|
[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,fG"))]))]
|
||||||
"TARGET_FP"
|
"TARGET_FP"
|
||||||
"cvt%-q%/ %R1,%0"
|
"cvt%-q%/ %R1,%0"
|
||||||
[(set_attr "type" "fadd")
|
[(set_attr "type" "fadd")
|
||||||
(set_attr "trap" "yes")
|
(set_attr "trap" "yes")
|
||||||
(set_attr "round_suffix" "c")
|
(set_attr "round_suffix" "c")
|
||||||
(set_attr "trap_suffix" "v_sv_svi")])
|
(set_attr "trap_suffix" "v_sv_svi")
|
||||||
|
(set (attr "enabled")
|
||||||
|
(cond [(eq_attr "alternative" "0")
|
||||||
|
(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
|
||||||
|
]
|
||||||
|
(symbol_ref "true")))])
|
||||||
|
|
||||||
(define_expand "fix_truncsfdi2"
|
(define_expand "fix_truncsfdi2"
|
||||||
[(set (match_operand:DI 0 "reg_no_subreg_operand")
|
[(set (match_operand:DI 0 "reg_no_subreg_operand")
|
||||||
|
@ -2108,25 +2065,20 @@
|
||||||
"TARGET_HAS_XFLOATING_LIBS"
|
"TARGET_HAS_XFLOATING_LIBS"
|
||||||
"alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
|
"alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
|
||||||
|
|
||||||
(define_insn "*floatdisf_ieee"
|
|
||||||
[(set (match_operand:SF 0 "register_operand" "=&f")
|
|
||||||
(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
|
||||||
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
||||||
"cvtq%,%/ %1,%0"
|
|
||||||
[(set_attr "type" "fadd")
|
|
||||||
(set_attr "trap" "yes")
|
|
||||||
(set_attr "round_suffix" "normal")
|
|
||||||
(set_attr "trap_suffix" "sui")])
|
|
||||||
|
|
||||||
(define_insn "floatdisf2"
|
(define_insn "floatdisf2"
|
||||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
[(set (match_operand:SF 0 "register_operand" "=f,&f")
|
||||||
(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))]
|
||||||
"TARGET_FP"
|
"TARGET_FP"
|
||||||
"cvtq%,%/ %1,%0"
|
"cvtq%,%/ %1,%0"
|
||||||
[(set_attr "type" "fadd")
|
[(set_attr "type" "fadd")
|
||||||
(set_attr "trap" "yes")
|
(set_attr "trap" "yes")
|
||||||
(set_attr "round_suffix" "normal")
|
(set_attr "round_suffix" "normal")
|
||||||
(set_attr "trap_suffix" "sui")])
|
(set_attr "trap_suffix" "sui")
|
||||||
|
(set (attr "enabled")
|
||||||
|
(cond [(eq_attr "alternative" "0")
|
||||||
|
(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
|
||||||
|
]
|
||||||
|
(symbol_ref "true")))])
|
||||||
|
|
||||||
(define_insn_and_split "*floatsisf2_ieee"
|
(define_insn_and_split "*floatsisf2_ieee"
|
||||||
[(set (match_operand:SF 0 "register_operand" "=&f")
|
[(set (match_operand:SF 0 "register_operand" "=&f")
|
||||||
|
@ -2155,25 +2107,20 @@
|
||||||
operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
|
operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
|
||||||
})
|
})
|
||||||
|
|
||||||
(define_insn "*floatdidf_ieee"
|
|
||||||
[(set (match_operand:DF 0 "register_operand" "=&f")
|
|
||||||
(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
|
||||||
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
||||||
"cvtq%-%/ %1,%0"
|
|
||||||
[(set_attr "type" "fadd")
|
|
||||||
(set_attr "trap" "yes")
|
|
||||||
(set_attr "round_suffix" "normal")
|
|
||||||
(set_attr "trap_suffix" "sui")])
|
|
||||||
|
|
||||||
(define_insn "floatdidf2"
|
(define_insn "floatdidf2"
|
||||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
[(set (match_operand:DF 0 "register_operand" "=f,&f")
|
||||||
(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
|
(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))]
|
||||||
"TARGET_FP"
|
"TARGET_FP"
|
||||||
"cvtq%-%/ %1,%0"
|
"cvtq%-%/ %1,%0"
|
||||||
[(set_attr "type" "fadd")
|
[(set_attr "type" "fadd")
|
||||||
(set_attr "trap" "yes")
|
(set_attr "trap" "yes")
|
||||||
(set_attr "round_suffix" "normal")
|
(set_attr "round_suffix" "normal")
|
||||||
(set_attr "trap_suffix" "sui")])
|
(set_attr "trap_suffix" "sui")
|
||||||
|
(set (attr "enabled")
|
||||||
|
(cond [(eq_attr "alternative" "0")
|
||||||
|
(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
|
||||||
|
]
|
||||||
|
(symbol_ref "true")))])
|
||||||
|
|
||||||
(define_insn_and_split "*floatsidf2_ieee"
|
(define_insn_and_split "*floatsidf2_ieee"
|
||||||
[(set (match_operand:DF 0 "register_operand" "=&f")
|
[(set (match_operand:DF 0 "register_operand" "=&f")
|
||||||
|
@ -2277,25 +2224,20 @@
|
||||||
"TARGET_HAS_XFLOATING_LIBS"
|
"TARGET_HAS_XFLOATING_LIBS"
|
||||||
"alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
|
"alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
|
||||||
|
|
||||||
(define_insn "*truncdfsf2_ieee"
|
|
||||||
[(set (match_operand:SF 0 "register_operand" "=&f")
|
|
||||||
(float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
|
|
||||||
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
||||||
"cvt%-%,%/ %R1,%0"
|
|
||||||
[(set_attr "type" "fadd")
|
|
||||||
(set_attr "trap" "yes")
|
|
||||||
(set_attr "round_suffix" "normal")
|
|
||||||
(set_attr "trap_suffix" "u_su_sui")])
|
|
||||||
|
|
||||||
(define_insn "truncdfsf2"
|
(define_insn "truncdfsf2"
|
||||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
[(set (match_operand:SF 0 "register_operand" "=f,&f")
|
||||||
(float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
|
(float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG,fG")))]
|
||||||
"TARGET_FP"
|
"TARGET_FP"
|
||||||
"cvt%-%,%/ %R1,%0"
|
"cvt%-%,%/ %R1,%0"
|
||||||
[(set_attr "type" "fadd")
|
[(set_attr "type" "fadd")
|
||||||
(set_attr "trap" "yes")
|
(set_attr "trap" "yes")
|
||||||
(set_attr "round_suffix" "normal")
|
(set_attr "round_suffix" "normal")
|
||||||
(set_attr "trap_suffix" "u_su_sui")])
|
(set_attr "trap_suffix" "u_su_sui")
|
||||||
|
(set (attr "enabled")
|
||||||
|
(cond [(eq_attr "alternative" "0")
|
||||||
|
(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
|
||||||
|
]
|
||||||
|
(symbol_ref "true")))])
|
||||||
|
|
||||||
(define_expand "trunctfdf2"
|
(define_expand "trunctfdf2"
|
||||||
[(use (match_operand:DF 0 "register_operand"))
|
[(use (match_operand:DF 0 "register_operand"))
|
||||||
|
@ -2672,27 +2614,21 @@
|
||||||
;; we need to have variants that expand the arguments from SFmode
|
;; we need to have variants that expand the arguments from SFmode
|
||||||
;; to DFmode.
|
;; to DFmode.
|
||||||
|
|
||||||
(define_insn "*cmpdf_ieee"
|
|
||||||
[(set (match_operand:DF 0 "register_operand" "=&f")
|
|
||||||
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
|
||||||
[(match_operand:DF 2 "reg_or_0_operand" "fG")
|
|
||||||
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
|
|
||||||
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
|
|
||||||
"cmp%-%C1%/ %R2,%R3,%0"
|
|
||||||
[(set_attr "type" "fadd")
|
|
||||||
(set_attr "trap" "yes")
|
|
||||||
(set_attr "trap_suffix" "su")])
|
|
||||||
|
|
||||||
(define_insn "*cmpdf_internal"
|
(define_insn "*cmpdf_internal"
|
||||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
[(set (match_operand:DF 0 "register_operand" "=f,&f")
|
||||||
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
(match_operator:DF 1 "alpha_fp_comparison_operator"
|
||||||
[(match_operand:DF 2 "reg_or_0_operand" "fG")
|
[(match_operand:DF 2 "reg_or_0_operand" "fG,fG")
|
||||||
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
|
(match_operand:DF 3 "reg_or_0_operand" "fG,fG")]))]
|
||||||
"TARGET_FP"
|
"TARGET_FP"
|
||||||
"cmp%-%C1%/ %R2,%R3,%0"
|
"cmp%-%C1%/ %R2,%R3,%0"
|
||||||
[(set_attr "type" "fadd")
|
[(set_attr "type" "fadd")
|
||||||
(set_attr "trap" "yes")
|
(set_attr "trap" "yes")
|
||||||
(set_attr "trap_suffix" "su")])
|
(set_attr "trap_suffix" "su")
|
||||||
|
(set (attr "enabled")
|
||||||
|
(cond [(eq_attr "alternative" "0")
|
||||||
|
(symbol_ref "alpha_fptm < ALPHA_FPTM_SU")
|
||||||
|
]
|
||||||
|
(symbol_ref "true")))])
|
||||||
|
|
||||||
(define_insn "*cmpdf_ext1"
|
(define_insn "*cmpdf_ext1"
|
||||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||||
|
|
Loading…
Reference in New Issue