RISC-V: Minimal support of vector extensions
gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_implied_info): Add vector extensions. (riscv_ext_version_table): Add version info for vector extensions. (riscv_ext_flag_table): Add option mask for vector extensions. * config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): New. (MASK_VECTOR_EEW_64): New. (MASK_VECTOR_EEW_FP_32): New. (MASK_VECTOR_EEW_FP_64): New. (MASK_ZVL32B): New. (MASK_ZVL64B): New. (MASK_ZVL128B): New. (MASK_ZVL256B): New. (MASK_ZVL512B): New. (MASK_ZVL1024B): New. (MASK_ZVL2048B): New. (MASK_ZVL4096B): New. (MASK_ZVL8192B): New. (MASK_ZVL16384B): New. (MASK_ZVL32768B): New. (MASK_ZVL65536B): New. (TARGET_ZVL32B): New. (TARGET_ZVL64B): New. (TARGET_ZVL128B): New. (TARGET_ZVL256B): New. (TARGET_ZVL512B): New. (TARGET_ZVL1024B): New. (TARGET_ZVL2048B): New. (TARGET_ZVL4096B): New. (TARGET_ZVL8192B): New. (TARGET_ZVL16384B): New. (TARGET_ZVL32768B): New. (TARGET_ZVL65536B): New. * config/riscv/riscv.opt (Mask(VECTOR)): New. (riscv_vector_eew_flags): New. (riscv_zvl_flags): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-14.c: New. * gcc.target/riscv/predef-15.c: Ditto. * gcc.target/riscv/predef-16.c: Ditto.
This commit is contained in:
Kito Cheng
parent
c8bdb34520
commit
e7da31ba20
@ -64,6 +64,38 @@ static const riscv_implied_info_t riscv_implied_info[] =
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{"zks", "zbkx"},
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{"zks", "zksed"},
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{"zks", "zksh"},
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{"v", "zvl128b"},
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{"v", "zve64d"},
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{"zve32f", "f"},
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{"zve64f", "f"},
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{"zve64d", "d"},
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{"zve32x", "zvl32b"},
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{"zve32f", "zve32x"},
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{"zve32f", "zvl32b"},
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{"zve64x", "zve32x"},
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{"zve64x", "zvl64b"},
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{"zve64f", "zve32f"},
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{"zve64f", "zve64x"},
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{"zve64f", "zvl64b"},
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{"zve64d", "zve64f"},
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{"zve64d", "zvl64b"},
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{"zvl64b", "zvl32b"},
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{"zvl128b", "zvl64b"},
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{"zvl256b", "zvl128b"},
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{"zvl512b", "zvl256b"},
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{"zvl1024b", "zvl512b"},
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{"zvl2048b", "zvl1024b"},
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{"zvl4096b", "zvl2048b"},
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{"zvl8192b", "zvl4096b"},
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{"zvl16384b", "zvl8192b"},
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{"zvl32768b", "zvl16384b"},
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{"zvl65536b", "zvl32768b"},
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{NULL, NULL}
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};
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@ -109,6 +141,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
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{"c", ISA_SPEC_CLASS_20190608, 2, 0},
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{"c", ISA_SPEC_CLASS_2P2, 2, 0},
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{"v", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
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{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
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@ -131,6 +165,26 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
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{"zksh", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zkt", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve32x", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve32f", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve32d", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve64x", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve64f", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve64d", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl32b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl64b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl128b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl256b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl512b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl1024b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl2048b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl4096b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl8192b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl16384b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
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/* Terminate the list. */
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{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
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};
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@ -965,6 +1019,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
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{"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT},
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{"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
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{"c", &gcc_options::x_target_flags, MASK_RVC},
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{"v", &gcc_options::x_target_flags, MASK_VECTOR},
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{"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
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{"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
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@ -985,6 +1040,37 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
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{"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
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{"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT},
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{"zve32x", &gcc_options::x_target_flags, MASK_VECTOR},
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{"zve32f", &gcc_options::x_target_flags, MASK_VECTOR},
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{"zve64x", &gcc_options::x_target_flags, MASK_VECTOR},
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{"zve64f", &gcc_options::x_target_flags, MASK_VECTOR},
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{"zve64d", &gcc_options::x_target_flags, MASK_VECTOR},
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/* We don't need to put complete EEW/EEW_FP info here, due to the
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implication relation of vector extension.
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e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_EEW_FP_64,
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MASK_VECTOR_EEW_FP_32, MASK_VECTOR_EEW_64 and MASK_VECTOR_EEW_32
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due to the extension implication. */
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{"zve32x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_32},
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{"zve32f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
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{"zve64x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_64},
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{"zve64f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
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{"zve64d", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_64},
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{"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
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{"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
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{"zvl128b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B},
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{"zvl256b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL256B},
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{"zvl512b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL512B},
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{"zvl1024b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL1024B},
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{"zvl2048b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL2048B},
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{"zvl4096b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL4096B},
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{"zvl8192b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL8192B},
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{"zvl16384b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL16384B},
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{"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
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{"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
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{NULL, NULL, 0}
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};
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@ -105,4 +105,35 @@ enum stack_protector_guard {
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#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
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#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
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#define MASK_VECTOR_EEW_32 (1 << 0)
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#define MASK_VECTOR_EEW_64 (1 << 1)
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#define MASK_VECTOR_EEW_FP_32 (1 << 2)
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#define MASK_VECTOR_EEW_FP_64 (1 << 3)
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#define MASK_ZVL32B (1 << 0)
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#define MASK_ZVL64B (1 << 1)
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#define MASK_ZVL128B (1 << 2)
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#define MASK_ZVL256B (1 << 3)
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#define MASK_ZVL512B (1 << 4)
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#define MASK_ZVL1024B (1 << 5)
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#define MASK_ZVL2048B (1 << 6)
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#define MASK_ZVL4096B (1 << 7)
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#define MASK_ZVL8192B (1 << 8)
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#define MASK_ZVL16384B (1 << 9)
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#define MASK_ZVL32768B (1 << 10)
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#define MASK_ZVL65536B (1 << 11)
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#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
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#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
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#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
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#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
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#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
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#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
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#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
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#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
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#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
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#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
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#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
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#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
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#endif /* ! GCC_RISCV_OPTS_H */
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@ -146,6 +146,8 @@ Mask(RVC)
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Mask(RVE)
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Mask(VECTOR)
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mriscv-attribute
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Target Var(riscv_emit_attribute_p) Init(-1)
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Emit RISC-V ELF attribute.
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@ -201,6 +203,12 @@ int riscv_zb_subext
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TargetVariable
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int riscv_zk_subext
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TargetVariable
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int riscv_vector_eew_flags
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TargetVariable
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int riscv_zvl_flags
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Enum
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Name(isa_spec_class) Type(enum riscv_isa_spec_class)
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Supported ISA specs (for use with the -misa-spec= option):
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83
gcc/testsuite/gcc.target/riscv/predef-14.c
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83
gcc/testsuite/gcc.target/riscv/predef-14.c
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@ -0,0 +1,83 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
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int main () {
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#ifndef __riscv_arch_test
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#error "__riscv_arch_test"
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#endif
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#if __riscv_xlen != 32
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#error "__riscv_xlen"
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#endif
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#if !defined(__riscv_i)
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#error "__riscv_i"
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#endif
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#if defined(__riscv_c)
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#error "__riscv_c"
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#endif
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#if defined(__riscv_e)
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#error "__riscv_e"
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#endif
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#if defined(__riscv_a)
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#error "__riscv_a"
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#endif
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#if defined(__riscv_m)
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#error "__riscv_m"
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#endif
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#if !defined(__riscv_f)
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#error "__riscv_f"
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#endif
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#if !defined(__riscv_d)
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#error "__riscv_d"
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#endif
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#if !defined(__riscv_v)
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#error "__riscv_v"
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#endif
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#if !defined(__riscv_zvl32b)
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#error "__riscv_zvl32b"
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#endif
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#if !defined(__riscv_zvl64b)
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#error "__riscv_zvl64b"
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#endif
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#if !defined(__riscv_zvl128b)
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#error "__riscv_zvl128b"
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#endif
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#if defined(__riscv_zvl256b)
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#error "__riscv_zvl256b"
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#endif
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#if !defined(__riscv_zve32x)
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#error "__riscv_zve32x"
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#endif
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#if !defined(__riscv_zve32f)
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#error "__riscv_zve32f"
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#endif
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#if !defined(__riscv_zve64x)
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#error "__riscv_zve64x"
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#endif
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#if !defined(__riscv_zve64f)
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#error "__riscv_zve64f"
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#endif
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#if !defined(__riscv_zve64d)
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#error "__riscv_zve64d"
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#endif
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return 0;
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}
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91
gcc/testsuite/gcc.target/riscv/predef-15.c
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91
gcc/testsuite/gcc.target/riscv/predef-15.c
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
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int main () {
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#ifndef __riscv_arch_test
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#error "__riscv_arch_test"
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#endif
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#if __riscv_xlen != 64
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#error "__riscv_xlen"
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#endif
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#if !defined(__riscv_i)
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#error "__riscv_i"
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#endif
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#if defined(__riscv_c)
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#error "__riscv_c"
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#endif
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#if defined(__riscv_e)
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#error "__riscv_e"
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#endif
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#if defined(__riscv_a)
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#error "__riscv_a"
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#endif
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#if defined(__riscv_m)
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#error "__riscv_m"
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#endif
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#if !defined(__riscv_f)
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#error "__riscv_f"
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#endif
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#if !defined(__riscv_d)
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#error "__riscv_d"
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#endif
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#if !defined(__riscv_v)
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#error "__riscv_v"
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#endif
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#if !defined(__riscv_zvl32b)
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#error "__riscv_zvl32b"
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#endif
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#if !defined(__riscv_zvl64b)
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#error "__riscv_zvl64b"
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#endif
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#if !defined(__riscv_zvl128b)
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#error "__riscv_zvl128b"
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#endif
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#if !defined(__riscv_zvl256b)
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#error "__riscv_zvl256b"
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#endif
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#if !defined(__riscv_zvl512b)
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#error "__riscv_zvl512b"
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#endif
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#if defined(__riscv_zvl1024b)
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#error "__riscv_zvl1024b"
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#endif
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#if !defined(__riscv_zve32x)
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#error "__riscv_zve32x"
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#endif
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#if !defined(__riscv_zve32f)
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#error "__riscv_zve32f"
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#endif
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#if !defined(__riscv_zve64x)
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#error "__riscv_zve64x"
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#endif
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#if !defined(__riscv_zve64f)
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#error "__riscv_zve64f"
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#endif
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#if !defined(__riscv_zve64d)
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#error "__riscv_zve64d"
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#endif
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return 0;
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}
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91
gcc/testsuite/gcc.target/riscv/predef-16.c
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91
gcc/testsuite/gcc.target/riscv/predef-16.c
Normal file
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
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int main () {
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#ifndef __riscv_arch_test
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#error "__riscv_arch_test"
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#endif
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#if __riscv_xlen != 64
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#error "__riscv_xlen"
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#endif
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#if !defined(__riscv_i)
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#error "__riscv_i"
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#endif
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#if defined(__riscv_c)
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#error "__riscv_c"
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#endif
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#if defined(__riscv_e)
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#error "__riscv_e"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_a)
|
||||
#error "__riscv_a"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_m)
|
||||
#error "__riscv_m"
|
||||
#endif
|
||||
|
||||
#if !defined(__riscv_f)
|
||||
#error "__riscv_f"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_d)
|
||||
#error "__riscv_d"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_v)
|
||||
#error "__riscv_v"
|
||||
#endif
|
||||
|
||||
#if !defined(__riscv_zvl32b)
|
||||
#error "__riscv_zvl32b"
|
||||
#endif
|
||||
|
||||
#if !defined(__riscv_zvl64b)
|
||||
#error "__riscv_zvl64b"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_zvl128b)
|
||||
#error "__riscv_zvl128b"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_zvl256b)
|
||||
#error "__riscv_zvl256b"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_zvl512b)
|
||||
#error "__riscv_zvl512b"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_zvl1024b)
|
||||
#error "__riscv_zvl1024b"
|
||||
#endif
|
||||
|
||||
#if !defined(__riscv_zve32x)
|
||||
#error "__riscv_zve32x"
|
||||
#endif
|
||||
|
||||
#if !defined(__riscv_zve32f)
|
||||
#error "__riscv_zve32f"
|
||||
#endif
|
||||
|
||||
#if !defined(__riscv_zve64x)
|
||||
#error "__riscv_zve64x"
|
||||
#endif
|
||||
|
||||
#if !defined(__riscv_zve64f)
|
||||
#error "__riscv_zve64f"
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_zve64d)
|
||||
#error "__riscv_zve64d"
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user