c4x.c (valid_parallel_load_store): Flog functionality from old valid_parallel_operands_4.
* config/c4x/c4x.c (valid_parallel_load_store): Flog functionality from old valid_parallel_operands_4. (valid_parallel_operands_4): Check that operands for 4 operand parallel insns are valid, excluding load/store insns. * config/c4x/c4x.h (valid_parallel_load_store): Add prototype. * config/c4x/c4x.md (*movqf_parallel, *movqi_parallel): Use valid_parallel_load_store instead of valid_parallel_operands_4. (*absqf2_movqf_clobber, *floatqiqf2_movqf_clobber, *negqf2_movqf_clobber, *absqi2_movqi_clobber, *fixqfqi2_movqi_clobber, *negqi2_movqi_clobber, *notqi_movqi_clobber): Use valid_parallel_operands_4. (*subqf3_movqf_clobber, *ashlqi3_movqi_clobber, *ashrqi3_movqi_clobber, *lshrqi3_movqi_clobber, *subqi3_movqi_clobber): Use valid_parallel_operands_5. From-SVN: r24108
This commit is contained in:
Michael Hayes
Michael Hayes
parent
cd20cc860b
commit
e868a8406d
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@ -1,3 +1,20 @@
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Sun Dec 6 00:28:16 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.c (valid_parallel_load_store): Flog functionality
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from old valid_parallel_operands_4.
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(valid_parallel_operands_4): Check that operands for 4 operand
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parallel insns are valid, excluding load/store insns.
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* config/c4x/c4x.h (valid_parallel_load_store): Add prototype.
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* config/c4x/c4x.md (*movqf_parallel, *movqi_parallel): Use
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valid_parallel_load_store instead of valid_parallel_operands_4.
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(*absqf2_movqf_clobber, *floatqiqf2_movqf_clobber,
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*negqf2_movqf_clobber, *absqi2_movqi_clobber,
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*fixqfqi2_movqi_clobber, *negqi2_movqi_clobber,
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*notqi_movqi_clobber): Use valid_parallel_operands_4.
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(*subqf3_movqf_clobber, *ashlqi3_movqi_clobber,
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*ashrqi3_movqi_clobber, *lshrqi3_movqi_clobber,
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*subqi3_movqi_clobber): Use valid_parallel_operands_5.
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Sat Dec 5 23:52:01 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.c (iteration_info): Delete extern.
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@ -3209,8 +3209,7 @@ c4x_label_conflict (insn, jump, db)
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/* Validate combination of operands for parallel load/store instructions. */
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int
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valid_parallel_operands_4 (operands, mode)
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valid_parallel_load_store (operands, mode)
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rtx *operands;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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@ -3233,11 +3232,11 @@ valid_parallel_operands_4 (operands, mode)
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should be REGs and the other 2 should be MEMs. */
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/* This test prevents the multipack pass from using this pattern if
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op0 is used as an index or base register in op3, since this combination
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will require reloading. */
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op0 is used as an index or base register in op2 or op3, since
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this combination will require reloading. */
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if (GET_CODE (op0) == REG
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&& GET_CODE (op3) == MEM
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&& reg_mentioned_p (op0, XEXP (op3, 0)))
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&& ((GET_CODE (op2) == MEM && reg_mentioned_p (op0, XEXP (op2, 0)))
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|| (GET_CODE (op3) == MEM && reg_mentioned_p (op0, XEXP (op3, 0)))))
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return 0;
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/* LDI||LDI */
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@ -3265,8 +3264,32 @@ valid_parallel_operands_4 (operands, mode)
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}
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/* We only use this to check operands 1 and 2 since these may be
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commutative. It will need extending for the C32 opcodes. */
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int
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valid_parallel_operands_4 (operands, mode)
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rtx *operands;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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int regs = 0;
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rtx op0 = operands[0];
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rtx op2 = operands[2];
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if (GET_CODE (op0) == SUBREG)
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op0 = SUBREG_REG (op0);
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if (GET_CODE (op2) == SUBREG)
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op2 = SUBREG_REG (op2);
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/* This test prevents the multipack pass from using this pattern if
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op0 is used as an index or base register in op2, since this combination
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will require reloading. */
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if (GET_CODE (op0) == REG
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&& GET_CODE (op2) == MEM
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&& reg_mentioned_p (op0, XEXP (op2, 0)))
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return 0;
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return 1;
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}
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int
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valid_parallel_operands_5 (operands, mode)
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rtx *operands;
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@ -3274,18 +3297,21 @@ valid_parallel_operands_5 (operands, mode)
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{
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int regs = 0;
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rtx op0 = operands[0];
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rtx op1 = operands[1];
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rtx op2 = operands[2];
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rtx op3 = operands[3];
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if (GET_CODE (op0) == SUBREG)
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op0 = SUBREG_REG (op0);
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if (GET_CODE (op1) == SUBREG)
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op1 = SUBREG_REG (op1);
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if (GET_CODE (op2) == SUBREG)
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op2 = SUBREG_REG (op2);
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/* The patterns should only allow ext_low_reg_operand() or
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par_ind_operand() operands. */
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if (GET_CODE (op0) == REG)
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par_ind_operand() operands. Operands 1 and 2 may be commutative
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but only one of them can be a register. */
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if (GET_CODE (op1) == REG)
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regs++;
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if (GET_CODE (op2) == REG)
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regs++;
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@ -2663,6 +2663,8 @@ extern int legitimize_operands ();
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extern int valid_operands ();
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extern int valid_parallel_load_store ();
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extern int valid_parallel_operands_4 ();
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extern int valid_parallel_operands_5 ();
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@ -1262,7 +1262,7 @@
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(match_operand:QI 1 "parallel_operand" "S<>,q,S<>,q"))
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(set (match_operand:QI 2 "parallel_operand" "=q,S<>,S<>,q")
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(match_operand:QI 3 "parallel_operand" "S<>,q,q,S<>"))]
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"valid_parallel_operands_4 (operands, QImode)"
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"valid_parallel_load_store (operands, QImode)"
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"@
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ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2
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sti1\\t%1,%0\\n||\\tsti2\\t%3,%2
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@ -2952,7 +2952,7 @@
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(match_operand:QF 1 "parallel_operand" "S<>,q,S<>,q"))
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(set (match_operand:QF 2 "parallel_operand" "=q,S<>,S<>,q")
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(match_operand:QF 3 "parallel_operand" "S<>,q,q,S<>"))]
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"valid_parallel_operands_4 (operands, QFmode)"
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"valid_parallel_load_store (operands, QFmode)"
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"@
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ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2
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stf1\\t%1,%0\\n||\\tstf2\\t%3,%2
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@ -3800,7 +3800,7 @@
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(set (match_operand:QF 2 "par_ind_operand" "=S<>")
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(match_operand:QF 3 "ext_low_reg_operand" "q"))
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(clobber (reg:CC_NOOV 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
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"absf\\t%1,%0\\n||\\tstf\\t%3,%2"
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[(set_attr "type" "binarycc")])
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@ -3823,13 +3823,13 @@
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; FLOAT/STF
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;
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(define_insn "*floatqiqf_movqf_clobber"
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(define_insn "*floatqiqf2_movqf_clobber"
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[(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
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(float:QF (match_operand:QI 1 "par_ind_operand" "S<>")))
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(set (match_operand:QF 2 "par_ind_operand" "=S<>")
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(match_operand:QF 3 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
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"float\\t%1,%0\\n||\\tstf\\t%3,%2"
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[(set_attr "type" "binarycc")])
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@ -3891,7 +3891,7 @@
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(set (match_operand:QF 2 "par_ind_operand" "=S<>")
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(match_operand:QF 3 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
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"negf\\t%1,%0\\n||\\tstf\\t%3,%2"
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[(set_attr "type" "binarycc")])
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@ -3902,11 +3902,11 @@
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(define_insn "*subqf3_movqf_clobber"
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[(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
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(minus:QF (match_operand:QF 1 "ext_low_reg_operand" "q")
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(match_operand:QF 2 "par_ind_operand" "S<>")))
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(match_operand:QF 2 "par_ind_operand" "S<>")))
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(set (match_operand:QF 3 "par_ind_operand" "=S<>")
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(match_operand:QF 4 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
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"subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
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[(set_attr "type" "binarycc")])
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@ -3925,7 +3925,7 @@
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(set (match_operand:QI 2 "par_ind_operand" "=S<>")
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(match_operand:QI 3 "ext_low_reg_operand" "q"))
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(clobber (reg:CC_NOOV 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
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"absi\\t%1,%0\\n||\\tsti\\t%3,%2"
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[(set_attr "type" "binarycc")])
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@ -3970,7 +3970,7 @@
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(set (match_operand:QI 3 "par_ind_operand" "=S<>")
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(match_operand:QI 4 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
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"ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
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[(set_attr "type" "binarycc")])
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@ -3978,14 +3978,14 @@
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; ASH(right)/STI
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;
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(define_insn "*ashlqi3_movqi_clobber"
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(define_insn "*ashrqi3_movqi_clobber"
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[(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
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(ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
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(neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
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(set (match_operand:QI 3 "par_ind_operand" "=S<>")
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(match_operand:QI 4 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
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"ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
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[(set_attr "type" "binarycc")])
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@ -3999,7 +3999,7 @@
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(set (match_operand:QI 2 "par_ind_operand" "=S<>")
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(match_operand:QI 3 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
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"fix\\t%1,%0\\n||\\tsti\\t%3,%2"
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[(set_attr "type" "binarycc")])
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@ -4014,7 +4014,7 @@
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(set (match_operand:QI 3 "par_ind_operand" "=S<>")
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(match_operand:QI 4 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
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"lsh3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
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[(set_attr "type" "binarycc")])
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@ -4078,7 +4078,7 @@
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(set (match_operand:QI 2 "par_ind_operand" "=S<>")
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(match_operand:QI 3 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
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"negi\\t%1,%0\\n||\\tsti\\t%3,%2"
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[(set_attr "type" "binarycc")])
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@ -4092,7 +4092,7 @@
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(set (match_operand:QI 2 "par_ind_operand" "=S<>")
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(match_operand:QI 3 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
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"not\\t%1,%0\\n||\\tsti\\t%3,%2"
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[(set_attr "type" "binarycc")])
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@ -4122,7 +4122,7 @@
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(set (match_operand:QI 3 "par_ind_operand" "=S<>")
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(match_operand:QI 4 "ext_low_reg_operand" "q"))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL"
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"TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
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"subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
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[(set_attr "type" "binarycc")])
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