ia64.c (ia64_expand_widen_sum): New.
* config/ia64/ia64.c (ia64_expand_widen_sum): New.
(ia64_expand_dot_prod_v8qi): New.
* config/ia64/ia64-protos.h: Update.
* config/ia64/vect.md (pmpy2_r, pmpy2_l, widen_usumv8qi3,
widen_usumv4hi3, widen_ssumv8qi3, widen_ssumv4hi3, udot_prodv8qi,
sdot_prodv8qi, sdot_prodv4hi): New.
(reduc_splus_v2sf): Rename from reduc_plus_v2sf.
From-SVN: r104426
This commit is contained in:
Richard Henderson
Richard Henderson
parent
a220ee348d
commit
e898620c39
@ -1,3 +1,13 @@
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2005-09-19 Richard Henderson <rth@redhat.com>
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* config/ia64/ia64.c (ia64_expand_widen_sum): New.
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(ia64_expand_dot_prod_v8qi): New.
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* config/ia64/ia64-protos.h: Update.
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* config/ia64/vect.md (pmpy2_r, pmpy2_l, widen_usumv8qi3,
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widen_usumv4hi3, widen_ssumv8qi3, widen_ssumv4hi3, udot_prodv8qi,
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sdot_prodv8qi, sdot_prodv4hi): New.
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(reduc_splus_v2sf): Rename from reduc_plus_v2sf.
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2005-09-19 Richard Henderson <rth@redhat.com>
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PR 23941
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@ -50,6 +50,8 @@ extern bool ia64_expand_movxf_movrf (enum machine_mode, rtx[]);
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extern rtx ia64_expand_compare (enum rtx_code, enum machine_mode);
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extern void ia64_expand_vecint_cmov (rtx[]);
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extern bool ia64_expand_vecint_minmax (enum rtx_code, enum machine_mode, rtx[]);
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extern void ia64_expand_widen_sum (rtx[], bool);
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extern void ia64_expand_dot_prod_v8qi (rtx[], bool);
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extern void ia64_expand_call (rtx, rtx, rtx, int);
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extern void ia64_split_call (rtx, rtx, rtx, rtx, rtx, int, int);
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extern void ia64_reload_gp (void);
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@ -1766,6 +1766,113 @@ ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
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return true;
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}
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/* Emit an integral vector widening sum operations. */
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void
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ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
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{
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rtx l, h, x, s;
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enum machine_mode wmode, mode;
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rtx (*unpack_l) (rtx, rtx, rtx);
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rtx (*unpack_h) (rtx, rtx, rtx);
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rtx (*plus) (rtx, rtx, rtx);
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wmode = GET_MODE (operands[0]);
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mode = GET_MODE (operands[1]);
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switch (mode)
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{
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case V8QImode:
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unpack_l = gen_unpack1_l;
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unpack_h = gen_unpack1_h;
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plus = gen_addv4hi3;
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break;
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case V4HImode:
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unpack_l = gen_unpack2_l;
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unpack_h = gen_unpack2_h;
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plus = gen_addv2si3;
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break;
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default:
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gcc_unreachable ();
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}
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/* Fill in x with the sign extension of each element in op1. */
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if (unsignedp)
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x = CONST0_RTX (mode);
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else
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{
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bool neg;
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x = gen_reg_rtx (mode);
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neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
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CONST0_RTX (mode));
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gcc_assert (!neg);
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}
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l = gen_reg_rtx (wmode);
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h = gen_reg_rtx (wmode);
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s = gen_reg_rtx (wmode);
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emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
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emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
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emit_insn (plus (s, l, operands[2]));
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emit_insn (plus (operands[0], h, s));
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}
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/* Emit a signed or unsigned V8QI dot product operation. */
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void
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ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
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{
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rtx l1, l2, h1, h2, x1, x2, p1, p2, p3, p4, s1, s2, s3;
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/* Fill in x1 and x2 with the sign extension of each element. */
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if (unsignedp)
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x1 = x2 = CONST0_RTX (V8QImode);
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else
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{
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bool neg;
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x1 = gen_reg_rtx (V8QImode);
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x2 = gen_reg_rtx (V8QImode);
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neg = ia64_expand_vecint_compare (LT, V8QImode, x1, operands[1],
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CONST0_RTX (V8QImode));
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gcc_assert (!neg);
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neg = ia64_expand_vecint_compare (LT, V8QImode, x2, operands[2],
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CONST0_RTX (V8QImode));
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gcc_assert (!neg);
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}
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l1 = gen_reg_rtx (V4HImode);
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l2 = gen_reg_rtx (V4HImode);
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h1 = gen_reg_rtx (V4HImode);
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h2 = gen_reg_rtx (V4HImode);
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emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l1), operands[1], x1));
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emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l2), operands[2], x2));
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emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h1), operands[1], x1));
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emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h2), operands[2], x2));
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p1 = gen_reg_rtx (V2SImode);
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p2 = gen_reg_rtx (V2SImode);
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p3 = gen_reg_rtx (V2SImode);
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p4 = gen_reg_rtx (V2SImode);
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emit_insn (gen_pmpy2_r (p1, l1, l2));
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emit_insn (gen_pmpy2_l (p2, l1, l2));
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emit_insn (gen_pmpy2_r (p3, h1, h2));
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emit_insn (gen_pmpy2_l (p4, h1, h2));
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s1 = gen_reg_rtx (V2SImode);
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s2 = gen_reg_rtx (V2SImode);
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s3 = gen_reg_rtx (V2SImode);
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emit_insn (gen_addv2si3 (s1, p1, p2));
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emit_insn (gen_addv2si3 (s2, p3, p4));
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emit_insn (gen_addv2si3 (s3, s1, operands[3]));
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emit_insn (gen_addv2si3 (operands[0], s2, s3));
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}
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/* Emit the appropriate sequence for a call. */
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void
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@ -212,6 +212,36 @@
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"pmpyshr2 %0 = %1, %2, 0"
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[(set_attr "itanium_class" "mmmul")])
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(define_insn "pmpy2_r"
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[(set (match_operand:V2SI 0 "gr_register_operand" "=r")
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(mult:V2SI
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(vec_select:V2SI
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(sign_extend:V4SI
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(match_operand:V4HI 1 "gr_register_operand" "r"))
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(parallel [(const_int 0) (const_int 2)]))
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(vec_select:V2SI
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(sign_extend:V4SI
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(match_operand:V4HI 2 "gr_register_operand" "r"))
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(parallel [(const_int 0) (const_int 2)]))))]
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""
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"pmpy2.r %0 = %1, %2"
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[(set_attr "itanium_class" "mmshf")])
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(define_insn "pmpy2_l"
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[(set (match_operand:V2SI 0 "gr_register_operand" "=r")
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(mult:V2SI
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(vec_select:V2SI
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(sign_extend:V4SI
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(match_operand:V4HI 1 "gr_register_operand" "r"))
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(parallel [(const_int 1) (const_int 3)]))
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(vec_select:V2SI
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(sign_extend:V4SI
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(match_operand:V4HI 2 "gr_register_operand" "r"))
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(parallel [(const_int 1) (const_int 3)]))))]
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""
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"pmpy2.l %0 = %1, %2"
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[(set_attr "itanium_class" "mmshf")])
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(define_expand "umax<mode>3"
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[(set (match_operand:VECINT 0 "gr_register_operand" "")
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(umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
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@ -331,6 +361,88 @@
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operands[1] = gen_lowpart (DImode, operands[1]);
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})
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(define_expand "widen_usumv8qi3"
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[(match_operand:V4HI 0 "gr_register_operand" "")
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(match_operand:V8QI 1 "gr_register_operand" "")
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(match_operand:V4HI 2 "gr_register_operand" "")]
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""
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{
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ia64_expand_widen_sum (operands, true);
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DONE;
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})
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(define_expand "widen_usumv4hi3"
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[(match_operand:V2SI 0 "gr_register_operand" "")
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(match_operand:V4HI 1 "gr_register_operand" "")
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(match_operand:V2SI 2 "gr_register_operand" "")]
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""
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{
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ia64_expand_widen_sum (operands, true);
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DONE;
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})
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(define_expand "widen_ssumv8qi3"
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[(match_operand:V4HI 0 "gr_register_operand" "")
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(match_operand:V8QI 1 "gr_register_operand" "")
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(match_operand:V4HI 2 "gr_register_operand" "")]
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""
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{
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ia64_expand_widen_sum (operands, false);
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DONE;
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})
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(define_expand "widen_ssumv4hi3"
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[(match_operand:V2SI 0 "gr_register_operand" "")
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(match_operand:V4HI 1 "gr_register_operand" "")
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(match_operand:V2SI 2 "gr_register_operand" "")]
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""
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{
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ia64_expand_widen_sum (operands, false);
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DONE;
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})
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(define_expand "udot_prodv8qi"
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[(match_operand:V2SI 0 "gr_register_operand" "")
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(match_operand:V8QI 1 "gr_register_operand" "")
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(match_operand:V8QI 2 "gr_register_operand" "")
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(match_operand:V2SI 3 "gr_register_operand" "")]
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""
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{
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ia64_expand_dot_prod_v8qi (operands, true);
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DONE;
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})
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(define_expand "sdot_prodv8qi"
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[(match_operand:V2SI 0 "gr_register_operand" "")
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(match_operand:V8QI 1 "gr_register_operand" "")
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(match_operand:V8QI 2 "gr_register_operand" "")
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(match_operand:V2SI 3 "gr_register_operand" "")]
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""
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{
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ia64_expand_dot_prod_v8qi (operands, false);
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DONE;
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})
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(define_expand "sdot_prodv4hi"
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[(match_operand:V2SI 0 "gr_register_operand" "")
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(match_operand:V4HI 1 "gr_register_operand" "")
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(match_operand:V4HI 2 "gr_register_operand" "")
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(match_operand:V2SI 3 "gr_register_operand" "")]
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""
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{
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rtx l, r, t;
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r = gen_reg_rtx (V2SImode);
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l = gen_reg_rtx (V2SImode);
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t = gen_reg_rtx (V2SImode);
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emit_insn (gen_pmpy2_r (r, operands[1], operands[2]));
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emit_insn (gen_pmpy2_l (l, operands[1], operands[2]));
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emit_insn (gen_addv2si3 (t, r, operands[3]));
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emit_insn (gen_addv2si3 (operands[0], t, l));
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DONE;
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})
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(define_expand "vcond<mode>"
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[(set (match_operand:VECINT 0 "gr_register_operand" "")
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(if_then_else:VECINT
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@ -717,15 +829,11 @@
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;; padd.uus
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;; pavg
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;; pavgsub
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;; pmpy
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;; pmpyshr, general form
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;; psad
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;; pshladd
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;; pshradd
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;; psub.uus
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;; vec_set<mode>
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;; vec_extract<mode>
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;; vec_init<mode>
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;; Floating point vector operations
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@ -947,7 +1055,7 @@
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"fpmin %0 = %1, %2"
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[(set_attr "itanium_class" "fmisc")])
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(define_expand "reduc_plus_v2sf"
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(define_expand "reduc_splus_v2sf"
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[(match_operand:V2SF 0 "fr_register_operand" "")
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(match_operand:V2SF 1 "fr_register_operand" "")]
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""
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