Remove TARGET_RELAXED_ORDERING and optimize for weak memory models.
This patch removes the special casing for targets with relaxed memory ordering and handles guard accesses with equivalent atomic load acquire operations. In this process we change the algorithm to load the guard variable with an atomic load that has ACQUIRE semantics. This then means that on targets which have weak memory models, the fast path is inlined and can directly use a load-acquire instruction where available (and yay! one more hook gone). 2015-06-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR c++/66192 PR target/66200 * doc/tm.texi: Regenerate. * doc/tm.texi.in (TARGET_RELAXED_ORDERING): Delete. * target.def (TARGET_RELAXED_ORDERING): Likewise. * config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise. * config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Likewise. * config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Likewise. * config/sparc/linux.h (SPARC_RELAXED_ORDERING): Likewise. * config/sparc/linux64.h (SPARC_RELAXED_ORDERING): Likewise. * config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Likewise. * config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Likewise. * system.h (TARGET_RELAXED_ORDERING): Poison. 2015-06-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR c++/66192 PR target/66200 * cp-tree.h (get_guard_cond): Adjust declaration * decl.c (expand_static_init): Use atomic load acquire and adjust call to get_guard_cond. * decl2.c (build_atomic_load_byte): New function. (get_guard_cond): Handle thread_safety. (one_static_initialization_or_destruction): Adjust call to get_guard_cond. From-SVN: r224118
This commit is contained in:
Ramana Radhakrishnan
Ramana Radhakrishnan
parent
e2fc719399
commit
e93ca5cade
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@ -1,3 +1,18 @@
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2015-06-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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PR c++/66192
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PR target/66200
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* doc/tm.texi: Regenerate.
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* doc/tm.texi.in (TARGET_RELAXED_ORDERING): Delete.
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* target.def (TARGET_RELAXED_ORDERING): Likewise.
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* config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise.
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* config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Likewise.
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* config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Likewise.
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* config/sparc/linux.h (SPARC_RELAXED_ORDERING): Likewise.
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* config/sparc/linux64.h (SPARC_RELAXED_ORDERING): Likewise.
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* config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Likewise.
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* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Likewise.
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2015-06-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64.c (aarch64_override_options): Unconditionally
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@ -9987,12 +9987,6 @@ alpha_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
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#undef TARGET_EXPAND_BUILTIN_VA_START
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#define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start
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/* The Alpha architecture does not require sequential consistency. See
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http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
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for an example of how it can be violated in practice. */
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING true
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#undef TARGET_OPTION_OVERRIDE
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#define TARGET_OPTION_OVERRIDE alpha_option_override
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@ -630,11 +630,6 @@ static const struct attribute_spec ia64_attribute_table[] =
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#define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
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ia64_libgcc_floating_mode_supported_p
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/* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
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in an order different from the specified program order. */
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING true
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#undef TARGET_LEGITIMATE_CONSTANT_P
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#define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
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#undef TARGET_LEGITIMATE_ADDRESS_P
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@ -1620,17 +1620,6 @@ static const struct attribute_spec rs6000_attribute_table[] =
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#define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
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#endif
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/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
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The PowerPC architecture requires only weak consistency among
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processors--that is, memory accesses between processors need not be
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sequentially consistent and memory accesses among processors can occur
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in any order. The ability to order memory accesses weakly provides
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opportunities for more efficient use of the system bus. Unless a
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dependency exists, the 604e allows read operations to precede store
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operations. */
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING true
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#ifdef HAVE_AS_TLS
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#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
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#define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
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@ -139,12 +139,6 @@ do { \
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/* Static stack checking is supported by means of probes. */
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#define STACK_CHECK_STATIC_BUILTIN 1
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/* Linux currently uses RMO in uniprocessor mode, which is equivalent to
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TMO, and TMO in multiprocessor mode. But they reserve the right to
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change their minds. */
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#undef SPARC_RELAXED_ORDERING
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#define SPARC_RELAXED_ORDERING true
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#undef NEED_INDICATE_EXEC_STACK
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#define NEED_INDICATE_EXEC_STACK 1
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@ -253,12 +253,6 @@ do { \
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/* Static stack checking is supported by means of probes. */
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#define STACK_CHECK_STATIC_BUILTIN 1
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/* Linux currently uses RMO in uniprocessor mode, which is equivalent to
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TMO, and TMO in multiprocessor mode. But they reserve the right to
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change their minds. */
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#undef SPARC_RELAXED_ORDERING
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#define SPARC_RELAXED_ORDERING true
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#undef NEED_INDICATE_EXEC_STACK
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#define NEED_INDICATE_EXEC_STACK 1
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@ -808,9 +808,6 @@ char sparc_hard_reg_printed[8];
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#define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
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#endif
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
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#undef TARGET_OPTION_OVERRIDE
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#define TARGET_OPTION_OVERRIDE sparc_option_override
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@ -106,17 +106,6 @@ extern enum cmodel sparc_cmodel;
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#define SPARC_DEFAULT_CMODEL CM_32
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/* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
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which requires the following macro to be true if enabled. Prior to V9,
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there are no instructions to even talk about memory synchronization.
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Note that the UltraSPARC III processors don't implement RMO, unlike the
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UltraSPARC II processors. Niagara, Niagara-2, and Niagara-3 do not
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implement RMO either.
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Default to false; for example, Solaris never enables RMO, only ever uses
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total memory ordering (TMO). */
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#define SPARC_RELAXED_ORDERING false
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/* Do not use the .note.GNU-stack convention by default. */
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#define NEED_INDICATE_EXEC_STACK 0
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@ -1,3 +1,15 @@
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2015-06-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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PR c++/66192
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PR target/66200
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* cp-tree.h (get_guard_cond): Adjust declaration
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* decl.c (expand_static_init): Use atomic load acquire
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and adjust call to get_guard_cond.
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* decl2.c (build_atomic_load_byte): New function.
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(get_guard_cond): Handle thread_safety.
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(one_static_initialization_or_destruction): Adjust call to
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get_guard_cond.
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2015-06-03 Jason Merrill <jason@redhat.com>
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PR c++/44282
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@ -5491,7 +5491,7 @@ extern bool mark_used (tree, tsubst_flags_t);
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extern void finish_static_data_member_decl (tree, tree, bool, tree, int);
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extern tree cp_build_parm_decl (tree, tree);
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extern tree get_guard (tree);
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extern tree get_guard_cond (tree);
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extern tree get_guard_cond (tree, bool);
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extern tree set_guard (tree);
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extern tree get_tls_wrapper_fn (tree);
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extern void mark_needed (tree);
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@ -7227,7 +7227,7 @@ expand_static_init (tree decl, tree init)
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looks like:
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static <type> guard;
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if (!guard.first_byte) {
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if (!__atomic_load (guard.first_byte)) {
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if (__cxa_guard_acquire (&guard)) {
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bool flag = false;
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try {
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@ -7257,16 +7257,11 @@ expand_static_init (tree decl, tree init)
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/* Create the guard variable. */
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guard = get_guard (decl);
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/* This optimization isn't safe on targets with relaxed memory
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consistency. On such targets we force synchronization in
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__cxa_guard_acquire. */
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if (!targetm.relaxed_ordering || !thread_guard)
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{
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/* Begin the conditional initialization. */
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if_stmt = begin_if_stmt ();
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finish_if_stmt_cond (get_guard_cond (guard), if_stmt);
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then_clause = begin_compound_stmt (BCS_NO_SCOPE);
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}
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/* Begin the conditional initialization. */
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if_stmt = begin_if_stmt ();
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finish_if_stmt_cond (get_guard_cond (guard, thread_guard), if_stmt);
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then_clause = begin_compound_stmt (BCS_NO_SCOPE);
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if (thread_guard)
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{
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@ -7335,12 +7330,9 @@ expand_static_init (tree decl, tree init)
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finish_if_stmt (inner_if_stmt);
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}
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if (!targetm.relaxed_ordering || !thread_guard)
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{
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finish_compound_stmt (then_clause);
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finish_then_clause (if_stmt);
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finish_if_stmt (if_stmt);
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}
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finish_compound_stmt (then_clause);
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finish_then_clause (if_stmt);
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finish_if_stmt (if_stmt);
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}
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else if (DECL_THREAD_LOCAL_P (decl))
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tls_aggregates = tree_cons (init, decl, tls_aggregates);
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@ -3034,6 +3034,27 @@ get_guard (tree decl)
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return guard;
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}
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/* Return an atomic load of src with the appropriate memory model. */
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static tree
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build_atomic_load_byte (tree src, HOST_WIDE_INT model)
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{
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tree ptr_type = build_pointer_type (char_type_node);
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tree mem_model = build_int_cst (integer_type_node, model);
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tree t, addr, val;
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unsigned int size;
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int fncode;
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size = tree_to_uhwi (TYPE_SIZE_UNIT (char_type_node));
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fncode = BUILT_IN_ATOMIC_LOAD_N + exact_log2 (size) + 1;
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t = builtin_decl_implicit ((enum built_in_function) fncode);
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addr = build1 (ADDR_EXPR, ptr_type, src);
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val = build_call_expr (t, 2, addr, mem_model);
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return val;
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}
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/* Return those bits of the GUARD variable that should be set when the
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guarded entity is actually initialized. */
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@ -3060,12 +3081,14 @@ get_guard_bits (tree guard)
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variable has already been initialized. */
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tree
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get_guard_cond (tree guard)
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get_guard_cond (tree guard, bool thread_safe)
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{
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tree guard_value;
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/* Check to see if the GUARD is zero. */
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guard = get_guard_bits (guard);
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if (!thread_safe)
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guard = get_guard_bits (guard);
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else
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guard = build_atomic_load_byte (guard, MEMMODEL_ACQUIRE);
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/* Mask off all but the low bit. */
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if (targetm.cxx.guard_mask_bit ())
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@ -3681,7 +3704,7 @@ one_static_initialization_or_destruction (tree decl, tree init, bool initp)
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/* When using __cxa_atexit, we never try to destroy
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anything from a static destructor. */
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gcc_assert (initp);
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guard_cond = get_guard_cond (guard);
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guard_cond = get_guard_cond (guard, false);
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}
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/* If we don't have __cxa_atexit, then we will be running
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destructors from .fini sections, or their equivalents. So,
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@ -11395,16 +11395,6 @@ routine for target specific customizations of the system printf
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and scanf formatter settings.
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@end defmac
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@deftypevr {Target Hook} bool TARGET_RELAXED_ORDERING
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If set to @code{true}, means that the target's memory model does not
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guarantee that loads which do not depend on one another will access
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main memory in the order of the instruction stream; if ordering is
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important, an explicit memory barrier must be used. This is true of
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many recent processors which implement a policy of ``relaxed,''
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``weak,'' or ``release'' memory consistency, such as Alpha, PowerPC,
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and ia64. The default is @code{false}.
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@end deftypevr
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@deftypefn {Target Hook} {const char *} TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN (const_tree @var{typelist}, const_tree @var{funcdecl}, const_tree @var{val})
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If defined, this macro returns the diagnostic message when it is
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illegal to pass argument @var{val} to function @var{funcdecl}
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@ -8143,8 +8143,6 @@ routine for target specific customizations of the system printf
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and scanf formatter settings.
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@end defmac
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@hook TARGET_RELAXED_ORDERING
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@hook TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
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@hook TARGET_INVALID_CONVERSION
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@ -964,7 +964,7 @@ extern void fancy_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
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TARGET_HANDLE_PRAGMA_EXTERN_PREFIX \
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TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN \
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TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD \
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TARGET_MD_ASM_CLOBBERS
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TARGET_MD_ASM_CLOBBERS TARGET_RELAXED_ORDERING
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/* Arrays that were deleted in favor of a functional interface. */
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#pragma GCC poison built_in_decls implicit_built_in_decls
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@ -5785,19 +5785,6 @@ for the primary source file, immediately after printing\n\
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this to be done. The default is false.",
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bool, false)
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/* True if the target is allowed to reorder memory accesses unless
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synchronization is explicitly requested. */
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DEFHOOKPOD
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(relaxed_ordering,
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"If set to @code{true}, means that the target's memory model does not\n\
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guarantee that loads which do not depend on one another will access\n\
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main memory in the order of the instruction stream; if ordering is\n\
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important, an explicit memory barrier must be used. This is true of\n\
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many recent processors which implement a policy of ``relaxed,''\n\
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``weak,'' or ``release'' memory consistency, such as Alpha, PowerPC,\n\
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and ia64. The default is @code{false}.",
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bool, false)
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/* Returns true if we should generate exception tables for use with the
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ARM EABI. The effects the encoding of function exception specifications. */
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DEFHOOKPOD
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