S/390: Make constant checking more strict
gcc/ChangeLog: 2015-12-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/predicates.md (const_mask_operand): New predicate. * config/s390/s390-builtins.def: Set a smaller bitmask for a few builtins. * config/s390/vector.md: Change predicate from immediate_operand to either const_int_operand or const_mask_operand. Add special insn conditions on patterns which have to exclude certain values. * config/s390/vx-builtins.md: Likewise. From-SVN: r231159
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@ -1,3 +1,12 @@
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2015-12-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* config/s390/predicates.md (const_mask_operand): New predicate.
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* config/s390/s390-builtins.def: Set a smaller bitmask for a few builtins.
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* config/s390/vector.md: Change predicate from immediate_operand
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to either const_int_operand or const_mask_operand. Add special
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insn conditions on patterns which have to exclude certain values.
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* config/s390/vx-builtins.md: Likewise.
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2015-12-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* config/s390/vector.md ("*vec_set<mode>"): Change shift count
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@ -34,6 +34,11 @@
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(and (match_code "const_int, const_double,const_vector")
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(match_test "op == CONSTM1_RTX (mode)")))
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;; Return true if OP is a 4 bit mask operand
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(define_predicate "const_mask_operand"
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(and (match_code "const_int")
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(match_test "UINTVAL (op) < 16")))
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;; Return true if OP is constant.
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(define_special_predicate "consttable_operand"
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@ -2470,15 +2470,15 @@ OB_DEF (s390_vec_ctd, s390_vec_ctd_s64, s390_vec_ctd_u64,
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OB_DEF_VAR (s390_vec_ctd_s64, s390_vec_ctd_s64, O2_U5, BT_OV_V2DF_V2DI_INT) /* vcdgb */
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OB_DEF_VAR (s390_vec_ctd_u64, s390_vec_ctd_u64, O2_U5, BT_OV_V2DF_UV2DI_INT) /* vcdlgb */
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B_DEF (s390_vec_ctd_s64, vec_ctd_s64, 0, B_VX, O2_U5, BT_FN_V2DF_V2DI_INT) /* vcdgb */
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B_DEF (s390_vec_ctd_u64, vec_ctd_u64, 0, B_VX, O2_U5, BT_FN_V2DF_UV2DI_INT) /* vcdlgb */
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B_DEF (s390_vcdgb, vec_di_to_df_s64, 0, B_VX, O2_U5, BT_FN_V2DF_V2DI_INT)
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B_DEF (s390_vcdlgb, vec_di_to_df_u64, 0, B_VX, O2_U5, BT_FN_V2DF_UV2DI_INT)
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B_DEF (s390_vec_ctsl, vec_ctsl, 0, B_VX, O2_U5, BT_FN_V2DI_V2DF_INT) /* vcgdb */
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B_DEF (s390_vec_ctul, vec_ctul, 0, B_VX, O2_U5, BT_FN_UV2DI_V2DF_INT) /* vclgdb */
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B_DEF (s390_vcgdb, vec_df_to_di_s64, 0, B_VX, O2_U5, BT_FN_V2DI_V2DF_INT)
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B_DEF (s390_vclgdb, vec_df_to_di_u64, 0, B_VX, O2_U5, BT_FN_UV2DI_V2DF_INT)
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B_DEF (s390_vfidb, vfidb, 0, B_VX, O2_U4 | O3_U4, BT_FN_V2DF_V2DF_UCHAR_UCHAR)
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B_DEF (s390_vec_ctd_s64, vec_ctd_s64, 0, B_VX, O2_U3, BT_FN_V2DF_V2DI_INT) /* vcdgb */
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B_DEF (s390_vec_ctd_u64, vec_ctd_u64, 0, B_VX, O2_U3, BT_FN_V2DF_UV2DI_INT) /* vcdlgb */
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B_DEF (s390_vcdgb, vec_di_to_df_s64, 0, B_VX, O2_U3, BT_FN_V2DF_V2DI_INT) /* vcdgb */
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B_DEF (s390_vcdlgb, vec_di_to_df_u64, 0, B_VX, O2_U3, BT_FN_V2DF_UV2DI_INT) /* vcdlgb */
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B_DEF (s390_vec_ctsl, vec_ctsl, 0, B_VX, O2_U3, BT_FN_V2DI_V2DF_INT) /* vcgdb */
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B_DEF (s390_vec_ctul, vec_ctul, 0, B_VX, O2_U3, BT_FN_UV2DI_V2DF_INT) /* vclgdb */
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B_DEF (s390_vcgdb, vec_df_to_di_s64, 0, B_VX, O2_U3, BT_FN_V2DI_V2DF_INT) /* vcgdb */
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B_DEF (s390_vclgdb, vec_df_to_di_u64, 0, B_VX, O2_U3, BT_FN_UV2DI_V2DF_INT) /* vclgdb */
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B_DEF (s390_vfidb, vfidb, 0, B_VX, O2_U4 | O3_U3, BT_FN_V2DF_V2DF_UCHAR_UCHAR)
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B_DEF (s390_vec_ld2f, vec_ld2f, 0, B_VX, 0, BT_FN_V2DF_FLTCONSTPTR) /* vldeb */
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B_DEF (s390_vec_st2f, vec_st2f, 0, B_VX, 0, BT_FN_VOID_V2DF_FLTPTR) /* vledb */
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B_DEF (s390_vfmadb, fmav2df4, 0, B_VX, 0, BT_FN_V2DF_V2DF_V2DF_V2DF)
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@ -364,8 +364,8 @@
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(vec_select:<non_vec>
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(match_operand:V_HW 1 "register_operand" "v")
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(parallel
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[(match_operand:QI 2 "immediate_operand" "C")]))))]
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"TARGET_VX"
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[(match_operand:QI 2 "const_mask_operand" "C")]))))]
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"TARGET_VX && UINTVAL (operands[2]) < GET_MODE_NUNITS (<V_HW:MODE>mode)"
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"vrep<bhfgq>\t%v0,%v1,%2"
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[(set_attr "op_type" "VRI")])
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@ -1073,7 +1073,7 @@
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[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
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(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
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(match_operand:VI_HW_QHS 2 "register_operand" "v")
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(match_operand:QI 3 "immediate_operand" "C")]
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(match_operand:QI 3 "const_mask_operand" "C")]
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UNSPEC_VEC_VFENE))
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(set (reg:CCRAW CC_REGNUM)
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(unspec:CCRAW [(match_dup 1)
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@ -67,20 +67,20 @@
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; Vector gather element
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(define_insn "vec_gather_element<mode>"
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[(set (match_operand:V_HW_32_64 0 "register_operand" "=v")
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(unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0")
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(match_operand:<tointvec> 2 "register_operand" "v")
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(match_operand:BLK 3 "memory_operand" "QR")
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(match_operand:QI 4 "immediate_operand" "C")]
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[(set (match_operand:V_HW_32_64 0 "register_operand" "=v")
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(unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0")
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(match_operand:<tointvec> 2 "register_operand" "v")
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(match_operand:BLK 3 "memory_operand" "QR")
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(match_operand:QI 4 "const_mask_operand" "C")]
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UNSPEC_VEC_GATHER))]
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"TARGET_VX"
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"TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
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"vge<bhfgq>\t%0,%O3(%v2,%R3),%b4"
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[(set_attr "op_type" "VRV")])
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(define_expand "vec_genmask<mode>"
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[(match_operand:VI_HW 0 "register_operand" "=v")
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(match_operand:QI 1 "immediate_operand" "C")
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(match_operand:QI 2 "immediate_operand" "C")]
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(match_operand:QI 1 "const_int_operand" "C")
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(match_operand:QI 2 "const_int_operand" "C")]
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"TARGET_VX"
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{
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int nunits = GET_MODE_NUNITS (<VI_HW:MODE>mode);
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@ -120,8 +120,8 @@
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(define_expand "vec_genbytemaskv16qi"
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[(match_operand:V16QI 0 "register_operand" "")
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(match_operand 1 "immediate_operand" "")]
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"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'K', \"K\")"
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(match_operand:HI 1 "const_int_operand" "")]
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"TARGET_VX"
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{
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int i;
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unsigned mask = 0x8000;
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@ -177,11 +177,11 @@
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[(set_attr "op_type" "VRX")])
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(define_insn "vlbb"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand:BLK 1 "memory_operand" "QR")
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(match_operand:HI 2 "immediate_operand" " K")]
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand:BLK 1 "memory_operand" "QR")
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(match_operand:QI 2 "const_mask_operand" "C")]
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UNSPEC_VEC_LOAD_BNDRY))]
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"TARGET_VX"
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"TARGET_VX && UINTVAL (operands[2]) < 7"
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"vlbb\t%v0,%1,%2"
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[(set_attr "op_type" "VRX")])
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@ -351,10 +351,10 @@
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[(set_attr "op_type" "VRR")])
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(define_expand "vec_permi<mode>"
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[(set (match_operand:V_HW_64 0 "register_operand" "")
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(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "")
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(match_operand:V_HW_64 2 "register_operand" "")
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(match_operand:QI 3 "immediate_operand" "")]
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[(set (match_operand:V_HW_64 0 "register_operand" "")
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(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "")
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(match_operand:V_HW_64 2 "register_operand" "")
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(match_operand:QI 3 "const_mask_operand" "")]
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UNSPEC_VEC_PERMI))]
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"TARGET_VX"
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{
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@ -363,12 +363,12 @@
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})
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(define_insn "*vec_permi<mode>"
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[(set (match_operand:V_HW_64 0 "register_operand" "=v")
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(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "v")
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(match_operand:V_HW_64 2 "register_operand" "v")
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(match_operand:QI 3 "immediate_operand" "C")]
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[(set (match_operand:V_HW_64 0 "register_operand" "=v")
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(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "v")
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(match_operand:V_HW_64 2 "register_operand" "v")
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(match_operand:QI 3 "const_mask_operand" "C")]
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UNSPEC_VEC_PERMI))]
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"TARGET_VX"
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"TARGET_VX && (UINTVAL (operands[3]) & 10) == 0"
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"vpdi\t%v0,%v1,%v2,%b3"
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[(set_attr "op_type" "VRR")])
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@ -382,7 +382,7 @@
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(vec_duplicate:V_HW (vec_select:<non_vec>
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(match_operand:V_HW 1 "register_operand" "")
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(parallel
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[(match_operand:QI 2 "immediate_operand" "")]))))]
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[(match_operand:QI 2 "const_mask_operand" "")]))))]
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"TARGET_VX")
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; Vector scatter element
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@ -393,13 +393,13 @@
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(define_insn "vec_scatter_elementv4si_DI"
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[(set (mem:SI
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(plus:DI (zero_extend:DI
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(unspec:SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:DI 3 "immediate_operand" "I")]
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(unspec:SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:QI 3 "const_mask_operand" "C")]
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UNSPEC_VEC_EXTRACT))
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(match_operand:SI 2 "address_operand" "ZQ")))
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(unspec:SI [(match_operand:V4SI 0 "register_operand" "v")
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(match_operand:SI 2 "address_operand" "ZQ")))
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(unspec:SI [(match_operand:V4SI 0 "register_operand" "v")
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(match_dup 3)] UNSPEC_VEC_EXTRACT))]
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"TARGET_VX && TARGET_64BIT"
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"TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4"
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"vscef\t%v0,%O2(%v1,%R2),%3"
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[(set_attr "op_type" "VRV")])
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(define_insn "vec_scatter_element<V_HW_64:mode>_SI"
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[(set (mem:<non_vec>
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(plus:SI (subreg:SI
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(unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand" "v")
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(match_operand:DI 3 "immediate_operand" "I")]
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(unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand" "v")
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(match_operand:QI 3 "const_mask_operand" "C")]
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UNSPEC_VEC_EXTRACT) 4)
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(match_operand:SI 2 "address_operand" "ZQ")))
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(unspec:<non_vec> [(match_operand:V_HW_64 0 "register_operand" "v")
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(match_operand:SI 2 "address_operand" "ZQ")))
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(unspec:<non_vec> [(match_operand:V_HW_64 0 "register_operand" "v")
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(match_dup 3)] UNSPEC_VEC_EXTRACT))]
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"TARGET_VX && !TARGET_64BIT"
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"TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_64:MODE>mode)"
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"vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3"
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[(set_attr "op_type" "VRV")])
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(define_insn "vec_scatter_element<mode>_<non_vec_int>"
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[(set (mem:<non_vec>
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(plus:<non_vec_int> (unspec:<non_vec_int>
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[(match_operand:<tointvec> 1 "register_operand" "v")
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(match_operand:DI 3 "immediate_operand" "I")]
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[(match_operand:<tointvec> 1 "register_operand" "v")
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(match_operand:QI 3 "const_mask_operand" "C")]
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UNSPEC_VEC_EXTRACT)
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(match_operand:DI 2 "address_operand" "ZQ")))
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(unspec:<non_vec> [(match_operand:V_HW_32_64 0 "register_operand" "v")
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(match_operand:DI 2 "address_operand" "ZQ")))
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(unspec:<non_vec> [(match_operand:V_HW_32_64 0 "register_operand" "v")
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(match_dup 3)] UNSPEC_VEC_EXTRACT))]
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"TARGET_VX"
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"TARGET_VX && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
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"vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3"
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[(set_attr "op_type" "VRV")])
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@ -438,7 +438,7 @@
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[(match_operand:V_HW_32_64 0 "register_operand" "")
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(match_operand:<tointvec> 1 "register_operand" "")
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(match_operand 2 "address_operand" "")
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(match_operand:DI 3 "immediate_operand" "")]
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(match_operand:QI 3 "const_mask_operand" "")]
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"TARGET_VX"
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{
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if (TARGET_64BIT)
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@ -1042,7 +1042,7 @@
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(unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "0")
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(match_operand:VI_HW 2 "register_operand" "v")
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(match_operand:VI_HW 3 "register_operand" "v")
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(match_operand:SI 4 "immediate_operand" "I")]
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(match_operand:QI 4 "const_int_operand" "C")]
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UNSPEC_VEC_RL_MASK))]
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"TARGET_VX"
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"verim<bhfgq>\t%v0,%v2,%v3,%b4"
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@ -1079,7 +1079,7 @@
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[(set (match_operand:V_HW 0 "register_operand" "=v")
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(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
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(match_operand:V_HW 2 "register_operand" "v")
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(match_operand:DI 3 "immediate_operand" "C")]
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(match_operand:QI 3 "const_int_operand" "C")]
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UNSPEC_VEC_SLDB))]
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"TARGET_VX"
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"vsldb\t%v0,%v1,%v2,%b3"
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@ -1089,7 +1089,7 @@
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[(set (match_operand:V_HW 0 "register_operand" "")
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(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
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(match_operand:V_HW 2 "register_operand" "")
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(match_operand:DI 3 "immediate_operand" "")]
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(match_operand:QI 3 "const_int_operand" "")]
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UNSPEC_VEC_SLDB))]
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"TARGET_VX"
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{
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@ -1262,7 +1262,7 @@
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[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
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(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
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(match_operand:VI_HW_QHS 2 "register_operand" "v")
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(match_operand:SI 3 "immediate_operand" "C")]
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(match_operand:QI 3 "const_mask_operand" "C")]
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UNSPEC_VEC_VFAE))]
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"TARGET_VX"
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{
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@ -1282,9 +1282,9 @@
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; vfaezbs, vfaezhs, vfaezfs
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(define_insn "*vfaes<mode>"
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[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
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(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
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(match_operand:VI_HW_QHS 2 "register_operand" "v")
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(match_operand:SI 3 "immediate_operand" "C")]
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(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
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(match_operand:VI_HW_QHS 2 "register_operand" "v")
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(match_operand:QI 3 "const_mask_operand" "C")]
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UNSPEC_VEC_VFAE))
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(set (reg:CCRAW CC_REGNUM)
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(unspec:CCRAW [(match_dup 1)
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@ -1307,9 +1307,9 @@
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(define_expand "vfaez<mode>"
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[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
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(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "v")
|
||||
(match_operand:SI 3 "immediate_operand" "C")]
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:QI 3 "const_mask_operand" "")]
|
||||
UNSPEC_VEC_VFAE))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
|
@ -1319,9 +1319,9 @@
|
|||
(define_expand "vfaes<mode>"
|
||||
[(parallel
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:SI 3 "immediate_operand" "C")]
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:QI 3 "const_mask_operand" "")]
|
||||
UNSPEC_VEC_VFAE))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1)
|
||||
|
@ -1338,9 +1338,9 @@
|
|||
(define_expand "vfaezs<mode>"
|
||||
[(parallel
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:SI 3 "immediate_operand" "C")]
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:SI 3 "const_mask_operand" "")]
|
||||
UNSPEC_VEC_VFAE))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1)
|
||||
|
@ -1363,7 +1363,7 @@
|
|||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "v")
|
||||
(match_operand:QI 3 "immediate_operand" "C")]
|
||||
(match_operand:QI 3 "const_mask_operand" "C")]
|
||||
UNSPEC_VEC_VFEE))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1)
|
||||
|
@ -1541,11 +1541,11 @@
|
|||
; vstrcb, vstrch, vstrcf
|
||||
; vstrczb, vstrczh, vstrczf
|
||||
(define_insn "vstrc<mode>"
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "v")
|
||||
(match_operand:SI 4 "immediate_operand" "C")]
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "v")
|
||||
(match_operand:QI 4 "const_mask_operand" "C")]
|
||||
UNSPEC_VEC_VSTRC))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
|
@ -1564,11 +1564,11 @@
|
|||
; vstrcbs, vstrchs, vstrcfs
|
||||
; vstrczbs, vstrczhs, vstrczfs
|
||||
(define_insn "*vstrcs<mode>"
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "v")
|
||||
(match_operand:SI 4 "immediate_operand" "C")]
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "v")
|
||||
(match_operand:QI 4 "const_mask_operand" "C")]
|
||||
UNSPEC_VEC_VSTRC))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1)
|
||||
|
@ -1591,11 +1591,11 @@
|
|||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
(define_expand "vstrcz<mode>"
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "v")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "v")
|
||||
(match_operand:SI 4 "immediate_operand" "C")]
|
||||
[(set (match_operand:VI_HW_QHS 0 "register_operand" "")
|
||||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "")
|
||||
(match_operand:QI 4 "const_mask_operand" "")]
|
||||
UNSPEC_VEC_VSTRC))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
|
@ -1608,7 +1608,7 @@
|
|||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "")
|
||||
(match_operand:SI 4 "immediate_operand" "C")]
|
||||
(match_operand:QI 4 "const_mask_operand" "")]
|
||||
UNSPEC_VEC_VSTRC))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1)
|
||||
|
@ -1629,7 +1629,7 @@
|
|||
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 2 "register_operand" "")
|
||||
(match_operand:VI_HW_QHS 3 "register_operand" "")
|
||||
(match_operand:SI 4 "immediate_operand" "C")]
|
||||
(match_operand:QI 4 "const_mask_operand" "")]
|
||||
UNSPEC_VEC_VSTRC))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1)
|
||||
|
@ -1647,11 +1647,11 @@
|
|||
|
||||
; Signed V2DI -> V2DF conversion - inexact exception disabled
|
||||
(define_insn "vec_di_to_df_s64"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=v")
|
||||
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
|
||||
(match_operand:QI 2 "immediate_operand" "C")]
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=v")
|
||||
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
|
||||
(match_operand:QI 2 "const_mask_operand" "C")]
|
||||
UNSPEC_VEC_VCDGB))]
|
||||
"TARGET_VX"
|
||||
"TARGET_VX && UINTVAL (operands[2]) != 2 && UINTVAL (operands[2]) <= 7"
|
||||
"vcdgb\t%v0,%v1,4,%b2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
|
@ -1661,7 +1661,7 @@
|
|||
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
|
||||
(const_int 0)] ; According to current BFP rounding mode
|
||||
UNSPEC_VEC_VCDGB))
|
||||
(use (match_operand:QI 2 "immediate_operand" ""))
|
||||
(use (match_operand:QI 2 "const_int_operand" ""))
|
||||
(set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
|
@ -1679,7 +1679,7 @@
|
|||
(define_insn "vec_di_to_df_u64"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=v")
|
||||
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "v")
|
||||
(match_operand:QI 2 "immediate_operand" "C")]
|
||||
(match_operand:QI 2 "const_int_operand" "C")]
|
||||
UNSPEC_VEC_VCDLGB))]
|
||||
"TARGET_VX"
|
||||
"vcdlgb\t%v0,%v1,4,%b2"
|
||||
|
@ -1691,7 +1691,7 @@
|
|||
(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
|
||||
(const_int 0)] ; According to current BFP rounding mode
|
||||
UNSPEC_VEC_VCDLGB))
|
||||
(use (match_operand:QI 2 "immediate_operand" ""))
|
||||
(use (match_operand:QI 2 "const_int_operand" ""))
|
||||
(set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
|
@ -1710,7 +1710,7 @@
|
|||
(define_insn "vec_df_to_di_s64"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=v")
|
||||
(unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
|
||||
(match_operand:QI 2 "immediate_operand" "C")]
|
||||
(match_operand:QI 2 "const_int_operand" "C")]
|
||||
UNSPEC_VEC_VCGDB))]
|
||||
"TARGET_VX"
|
||||
"vcgdb\t%v0,%v1,4,%b2"
|
||||
|
@ -1718,7 +1718,7 @@
|
|||
|
||||
; The input needs to be multiplied with 2**op2
|
||||
(define_expand "vec_ctsl"
|
||||
[(use (match_operand:QI 2 "immediate_operand" ""))
|
||||
[(use (match_operand:QI 2 "const_int_operand" ""))
|
||||
(set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
|
||||
(match_dup 3)))
|
||||
(set (match_operand:V2DI 0 "register_operand" "")
|
||||
|
@ -1741,15 +1741,15 @@
|
|||
(define_insn "vec_df_to_di_u64"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=v")
|
||||
(unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
|
||||
(match_operand:QI 2 "immediate_operand" "C")]
|
||||
(match_operand:QI 2 "const_mask_operand" "C")]
|
||||
UNSPEC_VEC_VCLGDB))]
|
||||
"TARGET_VX"
|
||||
"TARGET_VX && UINTVAL (operands[2]) <= 7"
|
||||
"vclgdb\t%v0,%v1,4,%b2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
; The input needs to be multiplied with 2**op2
|
||||
(define_expand "vec_ctul"
|
||||
[(use (match_operand:QI 2 "immediate_operand" ""))
|
||||
[(use (match_operand:QI 2 "const_int_operand" ""))
|
||||
(set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
|
||||
(match_dup 3)))
|
||||
(set (match_operand:V2DI 0 "register_operand" "")
|
||||
|
@ -1770,12 +1770,12 @@
|
|||
|
||||
; Vector load fp integer - IEEE inexact exception is suppressed
|
||||
(define_insn "vfidb"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=v")
|
||||
(unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
|
||||
(match_operand:QI 2 "immediate_operand" "C")
|
||||
(match_operand:QI 3 "immediate_operand" "C")]
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=v")
|
||||
(unspec:V2DI [(match_operand:V2DF 1 "register_operand" "v")
|
||||
(match_operand:QI 2 "const_mask_operand" "C")
|
||||
(match_operand:QI 3 "const_mask_operand" "C")]
|
||||
UNSPEC_VEC_VFIDB))]
|
||||
"TARGET_VX"
|
||||
"TARGET_VX && !(UINTVAL (operands[2]) & 3) && UINTVAL (operands[3]) <= 7"
|
||||
"vfidb\t%v0,%v1,%b2,%b3"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
|
@ -1887,21 +1887,21 @@
|
|||
(define_insn "*vftcidb"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=v")
|
||||
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v")
|
||||
(match_operand:SI 2 "immediate_operand" "J")]
|
||||
(match_operand:HI 2 "const_int_operand" "J")]
|
||||
UNSPEC_VEC_VFTCIDB))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))]
|
||||
"TARGET_VX"
|
||||
"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
|
||||
"vftcidb\t%v0,%v1,%x2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
(define_insn "*vftcidb_cconly"
|
||||
[(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_operand:V2DF 1 "register_operand" "v")
|
||||
(match_operand:SI 2 "immediate_operand" "J")]
|
||||
(match_operand:HI 2 "const_int_operand" "J")]
|
||||
UNSPEC_VEC_VFTCIDBCC))
|
||||
(clobber (match_scratch:V2DI 0 "=v"))]
|
||||
"TARGET_VX"
|
||||
"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
|
||||
"vftcidb\t%v0,%v1,%x2"
|
||||
[(set_attr "op_type" "VRR")])
|
||||
|
||||
|
@ -1909,13 +1909,13 @@
|
|||
[(parallel
|
||||
[(set (match_operand:V2DF 0 "register_operand" "")
|
||||
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "")
|
||||
(match_operand:SI 2 "immediate_operand" "")]
|
||||
(match_operand:HI 2 "const_int_operand" "")]
|
||||
UNSPEC_VEC_VFTCIDB))
|
||||
(set (reg:CCRAW CC_REGNUM)
|
||||
(unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))])
|
||||
(set (match_operand:SI 3 "memory_operand" "")
|
||||
(unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
|
||||
"TARGET_VX")
|
||||
"TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")")
|
||||
|
||||
;;
|
||||
;; Integer compares
|
||||
|
|
Loading…
Reference in New Issue