From ea1e916837085fa51565e55a57c8c2f9dfaab9ce Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Wed, 23 Apr 2014 15:29:06 +0000 Subject: [PATCH] [ARM][3/3] Recognise bitwise operations leading to SImode rev16 * config/arm/arm.md (arm_rev16si2): New pattern. (arm_rev16si2_alt): Likewise. * config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case. * gcc.target/arm/rev16.c: New test. From-SVN: r209705 --- gcc/ChangeLog | 6 +++++ gcc/config/arm/arm.c | 11 +++++++- gcc/config/arm/arm.md | 38 ++++++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 4 +++ gcc/testsuite/gcc.target/arm/rev16.c | 35 +++++++++++++++++++++++++ 5 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/rev16.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1b8dd62b670..e499b256f61 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-04-23 Kyrylo Tkachov + + * config/arm/arm.md (arm_rev16si2): New pattern. + (arm_rev16si2_alt): Likewise. + * config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case. + 2014-04-23 Kyrylo Tkachov * config/aarch64/aarch64.md (rev162): New pattern. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b14537437b6..849176346c7 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -9899,8 +9899,17 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, /* Vector mode? */ *cost = LIBCALL_COST (2); return false; + case IOR: + if (mode == SImode && arm_arch6 && aarch_rev16_p (x)) + { + *cost = COSTS_N_INSNS (1); + if (speed_p) + *cost += extra_cost->alu.rev; - case AND: case XOR: case IOR: + return true; + } + /* Fall through. */ + case AND: case XOR: if (mode == SImode) { enum rtx_code subcode = GET_CODE (XEXP (x, 0)); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9aa0d352bbd..8a949b929fa 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12690,6 +12690,44 @@ (set_attr "type" "rev")] ) +;; There are no canonicalisation rules for the position of the lshiftrt, ashift +;; operations within an IOR/AND RTX, therefore we have two patterns matching +;; each valid permutation. + +(define_insn "arm_rev16si2" + [(set (match_operand:SI 0 "register_operand" "=l,l,r") + (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "l,l,r") + (const_int 8)) + (match_operand:SI 3 "const_int_operand" "n,n,n")) + (and:SI (lshiftrt:SI (match_dup 1) + (const_int 8)) + (match_operand:SI 2 "const_int_operand" "n,n,n"))))] + "arm_arch6 + && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) + && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" + "rev16\\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "type" "rev")] +) + +(define_insn "arm_rev16si2_alt" + [(set (match_operand:SI 0 "register_operand" "=l,l,r") + (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,l,r") + (const_int 8)) + (match_operand:SI 2 "const_int_operand" "n,n,n")) + (and:SI (ashift:SI (match_dup 1) + (const_int 8)) + (match_operand:SI 3 "const_int_operand" "n,n,n"))))] + "arm_arch6 + && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) + && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" + "rev16\\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "type" "rev")] +) + (define_expand "bswaphi2" [(set (match_operand:HI 0 "s_register_operand" "=r") (bswap:HI (match_operand:HI 1 "s_register_operand" "r")))] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9f1e7ce966c..f25a2b7f520 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2014-04-23 Kyrylo Tkachov + + * gcc.target/arm/rev16.c: New test. + 2014-04-23 Kyrylo Tkachov * gcc.target/aarch64/rev16_1.c: New test. diff --git a/gcc/testsuite/gcc.target/arm/rev16.c b/gcc/testsuite/gcc.target/arm/rev16.c new file mode 100644 index 00000000000..1c869b3067a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/rev16.c @@ -0,0 +1,35 @@ +/* { dg-options "-O2" } */ +/* { dg-do run } */ + +extern void abort (void); + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +int +main (void) +{ + volatile __u32 in32 = 0x12345678; + volatile __u32 expected32 = 0x34127856; + + if (__rev16_32 (in32) != expected32) + abort (); + + if (__rev16_32_alt (in32) != expected32) + abort (); + + return 0; +}