avr.c (avr_default_expand_builtin): New function.
* config/avr/avr.c (avr_default_expand_builtin): New function. (avr_expand_builtin): Use it. (avr_expand_unop_builtin): Remove. (avr_expand_binop_builtin): Remove. (avr_expand_triop_builtin): Remove. From-SVN: r188670
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
f8395d62c1
commit
eb6bb55998
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@ -1,3 +1,11 @@
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2012-06-15 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.c (avr_default_expand_builtin): New function.
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(avr_expand_builtin): Use it.
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(avr_expand_unop_builtin): Remove.
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(avr_expand_binop_builtin): Remove.
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(avr_expand_triop_builtin): Remove.
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2012-06-15 Michael Matz <matz@suse.de>
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PR middle-end/38474
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@ -10329,8 +10329,8 @@ avr_init_builtin_int24 (void)
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tree int24_type = make_signed_type (GET_MODE_BITSIZE (PSImode));
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tree uint24_type = make_unsigned_type (GET_MODE_BITSIZE (PSImode));
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(*lang_hooks.types.register_builtin_type) (int24_type, "__int24");
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(*lang_hooks.types.register_builtin_type) (uint24_type, "__uint24");
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lang_hooks.types.register_builtin_type (int24_type, "__int24");
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lang_hooks.types.register_builtin_type (uint24_type, "__uint24");
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}
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@ -10397,170 +10397,64 @@ avr_init_builtins (void)
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}
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/* Subroutine of avr_expand_builtin to take care of unop insns. */
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/* Subroutine of avr_expand_builtin to expand vanilla builtins
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with non-void result and 1 ... 3 arguments. */
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static rtx
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avr_expand_unop_builtin (enum insn_code icode, tree exp,
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rtx target)
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avr_default_expand_builtin (enum insn_code icode, tree exp, rtx target)
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{
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rtx pat;
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tree arg0 = CALL_EXPR_ARG (exp, 0);
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rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
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enum machine_mode op0mode = GET_MODE (op0);
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rtx pat, xop[3];
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int n, n_args = call_expr_nargs (exp);
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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if (! target
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gcc_assert (n_args >= 1 && n_args <= 3);
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if (target == NULL_RTX
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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|| !insn_data[icode].operand[0].predicate (target, tmode))
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{
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target = gen_reg_rtx (tmode);
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}
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if (op0mode == SImode && mode0 == HImode)
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for (n = 0; n < n_args; n++)
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{
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op0mode = HImode;
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op0 = gen_lowpart (HImode, op0);
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}
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tree arg = CALL_EXPR_ARG (exp, n);
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rtx op = expand_expr (arg, NULL_RTX, VOIDmode, EXPAND_NORMAL);
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enum machine_mode opmode = GET_MODE (op);
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enum machine_mode mode = insn_data[icode].operand[n+1].mode;
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if ((opmode == SImode || opmode == VOIDmode) && mode == HImode)
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{
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opmode = HImode;
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op = gen_lowpart (HImode, op);
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}
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/* In case the insn wants input operands in modes different from
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the result, abort. */
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gcc_assert (op0mode == mode0 || op0mode == VOIDmode);
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gcc_assert (opmode == mode || opmode == VOIDmode);
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (!insn_data[icode].operand[n+1].predicate (op, mode))
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op = copy_to_mode_reg (mode, op);
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pat = GEN_FCN (icode) (target, op0);
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if (! pat)
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return 0;
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emit_insn (pat);
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return target;
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}
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/* Subroutine of avr_expand_builtin to take care of binop insns. */
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static rtx
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avr_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
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{
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rtx pat;
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tree arg0 = CALL_EXPR_ARG (exp, 0);
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tree arg1 = CALL_EXPR_ARG (exp, 1);
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rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
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rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
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enum machine_mode op0mode = GET_MODE (op0);
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enum machine_mode op1mode = GET_MODE (op1);
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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enum machine_mode mode1 = insn_data[icode].operand[2].mode;
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if (! target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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{
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target = gen_reg_rtx (tmode);
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xop[n] = op;
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}
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if ((op0mode == SImode || op0mode == VOIDmode) && mode0 == HImode)
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switch (n_args)
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{
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op0mode = HImode;
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op0 = gen_lowpart (HImode, op0);
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case 1: pat = GEN_FCN (icode) (target, xop[0]); break;
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case 2: pat = GEN_FCN (icode) (target, xop[0], xop[1]); break;
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case 3: pat = GEN_FCN (icode) (target, xop[0], xop[1], xop[2]); break;
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default:
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gcc_unreachable();
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}
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if ((op1mode == SImode || op1mode == VOIDmode) && mode1 == HImode)
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{
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op1mode = HImode;
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op1 = gen_lowpart (HImode, op1);
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}
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/* In case the insn wants input operands in modes different from
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the result, abort. */
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gcc_assert ((op0mode == mode0 || op0mode == VOIDmode)
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&& (op1mode == mode1 || op1mode == VOIDmode));
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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pat = GEN_FCN (icode) (target, op0, op1);
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if (! pat)
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return 0;
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if (pat == NULL_RTX)
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return NULL_RTX;
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emit_insn (pat);
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return target;
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}
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/* Subroutine of avr_expand_builtin to take care of 3-operand insns. */
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static rtx
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avr_expand_triop_builtin (enum insn_code icode, tree exp, rtx target)
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{
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rtx pat;
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tree arg0 = CALL_EXPR_ARG (exp, 0);
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tree arg1 = CALL_EXPR_ARG (exp, 1);
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tree arg2 = CALL_EXPR_ARG (exp, 2);
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rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
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rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
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rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
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enum machine_mode op0mode = GET_MODE (op0);
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enum machine_mode op1mode = GET_MODE (op1);
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enum machine_mode op2mode = GET_MODE (op2);
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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enum machine_mode mode1 = insn_data[icode].operand[2].mode;
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enum machine_mode mode2 = insn_data[icode].operand[3].mode;
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if (! target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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{
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target = gen_reg_rtx (tmode);
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}
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if ((op0mode == SImode || op0mode == VOIDmode) && mode0 == HImode)
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{
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op0mode = HImode;
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op0 = gen_lowpart (HImode, op0);
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}
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if ((op1mode == SImode || op1mode == VOIDmode) && mode1 == HImode)
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{
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op1mode = HImode;
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op1 = gen_lowpart (HImode, op1);
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}
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if ((op2mode == SImode || op2mode == VOIDmode) && mode2 == HImode)
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{
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op2mode = HImode;
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op2 = gen_lowpart (HImode, op2);
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}
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/* In case the insn wants input operands in modes different from
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the result, abort. */
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gcc_assert ((op0mode == mode0 || op0mode == VOIDmode)
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&& (op1mode == mode1 || op1mode == VOIDmode)
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&& (op2mode == mode2 || op2mode == VOIDmode));
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
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op2 = copy_to_mode_reg (mode2, op2);
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pat = GEN_FCN (icode) (target, op0, op1, op2);
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if (! pat)
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return 0;
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emit_insn (pat);
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return target;
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}
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@ -10579,7 +10473,7 @@ avr_expand_builtin (tree exp, rtx target,
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int ignore ATTRIBUTE_UNUSED)
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{
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tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
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const char* bname = IDENTIFIER_POINTER (DECL_NAME (fndecl));
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const char *bname = IDENTIFIER_POINTER (DECL_NAME (fndecl));
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unsigned int id = DECL_FUNCTION_CODE (fndecl);
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const struct avr_builtin_description *d = &avr_bdesc[id];
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tree arg0;
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@ -10603,7 +10497,7 @@ avr_expand_builtin (tree exp, rtx target,
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else
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avr_expand_delay_cycles (op0);
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return 0;
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return NULL_RTX;
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}
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case AVR_BUILTIN_INSERT_BITS:
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@ -10621,24 +10515,16 @@ avr_expand_builtin (tree exp, rtx target,
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}
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/* No special treatment needed: vanilla expand. */
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switch (d->n_args)
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gcc_assert (d->n_args == call_expr_nargs (exp));
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if (d->n_args == 0)
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{
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case 0:
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emit_insn ((GEN_FCN (d->icode)) (target));
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return 0;
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case 1:
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return avr_expand_unop_builtin (d->icode, exp, target);
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case 2:
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return avr_expand_binop_builtin (d->icode, exp, target);
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case 3:
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return avr_expand_triop_builtin (d->icode, exp, target);
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return NULL_RTX;
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}
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gcc_unreachable ();
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return avr_default_expand_builtin (d->icode, exp, target);
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}
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