i386.h (TARGET_KEEPS_VECTOR_ALIGNED_STACK): New.
* gcc/config/i386/i386.h (TARGET_KEEPS_VECTOR_ALIGNED_STACK): New. * gcc/config/i386/darwin.h: (TARGET_KEEPS_VECTOR_ALIGNED_STACK): New. * gcc/config/i386/i386.md (fixuns_trunc<mode>si2, fixuns_truncsfhi2, fixuns_truncdfhi2): New. (fix_truncsfdi_sse): Call ix86_expand_convert_sign_didf_sse. (floatunsdidf2): Call ix86_expand_convert_uns_didf_sse. (floatunssisf2): Add call to ix86_expand_convert_uns_sisf_sse. (floatunssidf2): Allow nonimmediate source. * gcc/config/i386/sse.md (movdi_to_sse): New. (vec_concatv2di): Drop '*'. * gcc/config/i386/i386-protos.h (ix86_expand_convert_uns_si_sse, ix86_expand_convert_uns_didf_sse, ix86_expand_convert_uns_sidf_sse, ix86_expand_convert_uns_sisf_sse, ix86_expand_convert_sign_didf_sse): New. * gcc/config/i386/i386.c (ix86_expand_convert_uns_si_sse, ix86_expand_convert_uns_didf_sse, ix86_expand_convert_uns_sidf_sse, ix86_expand_convert_uns_sisf_sse, ix86_expand_convert_sign_didf_sse, ix86_build_const_vector, ix86_expand_vector_init_one_nonzero): New. (ix86_build_signbit_mask): Fix decl of v, refactor to call ix86_build_const_vector. (x86_emit_floatuns): Rewrite. Co-Authored-By: Richard Henderson <rth@redhat.com> From-SVN: r121790
This commit is contained in:
Stuart Hastings
Stuart Hastings
parent
692b647c4f
commit
ebff937c19
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@ -1,3 +1,25 @@
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2007-02-09 Stuart Hastings <stuart@apple.com>
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Richard Henderson <rth@redhat.com>
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* gcc/config/i386/i386.h (TARGET_KEEPS_VECTOR_ALIGNED_STACK): New.
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* gcc/config/i386/darwin.h: (TARGET_KEEPS_VECTOR_ALIGNED_STACK): New.
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* gcc/config/i386/i386.md (fixuns_trunc<mode>si2, fixuns_truncsfhi2,
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fixuns_truncdfhi2): New.
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(fix_truncsfdi_sse): Call ix86_expand_convert_sign_didf_sse.
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(floatunsdidf2): Call ix86_expand_convert_uns_didf_sse.
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(floatunssisf2): Add call to ix86_expand_convert_uns_sisf_sse.
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(floatunssidf2): Allow nonimmediate source.
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* gcc/config/i386/sse.md (movdi_to_sse): New. (vec_concatv2di): Drop '*'.
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* gcc/config/i386/i386-protos.h (ix86_expand_convert_uns_si_sse,
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ix86_expand_convert_uns_didf_sse, ix86_expand_convert_uns_sidf_sse,
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ix86_expand_convert_uns_sisf_sse, ix86_expand_convert_sign_didf_sse): New.
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* gcc/config/i386/i386.c (ix86_expand_convert_uns_si_sse,
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ix86_expand_convert_uns_didf_sse, ix86_expand_convert_uns_sidf_sse,
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ix86_expand_convert_uns_sisf_sse, ix86_expand_convert_sign_didf_sse,
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ix86_build_const_vector, ix86_expand_vector_init_one_nonzero): New.
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(ix86_build_signbit_mask): Fix decl of v, refactor to call ix86_build_const_vector.
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(x86_emit_floatuns): Rewrite.
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2007-02-10 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
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* genautomata.c (longest_path_length): Delete unused function.
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@ -66,6 +66,9 @@ Boston, MA 02110-1301, USA. */
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#undef FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
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#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN (0)
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#undef TARGET_KEEPS_VECTOR_ALIGNED_STACK
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#define TARGET_KEEPS_VECTOR_ALIGNED_STACK 1
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/* We want -fPIC by default, unless we're using -static to compile for
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the kernel or some such. */
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@ -89,6 +89,11 @@ extern void ix86_expand_binary_operator (enum rtx_code,
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extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]);
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extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode,
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rtx[]);
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extern void ix86_expand_convert_uns_si_sse (rtx, rtx);
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extern void ix86_expand_convert_uns_didf_sse (rtx, rtx);
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extern void ix86_expand_convert_uns_sidf_sse (rtx, rtx);
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extern void ix86_expand_convert_uns_sisf_sse (rtx, rtx);
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extern void ix86_expand_convert_sign_didf_sse (rtx, rtx);
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extern rtx ix86_build_signbit_mask (enum machine_mode, bool, bool);
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extern void ix86_expand_fp_absneg_operator (enum rtx_code, enum machine_mode,
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rtx[]);
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@ -1518,6 +1518,9 @@ static const char *ix86_mangle_fundamental_type (tree);
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static tree ix86_stack_protect_fail (void);
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static rtx ix86_internal_arg_pointer (void);
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static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int);
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static rtx ix86_build_const_vector (enum machine_mode, bool, rtx);
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static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
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rtx, rtx, int);
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/* This function is only used on Solaris. */
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static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
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@ -9858,6 +9861,233 @@ ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
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return TRUE;
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}
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/* Convert an SF or DFmode value in an SSE register into an unsigned SImode.
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When -fpmath=387, this is done with an x87 st(0)_FP->signed-int-64
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conversion, and ignoring the upper 32 bits of the result. On x86_64,
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there is an equivalent SSE %xmm->signed-int-64 conversion.
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On x86_32, we don't have the instruction, nor the 64-bit destination
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register it requires. Do the conversion inline in the SSE registers.
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Requires SSE2. For x86_32, -mfpmath=sse, !optimize_size only. */
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void
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ix86_expand_convert_uns_si_sse (rtx target, rtx input)
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{
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REAL_VALUE_TYPE TWO31r;
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enum machine_mode mode, vecmode;
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rtx two31, value, large, sign, result_vec, zero_or_two31, x;
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mode = GET_MODE (input);
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vecmode = mode == SFmode ? V4SFmode : V2DFmode;
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real_ldexp (&TWO31r, &dconst1, 31);
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two31 = const_double_from_real_value (TWO31r, mode);
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two31 = ix86_build_const_vector (mode, true, two31);
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two31 = force_reg (vecmode, two31);
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value = gen_reg_rtx (vecmode);
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ix86_expand_vector_init_one_nonzero (false, vecmode, value, input, 0);
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large = gen_reg_rtx (vecmode);
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x = gen_rtx_fmt_ee (LE, vecmode, two31, value);
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emit_insn (gen_rtx_SET (VOIDmode, large, x));
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zero_or_two31 = gen_reg_rtx (vecmode);
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x = gen_rtx_AND (vecmode, large, two31);
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emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
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x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
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emit_insn (gen_rtx_SET (VOIDmode, value, x));
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result_vec = gen_reg_rtx (V4SImode);
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if (mode == SFmode)
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x = gen_sse2_cvttps2dq (result_vec, value);
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else
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x = gen_sse2_cvttpd2dq (result_vec, value);
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emit_insn (x);
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sign = gen_reg_rtx (V4SImode);
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emit_insn (gen_ashlv4si3 (sign, gen_lowpart (V4SImode, large),
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GEN_INT (31)));
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emit_insn (gen_xorv4si3 (result_vec, result_vec, sign));
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ix86_expand_vector_extract (false, target, result_vec, 0);
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}
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/* Convert an unsigned DImode value into a DFmode, using only SSE.
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Expects the 64-bit DImode to be supplied in a pair of integral
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registers. Requires SSE2; will use SSE3 if available. For x86_32,
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-mfpmath=sse, !optimize_size only. */
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void
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ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
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{
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REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
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rtx int_xmm, fp_xmm;
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rtx biases, exponents;
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rtx x;
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int_xmm = gen_reg_rtx (V4SImode);
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if (TARGET_INTER_UNIT_MOVES)
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emit_insn (gen_movdi_to_sse (int_xmm, input));
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else if (TARGET_SSE_SPLIT_REGS)
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{
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emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
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emit_move_insn (gen_lowpart (DImode, int_xmm), input);
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}
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else
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{
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x = gen_reg_rtx (V2DImode);
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ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
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emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
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}
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x = gen_rtx_CONST_VECTOR (V4SImode,
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gen_rtvec (4, GEN_INT (0x43300000UL),
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GEN_INT (0x45300000UL),
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const0_rtx, const0_rtx));
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exponents = validize_mem (force_const_mem (V4SImode, x));
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/* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
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emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
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/* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
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yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
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Similarly (0x45300000UL ## fp_value_hi_xmm) yields
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(0x1.0p84 + double(fp_value_hi_xmm)).
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Note these exponents differ by 32. */
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fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
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/* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
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in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
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real_ldexp (&bias_lo_rvt, &dconst1, 52);
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real_ldexp (&bias_hi_rvt, &dconst1, 84);
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biases = const_double_from_real_value (bias_lo_rvt, DFmode);
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x = const_double_from_real_value (bias_hi_rvt, DFmode);
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biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
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biases = validize_mem (force_const_mem (V2DFmode, biases));
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emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
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/* Add the upper and lower DFmode values together. */
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if (TARGET_SSE3)
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emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
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else
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{
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x = copy_to_mode_reg (V2DFmode, fp_xmm);
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emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
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emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
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}
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ix86_expand_vector_extract (false, target, fp_xmm, 0);
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}
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/* Convert an unsigned SImode value into a DFmode. Only currently used
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for SSE, but applicable anywhere. */
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void
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ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
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{
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REAL_VALUE_TYPE TWO31r;
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rtx x, fp;
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x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
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NULL, 1, OPTAB_DIRECT);
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fp = gen_reg_rtx (DFmode);
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emit_insn (gen_floatsidf2 (fp, x));
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real_ldexp (&TWO31r, &dconst1, 31);
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x = const_double_from_real_value (TWO31r, DFmode);
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x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
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if (x != target)
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emit_move_insn (target, x);
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}
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/* Convert a signed DImode value into a DFmode. Only used for SSE in
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32-bit mode; otherwise we have a direct convert instruction. */
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void
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ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
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{
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REAL_VALUE_TYPE TWO32r;
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rtx fp_lo, fp_hi, x;
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fp_lo = gen_reg_rtx (DFmode);
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fp_hi = gen_reg_rtx (DFmode);
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emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
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real_ldexp (&TWO32r, &dconst1, 32);
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x = const_double_from_real_value (TWO32r, DFmode);
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fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
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ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
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x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
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0, OPTAB_DIRECT);
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if (x != target)
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emit_move_insn (target, x);
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}
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/* Convert an unsigned SImode value into a SFmode, using only SSE.
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For x86_32, -mfpmath=sse, !optimize_size only. */
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void
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ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
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{
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REAL_VALUE_TYPE ONE16r;
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rtx fp_hi, fp_lo, int_hi, int_lo, x;
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real_ldexp (&ONE16r, &dconst1, 16);
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x = const_double_from_real_value (ONE16r, SFmode);
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int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
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NULL, 0, OPTAB_DIRECT);
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int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
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NULL, 0, OPTAB_DIRECT);
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fp_hi = gen_reg_rtx (SFmode);
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fp_lo = gen_reg_rtx (SFmode);
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emit_insn (gen_floatsisf2 (fp_hi, int_hi));
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emit_insn (gen_floatsisf2 (fp_lo, int_lo));
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fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
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0, OPTAB_DIRECT);
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fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
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0, OPTAB_DIRECT);
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if (!rtx_equal_p (target, fp_hi))
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emit_move_insn (target, fp_hi);
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}
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/* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
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then replicate the value for all elements of the vector
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register. */
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static rtx
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ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
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{
|
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rtvec v;
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switch (mode)
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{
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case SFmode:
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if (vect)
|
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v = gen_rtvec (4, value, value, value, value);
|
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else
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v = gen_rtvec (4, value, CONST0_RTX (SFmode),
|
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CONST0_RTX (SFmode), CONST0_RTX (SFmode));
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return gen_rtx_CONST_VECTOR (V4SFmode, v);
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|
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case DFmode:
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if (vect)
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v = gen_rtvec (2, value, value);
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else
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v = gen_rtvec (2, value, CONST0_RTX (DFmode));
|
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return gen_rtx_CONST_VECTOR (V2DFmode, v);
|
||||
|
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default:
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gcc_unreachable ();
|
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}
|
||||
}
|
||||
|
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/* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
|
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Create a mask for the sign bit in MODE for an SSE register. If VECT is
|
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true, then replicate the mask for all elements of the vector register.
|
||||
|
|
@ -9869,7 +10099,7 @@ ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
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enum machine_mode vec_mode;
|
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HOST_WIDE_INT hi, lo;
|
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int shift = 63;
|
||||
rtvec v;
|
||||
rtx v;
|
||||
rtx mask;
|
||||
|
||||
/* Find the sign bit, sign extended to 2*HWI. */
|
||||
|
|
@ -9887,25 +10117,9 @@ ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
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mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
|
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mask = gen_lowpart (mode, mask);
|
||||
|
||||
if (mode == SFmode)
|
||||
{
|
||||
if (vect)
|
||||
v = gen_rtvec (4, mask, mask, mask, mask);
|
||||
else
|
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v = gen_rtvec (4, mask, CONST0_RTX (SFmode),
|
||||
CONST0_RTX (SFmode), CONST0_RTX (SFmode));
|
||||
vec_mode = V4SFmode;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (vect)
|
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v = gen_rtvec (2, mask, mask);
|
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else
|
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v = gen_rtvec (2, mask, CONST0_RTX (DFmode));
|
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vec_mode = V2DFmode;
|
||||
}
|
||||
|
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return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v));
|
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v = ix86_build_const_vector (mode, vect, mask);
|
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vec_mode = (mode == SFmode) ? V4SFmode : V2DFmode;
|
||||
return force_reg (vec_mode, v);
|
||||
}
|
||||
|
||||
/* Generate code for floating point ABS or NEG. */
|
||||
|
|
@ -19573,21 +19787,25 @@ x86_emit_floatuns (rtx operands[2])
|
|||
mode = GET_MODE (out);
|
||||
neglab = gen_label_rtx ();
|
||||
donelab = gen_label_rtx ();
|
||||
i1 = gen_reg_rtx (Pmode);
|
||||
f0 = gen_reg_rtx (mode);
|
||||
|
||||
emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, Pmode, 0, neglab);
|
||||
emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
|
||||
|
||||
expand_float (out, in, 0);
|
||||
|
||||
emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
|
||||
emit_jump_insn (gen_jump (donelab));
|
||||
emit_barrier ();
|
||||
|
||||
emit_label (neglab);
|
||||
|
||||
i0 = expand_simple_binop (Pmode, LSHIFTRT, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
|
||||
i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
|
||||
i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
|
||||
i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
|
||||
1, OPTAB_DIRECT);
|
||||
i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
|
||||
1, OPTAB_DIRECT);
|
||||
i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
|
||||
|
||||
expand_float (f0, i0, 0);
|
||||
|
||||
emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
|
||||
|
||||
emit_label (donelab);
|
||||
|
|
|
|||
|
|
@ -658,6 +658,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
|||
#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
|
||||
(ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
|
||||
|
||||
/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
|
||||
mandatory for the 64-bit ABI, and may or may not be true for other
|
||||
operating systems. */
|
||||
#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
|
||||
|
||||
/* Minimum allocation boundary for the code of a function. */
|
||||
#define FUNCTION_BOUNDARY 8
|
||||
|
||||
|
|
|
|||
|
|
@ -4331,6 +4331,38 @@
|
|||
}
|
||||
})
|
||||
|
||||
;; Unsigned conversion to SImode.
|
||||
|
||||
(define_expand "fixuns_trunc<mode>si2"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "")
|
||||
(fix:SI (match_operand:SSEMODEF 1 "register_operand" "")))]
|
||||
"!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
|
||||
&& TARGET_KEEPS_VECTOR_ALIGNED_STACK && !optimize_size"
|
||||
{
|
||||
ix86_expand_convert_uns_si_sse (operands[0], operands[1]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Unsigned conversion to HImode.
|
||||
;; Without these patterns, we'll try the unsigned SI conversion which
|
||||
;; is complex for SSE, rather than the signed SI conversion, which isn't.
|
||||
|
||||
(define_expand "fixuns_truncsfhi2"
|
||||
[(set (match_dup 2)
|
||||
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))
|
||||
(set (match_operand:HI 0 "nonimmediate_operand" "")
|
||||
(subreg:HI (match_dup 2) 0))]
|
||||
"TARGET_SSE_MATH"
|
||||
"operands[2] = gen_reg_rtx (SImode);")
|
||||
|
||||
(define_expand "fixuns_truncdfhi2"
|
||||
[(set (match_dup 2)
|
||||
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))
|
||||
(set (match_operand:HI 0 "nonimmediate_operand" "")
|
||||
(subreg:HI (match_dup 2) 0))]
|
||||
"TARGET_SSE_MATH"
|
||||
"operands[2] = gen_reg_rtx (SImode);")
|
||||
|
||||
;; When SSE is available, it is always faster to use it!
|
||||
(define_insn "fix_truncsfdi_sse"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r,r")
|
||||
|
|
@ -4848,8 +4880,14 @@
|
|||
(define_expand "floatdidf2"
|
||||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
|
||||
"TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
|
||||
"")
|
||||
"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
|
||||
{
|
||||
if (!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)
|
||||
{
|
||||
ix86_expand_convert_sign_didf_sse (operands[0], operands[1]);
|
||||
DONE;
|
||||
}
|
||||
})
|
||||
|
||||
(define_insn "*floatdidf2_mixed"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
|
||||
|
|
@ -4944,21 +4982,40 @@
|
|||
|
||||
(define_expand "floatunssisf2"
|
||||
[(use (match_operand:SF 0 "register_operand" ""))
|
||||
(use (match_operand:SI 1 "register_operand" ""))]
|
||||
"!TARGET_64BIT && TARGET_SSE_MATH"
|
||||
"x86_emit_floatuns (operands); DONE;")
|
||||
(use (match_operand:SI 1 "nonimmediate_operand" ""))]
|
||||
"!TARGET_64BIT"
|
||||
{
|
||||
if (TARGET_SSE_MATH && TARGET_SSE2)
|
||||
ix86_expand_convert_uns_sisf_sse (operands[0], operands[1]);
|
||||
else
|
||||
x86_emit_floatuns (operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "floatunssidf2"
|
||||
[(use (match_operand:DF 0 "register_operand" ""))
|
||||
(use (match_operand:SI 1 "nonimmediate_operand" ""))]
|
||||
"!TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE2"
|
||||
"ix86_expand_convert_uns_sidf_sse (operands[0], operands[1]); DONE;")
|
||||
|
||||
(define_expand "floatunsdisf2"
|
||||
[(use (match_operand:SF 0 "register_operand" ""))
|
||||
(use (match_operand:DI 1 "register_operand" ""))]
|
||||
(use (match_operand:DI 1 "nonimmediate_operand" ""))]
|
||||
"TARGET_64BIT && TARGET_SSE_MATH"
|
||||
"x86_emit_floatuns (operands); DONE;")
|
||||
|
||||
(define_expand "floatunsdidf2"
|
||||
[(use (match_operand:DF 0 "register_operand" ""))
|
||||
(use (match_operand:DI 1 "register_operand" ""))]
|
||||
"TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
|
||||
"x86_emit_floatuns (operands); DONE;")
|
||||
(use (match_operand:DI 1 "nonimmediate_operand" ""))]
|
||||
"TARGET_SSE_MATH && TARGET_SSE2
|
||||
&& (TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)"
|
||||
{
|
||||
if (TARGET_64BIT)
|
||||
x86_emit_floatuns (operands);
|
||||
else
|
||||
ix86_expand_convert_uns_didf_sse (operands[0], operands[1]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; SSE extract/set expanders
|
||||
|
||||
|
|
|
|||
|
|
@ -87,6 +87,47 @@
|
|||
(const_string "V4SF")
|
||||
(const_string "TI")))])
|
||||
|
||||
;; Move a DI from a 32-bit register pair (e.g. %edx:%eax) to an xmm.
|
||||
;; We'd rather avoid this entirely; if the 32-bit reg pair was loaded
|
||||
;; from memory, we'd prefer to load the memory directly into the %xmm
|
||||
;; register. To facilitate this happy circumstance, this pattern won't
|
||||
;; split until after register allocation. If the 64-bit value didn't
|
||||
;; come from memory, this is the best we can do. This is much better
|
||||
;; than storing %edx:%eax into a stack temporary and loading an %xmm
|
||||
;; from there.
|
||||
|
||||
(define_insn_and_split "movdi_to_sse"
|
||||
[(parallel
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=?x,x")
|
||||
(subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0))
|
||||
(clobber (match_scratch:V4SI 2 "=&x,X"))])]
|
||||
"!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(const_int 0)]
|
||||
{
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0:
|
||||
/* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
|
||||
Assemble the 64-bit DImode value in an xmm register. */
|
||||
emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode),
|
||||
gen_rtx_SUBREG (SImode, operands[1], 0)));
|
||||
emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode),
|
||||
gen_rtx_SUBREG (SImode, operands[1], 4)));
|
||||
emit_insn (gen_sse2_punpckldq (operands[0], operands[0], operands[2]));
|
||||
break;
|
||||
|
||||
case 1:
|
||||
emit_insn (gen_vec_concatv2di (operands[0], operands[1], const0_rtx));
|
||||
break;
|
||||
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "movv4sf"
|
||||
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
|
||||
(match_operand:V4SF 1 "nonimmediate_operand" ""))]
|
||||
|
|
@ -4118,7 +4159,7 @@
|
|||
[(set_attr "type" "sselog,ssemov,ssemov")
|
||||
(set_attr "mode" "TI,V4SF,V2SF")])
|
||||
|
||||
(define_insn "*vec_concatv2di"
|
||||
(define_insn "vec_concatv2di"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=Y2,?Y2,Y2,x,x,x")
|
||||
(vec_concat:V2DI
|
||||
(match_operand:DI 1 "nonimmediate_operand" " m,*y ,0 ,0,0,m")
|
||||
|
|
|
|||
Loading…
Reference in New Issue