mips.c (mips_expand_prologue): Convert to calls.struct_value_rtx hook.
2003-09-04 Eric Christopher <echristo@redhat.com> * config/mips/mips.c (mips_expand_prologue): Convert to calls.struct_value_rtx hook. (reg_or_const_float_1_operand): New. * config/mips/mips.h: Update Comments. (mips_arg): Add reg_or_const_float_1_operand. * config/mips/mips.md (divdf3); Convert to expander. (divsf3): Ditto. (*divdf3): New pattern. (*divsf3): Ditto. From-SVN: r71056
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Eric Christopher
Eric Christopher
parent
7a18b933f3
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ec24a74030
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@ -1,3 +1,15 @@
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2003-09-04 Eric Christopher <echristo@redhat.com>
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* config/mips/mips.c (mips_expand_prologue): Convert to
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calls.struct_value_rtx hook.
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(reg_or_const_float_1_operand): New.
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* config/mips/mips.h: Update Comments.
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(mips_arg): Add reg_or_const_float_1_operand.
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* config/mips/mips.md (divdf3); Convert to expander.
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(divsf3): Ditto.
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(*divdf3): New pattern.
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(*divsf3): Ditto.
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Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
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* toplev.c (wrapup_global_declarations): Fix final pass in
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@ -91,7 +103,7 @@ Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
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EXPAND_BUILTIN_SAVEREGS, SETUP_INCOMING_VARARGS,
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STRICT_ARGUMENT_NAMING, PRETEND_OUTGOING_VARARGS_NAMED): Convert
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to hooks.
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* config/alpha/alpha.c (alpha_output_mi_thunk_osf): Pass function
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to aggregate_value_p.
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* config/arm/arm.c (arm_init_cumulative_args,
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@ -108,7 +120,7 @@ Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
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function to aggregate_value_p.
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* objc/objc-act.c (generate_struct_by_value_array): Pass NULL to
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aggregate_value_p.
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* config/sh/sh-protos.h (sh_builtin_saveregs): Remove.
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(sh_attr_renesas_p, sh_cfun_attr_renesas_p, sh_function_arg,
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sh_function_arg_advance, sh_pass_in_reg_p): New. * config/sh/sh.c
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@ -150,7 +162,7 @@ Thu Sep 4 10:43:24 CEST 2003 Jan Hubicka <jh@suse.cz>
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SETUP_INCOMING_VARARGS, EXPAND_BUILTIN_SAVEREGS,
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PROMOTE_PROTOTYPES): Moved to sh.c. * config/sh/sh.md (call): Set
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call cookie to indicate renesas calls.
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2003-09-03 Mostafa Hagog <mustafa@il.ibm.com>
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* gcse.c (replace_one_set): New function.
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@ -1303,6 +1303,28 @@ reg_or_0_operand (rtx op, enum machine_mode mode)
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}
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}
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/* Accept a register or the floating point constant 1 in the appropriate mode. */
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int
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reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
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{
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REAL_VALUE_TYPE d;
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switch (GET_CODE (op))
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{
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case CONST_DOUBLE:
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if (mode != GET_MODE (op)
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|| (mode != DFmode && mode != SFmode))
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return 0;
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REAL_VALUE_FROM_CONST_DOUBLE (d, op);
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return REAL_VALUES_EQUAL (d, dconst1);
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default:
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return register_operand (op, mode);
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}
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}
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/* Accept the floating point constant 1 in the appropriate mode. */
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int
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@ -6714,7 +6736,7 @@ mips_expand_prologue (void)
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/* If struct value address is treated as the first argument, make it so. */
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if (aggregate_value_p (DECL_RESULT (fndecl), fndecl)
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&& ! current_function_returns_pcc_struct
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&& struct_value_incoming_rtx == 0)
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&& targetm.calls.struct_value_rtx (fndecl, 0) == 0)
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{
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tree type = build_pointer_type (fntype);
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tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
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@ -515,9 +515,9 @@ extern const struct mips_cpu_info *mips_tune_info;
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N_("Use GP relative sdata/sbss sections (now ignored)")}, \
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{"gpopt", 0, \
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N_("Use GP relative sdata/sbss sections (now ignored)")}, \
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{"no-gpOPT", 0, \
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{"no-gpOPT", 0, \
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N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
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{"no-gpopt", 0, \
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{"no-gpopt", 0, \
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N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
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{"stats", 0, \
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N_("Output compiler statistics (now ignored)")}, \
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@ -1415,12 +1415,7 @@ extern const struct mips_cpu_info *mips_tune_info;
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on the full register even if a narrower mode is specified. */
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#define WORD_REGISTER_OPERATIONS
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/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
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will either zero-extend or sign-extend. The value of this macro should
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be the code that says which one of the two operations is implicitly
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done, NIL if none.
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When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
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/* When in 64 bit mode, move insns will sign extend SImode and CCmode
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moves. All other references are zero extended. */
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#define LOAD_EXTEND_OP(MODE) \
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(TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
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@ -1809,31 +1804,31 @@ enum reg_class
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sub-initializer must be suitable as an initializer for the type
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`HARD_REG_SET' which is defined in `hard-reg-set.h'. */
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#define REG_CLASS_CONTENTS \
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{ \
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#define REG_CLASS_CONTENTS \
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{ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
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{ 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
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{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
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{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
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{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
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{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
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{ 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
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{ 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
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{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
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{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
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{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
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{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
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{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
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{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
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{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
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{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
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{ 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
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{ 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
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{ 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
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{ 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
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{ 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
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{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
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{ 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
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}
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@ -2668,9 +2663,7 @@ typedef struct mips_args {
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/* Specify the machine mode that this machine uses
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for the index in the tablejump instruction.
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??? Using HImode in mips16 mode can cause overflow. However, the
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overflow is no more likely than the overflow in a branch
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instruction. Large functions can currently break in both ways. */
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??? Using HImode in mips16 mode can cause overflow. */
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#define CASE_VECTOR_MODE \
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(TARGET_MIPS16 ? HImode : ptr_mode)
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@ -2808,6 +2801,7 @@ typedef struct mips_args {
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{"small_int", { CONST_INT }}, \
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{"mips_const_double_ok", { CONST_DOUBLE }}, \
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{"const_float_1_operand", { CONST_DOUBLE }}, \
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{"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
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{"simple_memory_operand", { MEM, SUBREG }}, \
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{"equality_op", { EQ, NE }}, \
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{"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
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@ -3366,7 +3360,7 @@ do { \
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do { \
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if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
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function_section (current_function_decl); \
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(*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
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(*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
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} while (0)
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/* This is how to output an assembler line
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@ -2365,6 +2365,17 @@
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;; ....................
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;;
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(define_expand "divdf3"
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[(set (match_operand:DF 0 "register_operand" "")
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(div:DF (match_operand:DF 1 "reg_or_const_float_1_operand" "")
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(match_operand:DF 2 "register_operand" "")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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{
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if (const_float_1_operand (operands[1], DFmode))
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if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
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FAIL;
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})
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;; This pattern works around the early SB-1 rev2 core "F1" erratum:
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;;
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;; If an mfc1 or dmfc1 happens to access the floating point register
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@ -2376,7 +2387,8 @@
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;;
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;; The workaround is to insert an unconditional 'mov' from/to the
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;; long latency op destination register.
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(define_insn "divdf3"
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(define_insn "*divdf3"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(div:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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@ -2395,6 +2407,17 @@
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(const_int 4)))])
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(define_expand "divsf3"
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[(set (match_operand:SF 0 "register_operand" "")
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(div:SF (match_operand:SF 1 "reg_or_const_float_1_operand" "")
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(match_operand:SF 2 "register_operand" "")))]
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"TARGET_HARD_FLOAT"
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{
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if (const_float_1_operand (operands[1], SFmode))
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if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
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FAIL;
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})
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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;;
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@ -2406,7 +2429,7 @@
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;; Therefore, we only allow div.s if not working around SB-1 rev2
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;; errata, or if working around those errata and a slight loss of
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;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
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(define_insn "divsf3"
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(define_insn "*divsf3"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(div:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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