From ec507f2d8b6a00a9139d53964d2e7df902336814 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Thu, 25 Mar 2004 17:43:24 +0000 Subject: [PATCH] rs6000.c (rs6000_always_hint): New variable. * config/rs6000/rs6000.c (rs6000_always_hint): New variable. (rs6000_sched_groups): New variable. (processor_target_table): Add power5. (rs6000_override_options): Set rs6000_sched_insert_nops, rs6000_sched_costly_dep and rs6000_sched_restricted_insns_priority from rs6000_sched_groups. (output_cbranch): Use rs6000_always_hint. (rs6000_variable_issue): Use rs6000_sched_groups. (rs6000_adjust_cost): Add CPU_POWER5. (is_microcoded_insn): Use rs6000_sched_groups. (is_dispatch_slot_restricted): Use rs6000_sched_groups. Return 2 for POWER5 cracked instructions. (is_cracked_insn): Use rs6000_sched_groups. (is_branch_slot_insn): Use rs6000_sched_groups. (rs6000_issue_rate): Add CPU_POWER5. (rs6000_sched_finish): Use rs6000_sched_groups. (rs6000_rtx_costs): Add PROCESSOR_POWER5. * config/rs6000/rs6000.h (processor_type): Add PROCESSOR_POWER5. (DEFAULT_SCHED_COSTLY_DEP): Delete. (DEFAULT_RESTRICTED_INSNS_PRIORITY): Delete. (DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME): Delete. * config/rs6000/rs6000.md (define_attr "cpu"): Add power5. * config/rs6000/power5.md: New file. * doc/invoke.texi: Add power5 option. From-SVN: r79958 --- gcc/ChangeLog | 27 ++++ gcc/config/rs6000/power5.md | 299 ++++++++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000.c | 77 ++++++---- gcc/config/rs6000/rs6000.h | 16 +- gcc/config/rs6000/rs6000.md | 3 +- gcc/doc/invoke.texi | 4 +- 6 files changed, 382 insertions(+), 44 deletions(-) create mode 100644 gcc/config/rs6000/power5.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f3be4d5c3fb..5a7d4d24bc3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,30 @@ +2004-03-25 David Edelsohn + + * config/rs6000/rs6000.c (rs6000_always_hint): New variable. + (rs6000_sched_groups): New variable. + (processor_target_table): Add power5. + (rs6000_override_options): Set rs6000_sched_insert_nops, + rs6000_sched_costly_dep and rs6000_sched_restricted_insns_priority + from rs6000_sched_groups. + (output_cbranch): Use rs6000_always_hint. + (rs6000_variable_issue): Use rs6000_sched_groups. + (rs6000_adjust_cost): Add CPU_POWER5. + (is_microcoded_insn): Use rs6000_sched_groups. + (is_dispatch_slot_restricted): Use rs6000_sched_groups. + Return 2 for POWER5 cracked instructions. + (is_cracked_insn): Use rs6000_sched_groups. + (is_branch_slot_insn): Use rs6000_sched_groups. + (rs6000_issue_rate): Add CPU_POWER5. + (rs6000_sched_finish): Use rs6000_sched_groups. + (rs6000_rtx_costs): Add PROCESSOR_POWER5. + * config/rs6000/rs6000.h (processor_type): Add PROCESSOR_POWER5. + (DEFAULT_SCHED_COSTLY_DEP): Delete. + (DEFAULT_RESTRICTED_INSNS_PRIORITY): Delete. + (DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME): Delete. + * config/rs6000/rs6000.md (define_attr "cpu"): Add power5. + * config/rs6000/power5.md: New file. + * doc/invoke.texi: Add power5 option. + 2004-03-25 Kazu Hirata * cfgrtl.c, dbxout.c, tree.def, config/darwin.h, diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md new file mode 100644 index 00000000000..59baa79c30c --- /dev/null +++ b/gcc/config/rs6000/power5.md @@ -0,0 +1,299 @@ +;; Scheduling description for IBM POWER5 processor. +;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 2, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to the +;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, +;; MA 02111-1307, USA. + +;; Sources: IBM Red Book and White Paper on POWER5 + +;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). +;; Instructions that update more than one register get broken into two +;; (split) or more internal ops. The chip can issue up to 5 +;; internal ops per cycle. + +(define_automaton "power5iu,power5fpu,power5misc") + +(define_cpu_unit "iu1_power5,iu2_power5" "power5iu") +(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc") +(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu") +(define_cpu_unit "bpu_power5,cru_power5" "power5misc") +(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5" + "power5misc") + +(define_reservation "lsq_power5" + "(du1_power5,lsu1_power5)\ + |(du2_power5,lsu2_power5)\ + |(du3_power5,nothing,lsu2_power5)\ + |(du4_power5,nothing,lsu1_power5)") + +(define_reservation "iq_power5" + "(du1_power5,iu1_power5)\ + |(du2_power5,iu2_power5)\ + |(du3_power5,nothing,iu2_power5)\ + |(du4_power5,nothing,iu1_power5)") + +(define_reservation "fpq_power5" + "(du1_power5,fpu1_power5)\ + |(du2_power5,fpu2_power5)\ + |(du3_power5,nothing,fpu2_power5)\ + |(du4_power5,nothing,fpu1_power5)") + +; Dispatch slots are allocated in order conforming to program order. +(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5") +(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5") +(absence_set "du3_power5" "du4_power5,du5_power5") +(absence_set "du4_power5" "du5_power5") + + +; Load/store +(define_insn_reservation "power5-load" 4 ; 3 + (and (eq_attr "type" "load") + (eq_attr "cpu" "power5")) + "lsq_power5") + +(define_insn_reservation "power5-load-ext" 5 + (and (eq_attr "type" "load_ext") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") + +(define_insn_reservation "power5-load-ext-update" 5 + (and (eq_attr "type" "load_ext_u") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5+du3_power5+du4_power5,\ + lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") + +(define_insn_reservation "power5-load-ext-update-indexed" 5 + (and (eq_attr "type" "load_ext_ux") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5+du3_power5+du4_power5,\ + iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") + +(define_insn_reservation "power5-load-update-indexed" 3 + (and (eq_attr "type" "load_ux") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5+du3_power5+du4_power5,\ + iu1_power5,lsu2_power5+iu2_power5") + +(define_insn_reservation "power5-load-update" 4 ; 3 + (and (eq_attr "type" "load_u") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,lsu1_power5+iu2_power5") + +(define_insn_reservation "power5-fpload" 6 ; 5 + (and (eq_attr "type" "fpload") + (eq_attr "cpu" "power5")) + "lsq_power5") + +(define_insn_reservation "power5-fpload-update" 6 ; 5 + (and (eq_attr "type" "fpload_u,fpload_ux") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,lsu1_power5+iu2_power5") + +(define_insn_reservation "power5-store" 1 + (and (eq_attr "type" "store") + (eq_attr "cpu" "power5")) + "(du1_power5,lsu1_power5,iu1_power5)\ + |(du2_power5,lsu2_power5,iu2_power5)\ + |(du3_power5,lsu2_power5,nothing,iu2_power5)\ + |(du4_power5,lsu1_power5,nothing,iu1_power5)") + +(define_insn_reservation "power5-store-update" 1 + (and (eq_attr "type" "store_u") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") + +(define_insn_reservation "power5-store-update-indexed" 1 + (and (eq_attr "type" "store_ux") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5+du3_power5+du4_power5,\ + iu1_power5,lsu2_power5+iu2_power5,iu2_power5") + +(define_insn_reservation "power5-fpstore" 1 + (and (eq_attr "type" "fpstore") + (eq_attr "cpu" "power5")) + "(du1_power5,lsu1_power5,fpu1_power5)\ + |(du2_power5,lsu2_power5,fpu2_power5)\ + |(du3_power5,lsu2_power5,nothing,fpu2_power5)\ + |(du4_power5,lsu1_power5,nothing,fpu1_power5)") + +(define_insn_reservation "power5-fpstore-update" 1 + (and (eq_attr "type" "fpstore_u,fpstore_ux") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") + + +; Integer latency is 2 cycles +(define_insn_reservation "power5-integer" 2 + (and (eq_attr "type" "integer") + (eq_attr "cpu" "power5")) + "iq_power5") + +(define_insn_reservation "power5-insert" 4 + (and (eq_attr "type" "insert_word") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5") + +(define_insn_reservation "power5-cmp" 3 + (and (eq_attr "type" "cmp,fast_compare") + (eq_attr "cpu" "power5")) + "iq_power5") + +(define_insn_reservation "power5-compare" 2 + (and (eq_attr "type" "compare,delayed_compare") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,iu1_power5,iu2_power5") + +(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") + +(define_insn_reservation "power5-lmul-cmp" 7 + (and (eq_attr "type" "lmul_compare") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,iu1_power5*6,iu2_power5") + +(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") + +(define_insn_reservation "power5-imul-cmp" 5 + (and (eq_attr "type" "imul_compare") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,iu1_power5*4,iu2_power5") + +(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") + +(define_insn_reservation "power5-lmul" 7 + (and (eq_attr "type" "lmul") + (eq_attr "cpu" "power5")) + "(du1_power5,iu1_power5*6)\ + |(du2_power5,iu2_power5*6)\ + |(du3_power5,iu2_power5*6)\ + |(du4_power5,iu2_power5*6)") +; |(du3_power5,nothing,iu2_power5*6)\ +; |(du4_power5,nothing,iu2_power5*6)") + +(define_insn_reservation "power5-imul" 5 + (and (eq_attr "type" "imul") + (eq_attr "cpu" "power5")) + "(du1_power5,iu1_power5*4)\ + |(du2_power5,iu2_power5*4)\ + |(du3_power5,iu2_power5*4)\ + |(du4_power5,iu1_power5*4)") +; |(du3_power5,nothing,iu2_power5*4)\ +; |(du4_power5,nothing,iu1_power5*4)") + +(define_insn_reservation "power5-imul3" 4 + (and (eq_attr "type" "imul2,imul3") + (eq_attr "cpu" "power5")) + "(du1_power5,iu1_power5*3)\ + |(du2_power5,iu2_power5*3)\ + |(du3_power5,iu2_power5*3)\ + |(du4_power5,iu1_power5*3)") +; |(du3_power5,nothing,iu2_power5*3)\ +; |(du4_power5,nothing,iu1_power5*3)") + + +; SPR move only executes in first IU. +; Integer division only executes in second IU. +(define_insn_reservation "power5-idiv" 36 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,iu2_power5*35") + +(define_insn_reservation "power5-ldiv" 68 + (and (eq_attr "type" "ldiv") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,iu2_power5*67") + + +(define_insn_reservation "power5-mtjmpr" 3 + (and (eq_attr "type" "mtjmpr,mfjmpr") + (eq_attr "cpu" "power5")) + "du1_power5,bpu_power5") + + +; Branches take dispatch Slot 4. The presence_sets prevent other insn from +; grabbing previous dispatch slots once this is assigned. +(define_insn_reservation "power5-branch" 2 + (and (eq_attr "type" "jmpreg,branch") + (eq_attr "cpu" "power5")) + "(du5_power5\ + |du4_power5+du5_power5\ + |du3_power5+du4_power5+du5_power5\ + |du2_power5+du3_power5+du4_power5+du5_power5\ + |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5") + + +; Condition Register logical ops are split if non-destructive (RT != RB) +(define_insn_reservation "power5-crlogical" 2 + (and (eq_attr "type" "cr_logical") + (eq_attr "cpu" "power5")) + "du1_power5,cru_power5") + +(define_insn_reservation "power5-delayedcr" 4 + (and (eq_attr "type" "delayed_cr") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5,cru_power5,cru_power5") + +; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu +(define_insn_reservation "power5-mfcr" 6 + (and (eq_attr "type" "mfcr") + (eq_attr "cpu" "power5")) + "du1_power5+du2_power5+du3_power5+du4_power5,\ + du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\ + cru_power5,cru_power5,cru_power5") + +; mfcrf (1 field) +(define_insn_reservation "power5-mfcrf" 3 + (and (eq_attr "type" "mfcrf") + (eq_attr "cpu" "power5")) + "du1_power5,cru_power5") + +; mtcrf (1 field) +(define_insn_reservation "power5-mtcr" 4 + (and (eq_attr "type" "mtcr") + (eq_attr "cpu" "power5")) + "du1_power5,iu1_power5") + +; Basic FP latency is 6 cycles +(define_insn_reservation "power5-fp" 6 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "power5")) + "fpq_power5") + +(define_insn_reservation "power5-fpcompare" 5 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "power5")) + "fpq_power5") + +(define_insn_reservation "power5-sdiv" 33 + (and (eq_attr "type" "sdiv,ddiv") + (eq_attr "cpu" "power5")) + "(du1_power5,fpu1_power5*28)\ + |(du2_power5,fpu2_power5*28)\ + |(du3_power5,fpu2_power5*28)\ + |(du4_power5,fpu1_power5*28)") +; |(du3_power5,nothing,fpu2_power5*28)\ +; |(du4_power5,nothing,fpu1_power5*28)") + +(define_insn_reservation "power5-sqrt" 40 + (and (eq_attr "type" "ssqrt,dsqrt") + (eq_attr "cpu" "power5")) + "(du1_power5,fpu1_power5*35)\ + |(du2_power5,fpu2_power5*35)\ + |(du3_power5,fpu2_power5*35)\ + |(du4_power5,fpu2_power5*35)") +; |(du3_power5,nothing,fpu2_power5*35)\ +; |(du4_power5,nothing,fpu2_power5*35)") + diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 09bc1b9606c..dc45a5092fb 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -124,6 +124,12 @@ struct rs6000_cpu_select rs6000_select[3] = { (const char *)0, "-mtune=", 1, 0 }, }; +/* Always emit branch hint bits. */ +static GTY(()) bool rs6000_always_hint; + +/* Schedule instructions for group formation. */ +static GTY(()) bool rs6000_sched_groups; + /* Support adjust_priority scheduler hook and -mprioritize-restricted-insns= option. */ const char *rs6000_sched_restricted_insns_priority_str; @@ -714,6 +720,8 @@ rs6000_override_options (const char *default_cpu) POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, {"power4", PROCESSOR_POWER4, POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, + {"power5", PROCESSOR_POWER5, + POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, {"powerpc64", PROCESSOR_POWERPC64, POWERPC_BASE_MASK | MASK_POWERPC64}, @@ -914,6 +922,11 @@ rs6000_override_options (const char *default_cpu) rs6000_long_double_type_size = 64; } + rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 + && rs6000_cpu != PROCESSOR_POWER5); + rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 + || rs6000_cpu == PROCESSOR_POWER5); + /* Handle -m(no-)longcall option. This is a bit of a cheap hack, using TARGET_OPTIONS to handle a toggle switch, but we're out of bits in target_flags so TARGET_SWITCHES cannot be used. @@ -942,13 +955,15 @@ rs6000_override_options (const char *default_cpu) } /* Handle -mprioritize-restricted-insns option. */ - rs6000_sched_restricted_insns_priority = DEFAULT_RESTRICTED_INSNS_PRIORITY; + rs6000_sched_restricted_insns_priority + = (rs6000_sched_groups ? 1 : 0); if (rs6000_sched_restricted_insns_priority_str) rs6000_sched_restricted_insns_priority = atoi (rs6000_sched_restricted_insns_priority_str); /* Handle -msched-costly-dep option. */ - rs6000_sched_costly_dep = DEFAULT_SCHED_COSTLY_DEP; + rs6000_sched_costly_dep + = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); if (rs6000_sched_costly_dep_str) { if (! strcmp (rs6000_sched_costly_dep_str, "no")) @@ -964,7 +979,8 @@ rs6000_override_options (const char *default_cpu) } /* Handle -minsert-sched-nops option. */ - rs6000_sched_insert_nops = DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME; + rs6000_sched_insert_nops + = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); if (rs6000_sched_insert_nops_str) { if (! strcmp (rs6000_sched_insert_nops_str, "no")) @@ -10066,7 +10082,6 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) { /* PROB is the difference from 50%. */ int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; - bool always_hint = rs6000_cpu != PROCESSOR_POWER4; /* Only hint for highly probable/improbable branches on newer cpus as static prediction overrides processor dynamic @@ -10074,7 +10089,7 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn) assume not taken for branches that are very close to 50% as a mispredicted taken branch is more expensive than a mispredicted not-taken branch. */ - if (always_hint + if (rs6000_always_hint || abs (prob) > REG_BR_PROB_BASE / 100 * 48) { if (abs (prob) > REG_BR_PROB_BASE / 20 @@ -13885,7 +13900,7 @@ rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, || GET_CODE (PATTERN (insn)) == CLOBBER) return more; - if (rs6000_cpu == PROCESSOR_POWER4) + if (rs6000_sched_groups) { if (is_microcoded_insn (insn)) return 0; @@ -13933,7 +13948,8 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED, || rs6000_cpu_attr == CPU_PPC750 || rs6000_cpu_attr == CPU_PPC7400 || rs6000_cpu_attr == CPU_PPC7450 - || rs6000_cpu_attr == CPU_POWER4) + || rs6000_cpu_attr == CPU_POWER4 + || rs6000_cpu_attr == CPU_POWER5) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0) && (get_attr_type (dep_insn) == TYPE_CMP @@ -13965,7 +13981,7 @@ is_microcoded_insn (rtx insn) || GET_CODE (PATTERN (insn)) == CLOBBER) return false; - if (rs6000_cpu == PROCESSOR_POWER4) + if (rs6000_sched_groups) { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_EXT_U @@ -13990,7 +14006,7 @@ is_dispatch_slot_restricted (rtx insn) { enum attr_type type; - if (rs6000_cpu != PROCESSOR_POWER4) + if (!rs6000_sched_groups) return 0; if (!insn @@ -14002,21 +14018,25 @@ is_dispatch_slot_restricted (rtx insn) type = get_attr_type (insn); - switch (type){ - case TYPE_MFCR: - case TYPE_MFCRF: - case TYPE_MTCR: - case TYPE_DELAYED_CR: - case TYPE_CR_LOGICAL: - case TYPE_MTJMPR: - case TYPE_MFJMPR: - return 1; - case TYPE_IDIV: - case TYPE_LDIV: - return 2; - default: - return 0; - } + switch (type) + { + case TYPE_MFCR: + case TYPE_MFCRF: + case TYPE_MTCR: + case TYPE_DELAYED_CR: + case TYPE_CR_LOGICAL: + case TYPE_MTJMPR: + case TYPE_MFJMPR: + return 1; + case TYPE_IDIV: + case TYPE_LDIV: + return 2; + default: + if (rs6000_cpu == PROCESSOR_POWER5 + && is_cracked_insn (insn)) + return 2; + return 0; + } } /* The function returns true if INSN is cracked into 2 instructions @@ -14030,7 +14050,7 @@ is_cracked_insn (rtx insn) || GET_CODE (PATTERN (insn)) == CLOBBER) return false; - if (rs6000_cpu == PROCESSOR_POWER4) + if (rs6000_sched_groups) { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_U || type == TYPE_STORE_U @@ -14058,7 +14078,7 @@ is_branch_slot_insn (rtx insn) || GET_CODE (PATTERN (insn)) == CLOBBER) return false; - if (rs6000_cpu == PROCESSOR_POWER4) + if (rs6000_sched_groups) { enum attr_type type = get_attr_type (insn); if (type == TYPE_BRANCH || type == TYPE_JMPREG) @@ -14158,6 +14178,7 @@ rs6000_issue_rate (void) case CPU_PPC630: return 4; case CPU_POWER4: + case CPU_POWER5: return 5; default: return 1; @@ -14711,7 +14732,7 @@ rs6000_sched_finish (FILE *dump, int sched_verbose) if (sched_verbose) fprintf (dump, "=== Finishing schedule.\n"); - if (reload_completed && rs6000_cpu == PROCESSOR_POWER4) + if (reload_completed && rs6000_sched_groups) { if (rs6000_sched_insert_nops == sched_finish_none) return; @@ -15905,6 +15926,7 @@ rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, return true; case PROCESSOR_POWER4: + case PROCESSOR_POWER5: *total = (GET_CODE (XEXP (x, 1)) != CONST_INT ? GET_MODE (XEXP (x, 1)) != DImode ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4) @@ -15990,6 +16012,7 @@ rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, return true; case PROCESSOR_POWER4: + case PROCESSOR_POWER5: *total = (GET_MODE (XEXP (x, 1)) != DImode ? COSTS_N_INSNS (18) : COSTS_N_INSNS (34)); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 9d64f7ef10b..7590dfd8717 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -386,7 +386,8 @@ enum processor_type PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_PPC8540, - PROCESSOR_POWER4 + PROCESSOR_POWER4, + PROCESSOR_POWER5 }; extern enum processor_type rs6000_cpu; @@ -550,19 +551,6 @@ extern const char *rs6000_warn_altivec_long_switch; #define TARGET_ALIGN_NATURAL 0 #endif -/* Set a default value for DEFAULT_SCHED_COSTLY_DEP used by target hook - is_costly_dependence. */ -#define DEFAULT_SCHED_COSTLY_DEP \ - (rs6000_cpu == PROCESSOR_POWER4 ? store_to_load_dep_costly : no_dep_costly) - -/* Define if the target has restricted dispatch slot instructions. */ -#define DEFAULT_RESTRICTED_INSNS_PRIORITY (rs6000_cpu == PROCESSOR_POWER4 ? 1 : 0) - -/* Set a default value for post scheduling nop insertion scheme - (used by taget hook sched_finish). */ -#define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \ - (rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none) - #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) #define TARGET_ALTIVEC_ABI rs6000_altivec_abi #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4f95e21673f..b88aef9fb99 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -82,7 +82,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4" +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" (const (symbol_ref "rs6000_cpu_attr"))) (automata_option "ndfa") @@ -99,6 +99,7 @@ (include "7450.md") (include "8540.md") (include "power4.md") +(include "power5.md") ;; Start with fixed-point load and store insns. Here we put only the more diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d9ef797bc5e..ac3a49ad0ae 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -7041,8 +7041,8 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, @samp{860}, @samp{970}, @samp{common}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3}, -@samp{power4}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, -@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}. +@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64}, +@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}. @option{-mcpu=common} selects a completely generic processor. Code generated under this option will run on any POWER or PowerPC processor.