2064.md ("z_mul", "z_inf"): New insn reservations.
2005-04-04 Andreas Krebbel <krebbel1@de.ibm.com> Adrian Straetling <straetling@de.ibm.com> * config/s390/2064.md ("z_mul", "z_inf"): New insn reservations. * config/s390/2084.md ("x_mul_hi", "x_mul_sidi", "x_div"): Likewise. * config/s390/s390.md ("imulhi", "imulsi", "imuldi"): Added to "type" attribute. ("imul"): Removed from "type" attribute. ("*muldi3_sign", "muldi3"): Changed type to imuldi. ("mulsi3/1", "mulsi3/3", "mulsi/4", "mulsidi3", "umulsidi3"): Changed type to imulsi. ("*mulsi3_sign", "mulsi3/2"): Changed type to imulhi. Co-Authored-By: Adrian Straetling <straetling@de.ibm.com> From-SVN: r97545
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@ -1,3 +1,16 @@
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2005-04-04 Andreas Krebbel <krebbel1@de.ibm.com>
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Adrian Straetling <straetling@de.ibm.com>
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* config/s390/2064.md ("z_mul", "z_inf"): New insn reservations.
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* config/s390/2084.md ("x_mul_hi", "x_mul_sidi", "x_div"): Likewise.
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* config/s390/s390.md ("imulhi", "imulsi", "imuldi"): Added to "type"
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attribute.
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("imul"): Removed from "type" attribute.
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("*muldi3_sign", "muldi3"): Changed type to imuldi.
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("mulsi3/1", "mulsi3/3", "mulsi/4", "mulsidi3", "umulsidi3"):
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Changed type to imulsi.
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("*mulsi3_sign", "mulsi3/2"): Changed type to imulhi.
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2005-04-04 Richard Sandiford <rsandifo@redhat.com>
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* config/mcore/mcore.h (target_flags, HARDLIT_BIT, ALIGN8_BIT, DIV_BIT)
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@ -72,6 +72,16 @@
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(eq_attr "type" "jsr"))
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"z_e1*5,z_wr")
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(define_insn_reservation "z_mul" 5
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(and (eq_attr "cpu" "g5,g6,z900")
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(eq_attr "type" "imulsi,imulhi"))
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"z_e1*5,z_wr")
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(define_insn_reservation "z_inf" 10
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(and (eq_attr "cpu" "g5,g6,z900")
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(eq_attr "type" "idiv,imuldi"))
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"z_e1*10,z_wr")
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;; For everything else we check the atype flag.
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(define_insn_reservation "z_int" 1
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@ -106,7 +106,22 @@
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(define_insn_reservation "x_call" 5
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "jsr"))
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"x-e1-np*5,x-wr-np")
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"x-e1-np*5,x-wr-np")
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(define_insn_reservation "x_mul_hi" 2
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "imulhi"))
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"x-e1-np*2,x-wr-np")
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(define_insn_reservation "x_mul_sidi" 4
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "imulsi,imuldi"))
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"x-e1-np*4,x-wr-np")
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(define_insn_reservation "x_div" 10
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "idiv"))
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"x-e1-np*10,x-wr-np")
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;;
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;; Multicycle insns
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@ -156,7 +156,8 @@
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;; Instruction type attribute used for scheduling.
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(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
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cs,vs,store,imul,idiv,
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cs,vs,store,idiv,
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imulhi,imulsi,imuldi,
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branch,jsr,fsimpd,fsimps,
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floadd,floads,fstored, fstores,
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fmuld,fmuls,fdivd,fdivs,
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@ -4512,7 +4513,7 @@
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msgfr\t%0,%2
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msgf\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")
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(set_attr "type" "imul")])
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(set_attr "type" "imuldi")])
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(define_insn "muldi3"
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[(set (match_operand:DI 0 "register_operand" "=d,d,d")
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@ -4524,7 +4525,7 @@
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mghi\t%0,%h2
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msg\t%0,%2"
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[(set_attr "op_type" "RRE,RI,RXY")
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(set_attr "type" "imul")])
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(set_attr "type" "imuldi")])
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;
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; mulsi3 instruction pattern(s).
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@ -4537,7 +4538,7 @@
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""
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"mh\t%0,%2"
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[(set_attr "op_type" "RX")
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(set_attr "type" "imul")])
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(set_attr "type" "imulhi")])
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(define_insn "mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
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@ -4550,7 +4551,7 @@
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ms\t%0,%2
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msy\t%0,%2"
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[(set_attr "op_type" "RRE,RI,RX,RXY")
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(set_attr "type" "imul")])
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(set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
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;
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; mulsidi3 instruction pattern(s).
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@ -4567,7 +4568,7 @@
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mr\t%0,%2
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m\t%0,%2"
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[(set_attr "op_type" "RR,RX")
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(set_attr "type" "imul")])
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(set_attr "type" "imulsi")])
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;
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; umulsidi3 instruction pattern(s).
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@ -4584,7 +4585,7 @@
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mlr\t%0,%2
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ml\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")
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(set_attr "type" "imul")])
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(set_attr "type" "imulsi")])
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;
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; muldf3 instruction pattern(s).
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