The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.
gcc/ChangeLog: PR target/101248 * config/i386/sse.md (avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>): Refined to .. (avx512f_sfixupimm<mode><maskz_scalar_name><round_saeonly_name>): this. (avx512f_sfixupimm<mode>_mask<round_saeonly_name>"): Refined. * config/i386/subst.md (maskz_scalar): New define_subst. (maskz_scalar_name): New subst_attr. (maskz_scalar_op5): Ditto. (round_saeonly_maskz_scalar_op5): Ditto. (round_saeonly_maskz_scalar_operand5): Ditto. gcc/testsuite/ChangeLog PR target/101248 * gcc.target/i386/pr101248.c: New test.
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liuhongt
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@ -9942,7 +9942,7 @@
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DONE;
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})
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(define_insn "avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>"
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(define_insn "avx512f_sfixupimm<mode><maskz_scalar_name><round_saeonly_name>"
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[(set (match_operand:VF_128 0 "register_operand" "=v")
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(vec_merge:VF_128
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(unspec:VF_128
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@ -9951,10 +9951,10 @@
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(match_operand:<sseintvecmode> 3 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
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(match_operand:SI 4 "const_0_to_255_operand")]
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UNSPEC_FIXUPIMM)
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(match_dup 1)
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(match_dup 2)
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(const_int 1)))]
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"TARGET_AVX512F"
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"vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2, %0<sd_mask_op5>|%0<sd_mask_op5>, %2, %<iptr>3<round_saeonly_sd_mask_op5>, %4}";
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"vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_maskz_scalar_op5>%3, %2, %0<maskz_scalar_op5>|%0<maskz_scalar_op5>, %2, %<iptr>3<round_saeonly_maskz_scalar_op5>, %4}";
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<ssescalarmode>")])
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@ -9968,7 +9968,7 @@
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(match_operand:<sseintvecmode> 3 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
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(match_operand:SI 4 "const_0_to_255_operand")]
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UNSPEC_FIXUPIMM)
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(match_dup 1)
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(match_dup 2)
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(const_int 1))
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(match_dup 1)
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(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
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@ -117,6 +117,25 @@
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(match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
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])
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(define_subst_attr "maskz_scalar_name" "maskz_scalar" "" "_maskz_1")
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(define_subst_attr "maskz_scalar_op5" "maskz_scalar" "" "%{%6%}%N5")
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(define_subst "maskz_scalar"
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[(set (match_operand:SUBST_V 0)
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(vec_merge:SUBST_V
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(match_operand:SUBST_V 1)
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(match_operand:SUBST_V 2)
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(const_int 1)))]
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"TARGET_AVX512F"
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[(set (match_dup 0)
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(vec_merge:SUBST_V
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(vec_merge:SUBST_V
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(match_dup 1)
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(match_operand:SUBST_V 3 "const0_operand" "C")
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(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
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(match_dup 2)
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(const_int 1)))])
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(define_subst_attr "round_name" "round" "" "_round")
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(define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
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(define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
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@ -163,6 +182,7 @@
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(define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
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(define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
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(define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
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(define_subst_attr "round_saeonly_maskz_scalar_operand5" "maskz_scalar" "%r5" "%r7")
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(define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
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(define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
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(define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
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@ -175,6 +195,7 @@
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(define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
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(define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
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(define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
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(define_subst_attr "round_saeonly_maskz_scalar_op5" "round_saeonly" "" "<round_saeonly_maskz_scalar_operand5>")
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(define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]")
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(define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
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(define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
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123
gcc/testsuite/gcc.target/i386/pr101248.c
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123
gcc/testsuite/gcc.target/i386/pr101248.c
Normal file
@ -0,0 +1,123 @@
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/* PR target/101248 */
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/* { dg-do run } */
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/* { dg-options "-O2 -mavx512vl -std=gnu99" } */
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/* { dg-require-effective-target avx512vl } */
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/* { dg-require-effective-target c99_runtime } */
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#define AVX512VL
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#define AVX512F_LEN 128
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#define AVX512F_LEN_HALF 128
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#include "avx512f-helper.h"
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#define SIZE (AVX512F_LEN / 64)
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#include "avx512f-mask-type.h"
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#include "math_m_pi.h"
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#include "float.h"
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static void
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CALC (double *r, double dest, double src, long long tbl)
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{
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switch (tbl & 0xf)
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{
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case 0:
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*r = dest;
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break;
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case 1:
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*r = src;
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break;
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case 2:
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*r = signbit (src) ? -NAN : NAN;
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break;
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case 3:
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*r = -NAN;
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break;
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case 4:
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*r = -INFINITY;
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break;
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case 5:
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*r = INFINITY;
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break;
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case 6:
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*r = signbit (src) ? -INFINITY : INFINITY;
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break;
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case 7:
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*r = 1.0 / -INFINITY;
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break;
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case 8:
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*r = 0.0;
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break;
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case 9:
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*r = -1.0;
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break;
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case 10:
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*r = 1.0;
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break;
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case 11:
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*r = 1.0 / 2.0;
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break;
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case 12:
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*r = 90.0;
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break;
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case 13:
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*r = M_PI_2;
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break;
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case 14:
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*r = DBL_MAX;
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break;
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case 15:
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*r = -DBL_MAX;
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break;
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default:
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abort ();
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}
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}
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void
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TEST (void)
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{
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int i, j;
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UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, s1;
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UNION_TYPE (AVX512F_LEN, i_q) s2;
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double res_ref[SIZE];
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float vals[2] = { -10, 10 };
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int controls[8] = {0, 0x11111111, 0x77777777, 0x88888888,
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0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc};
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MASK_TYPE mask = 1;
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for (i = 0; i < 2; i++)
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{
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for (j = 0; j < SIZE; j++)
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{
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s1.a[j] = vals[i];
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s2.a[j] = controls[j];
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res1.a[j] = DEFAULT_VALUE;
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res2.a[j] = DEFAULT_VALUE;
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res3.a[j] = DEFAULT_VALUE;
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CALC (&res_ref[j], res1.a[j], s1.a[j], s2.a[j]);
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}
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res1.x = INTRINSIC (_fixupimm_pd) (res1.x, s1.x, s2.x, 0);
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res2.x = INTRINSIC (_mask_fixupimm_pd) (res2.x, mask, s1.x, s2.x, 0);
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res3.x = INTRINSIC (_maskz_fixupimm_pd) (mask, res3.x, s1.x, s2.x, 0);
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if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
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abort ();
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MASK_MERGE(d) (res_ref, mask, SIZE);
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if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
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abort ();
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MASK_ZERO(d) (res_ref, mask, SIZE);
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if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
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abort ();
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}
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}
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void
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test_256 (void)
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{}
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