AVX-512. 68/n. Add vpmullw, vpacksdw, pmaddwd insn.
gcc/ * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_PMADDWD512. (define_mode_iterator VI2_AVX2): Add V32HI mode. (define_expand "mul<mode>3<mask_name>"): Add masking. (define_insn "*mul<mode>3<mask_name>"): Ditto. (define_expand "<s>mul<mode>3_highpart<mask_name>"): Ditto. (define_insn "*<s>mul<mode>3_highpart<mask_name>"): Ditto. (define_insn "avx512bw_pmaddwd512<mode><mask_name>"): New. (define_mode_attr SDOT_PMADD_SUF): Ditto. (define_expand "sdot_prod<mode>"): Add <SDOT_PMADD_SUF>. (define_insn "<sse2_avx2>_packssdw<mask_name>"): Add masking. (define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"): Ditto. (define_insn "avx2_packusdw"): Delete. (define_insn "sse4_1_packusdw"): Ditto. (define_insn "<sse4_1_avx2>_packusdw<mask_name>"): New. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r216185
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
1aff6f9a2f
commit
ed3e611e05
@ -1,3 +1,28 @@
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2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/i386/sse.md
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(define_c_enum "unspec"): Add UNSPEC_PMADDWD512.
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(define_mode_iterator VI2_AVX2): Add V32HI mode.
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(define_expand "mul<mode>3<mask_name>"): Add masking.
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(define_insn "*mul<mode>3<mask_name>"): Ditto.
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(define_expand "<s>mul<mode>3_highpart<mask_name>"): Ditto.
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(define_insn "*<s>mul<mode>3_highpart<mask_name>"): Ditto.
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(define_insn "avx512bw_pmaddwd512<mode><mask_name>"): New.
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(define_mode_attr SDOT_PMADD_SUF): Ditto.
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(define_expand "sdot_prod<mode>"): Add <SDOT_PMADD_SUF>.
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(define_insn "<sse2_avx2>_packssdw<mask_name>"): Add masking.
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(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"): Ditto.
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(define_insn "avx2_packusdw"): Delete.
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(define_insn "sse4_1_packusdw"): Ditto.
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(define_insn "<sse4_1_avx2>_packusdw<mask_name>"): New.
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2014-10-14 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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@ -132,6 +132,7 @@
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;; For AVX512BW support
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UNSPEC_DBPSADBW
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UNSPEC_PMADDUBSW512
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UNSPEC_PMADDWD512
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UNSPEC_PSHUFHW
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UNSPEC_PSHUFLW
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@ -300,7 +301,7 @@
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[(V32QI "TARGET_AVX2") V16QI])
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(define_mode_iterator VI2_AVX2
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[(V16HI "TARGET_AVX2") V8HI])
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[(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI])
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(define_mode_iterator VI2_AVX512F
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[(V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI])
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@ -9135,28 +9136,30 @@
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DONE;
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})
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(define_expand "mul<mode>3"
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(define_expand "mul<mode>3<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand")
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(mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand")
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(match_operand:VI2_AVX2 2 "nonimmediate_operand")))]
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"TARGET_SSE2"
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"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
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(define_insn "*mul<mode>3"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x")
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(mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v")
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(match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))]
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"TARGET_SSE2 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
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(define_insn "*mul<mode>3<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
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(mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v")
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(match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))]
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"TARGET_SSE2
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&& ix86_binary_operator_ok (MULT, <MODE>mode, operands)
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&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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"@
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pmullw\t{%2, %0|%0, %2}
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vpmullw\t{%2, %1, %0|%0, %1, %2}"
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vpmullw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseimul")
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(set_attr "prefix_data16" "1,*")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "<s>mul<mode>3_highpart"
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(define_expand "<s>mul<mode>3_highpart<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand")
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(truncate:VI2_AVX2
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(lshiftrt:<ssedoublemode>
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@ -9166,23 +9169,26 @@
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(any_extend:<ssedoublemode>
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(match_operand:VI2_AVX2 2 "nonimmediate_operand")))
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(const_int 16))))]
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"TARGET_SSE2"
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"TARGET_SSE2
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&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
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(define_insn "*<s>mul<mode>3_highpart"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x")
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(define_insn "*<s>mul<mode>3_highpart<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
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(truncate:VI2_AVX2
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(lshiftrt:<ssedoublemode>
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(mult:<ssedoublemode>
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(any_extend:<ssedoublemode>
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(match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,x"))
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(match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v"))
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(any_extend:<ssedoublemode>
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(match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,xm")))
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(match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))
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(const_int 16))))]
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"TARGET_SSE2 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
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"TARGET_SSE2
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&& ix86_binary_operator_ok (MULT, <MODE>mode, operands)
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&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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"@
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pmulh<u>w\t{%2, %0|%0, %2}
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vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
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vpmulh<u>w\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseimul")
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(set_attr "prefix_data16" "1,*")
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@ -9425,6 +9431,18 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "TI")])
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(define_insn "avx512bw_pmaddwd512<mode><mask_name>"
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[(set (match_operand:<sseunpackmode> 0 "register_operand" "=v")
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(unspec:<sseunpackmode>
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[(match_operand:VI2_AVX2 1 "register_operand" "v")
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(match_operand:VI2_AVX2 2 "nonimmediate_operand" "vm")]
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UNSPEC_PMADDWD512))]
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"TARGET_AVX512BW && <mask_mode512bit_condition>"
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"vpmaddwd\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
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[(set_attr "type" "sseiadd")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_expand "avx2_pmaddwd"
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[(set (match_operand:V8SI 0 "register_operand")
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(plus:V8SI
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@ -9665,6 +9683,9 @@
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DONE;
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})
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(define_mode_attr SDOT_PMADD_SUF
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[(V32HI "512v32hi") (V16HI "") (V8HI "")])
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(define_expand "sdot_prod<mode>"
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[(match_operand:<sseunpackmode> 0 "register_operand")
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(match_operand:VI2_AVX2 1 "register_operand")
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@ -9673,7 +9694,7 @@
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"TARGET_SSE2"
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{
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rtx t = gen_reg_rtx (<sseunpackmode>mode);
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emit_insn (gen_<sse2_avx2>_pmaddwd (t, operands[1], operands[2]));
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emit_insn (gen_<sse2_avx2>_pmaddwd<SDOT_PMADD_SUF> (t, operands[1], operands[2]));
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_PLUS (<sseunpackmode>mode,
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operands[3], t)));
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@ -10857,17 +10878,17 @@
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(set_attr "prefix" "orig,maybe_evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "<sse2_avx2>_packssdw"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x")
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(define_insn "<sse2_avx2>_packssdw<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
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(vec_concat:VI2_AVX2
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(ss_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 1 "register_operand" "0,x"))
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(match_operand:<sseunpackmode> 1 "register_operand" "0,v"))
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(ss_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,xm"))))]
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"TARGET_SSE2"
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(match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))]
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"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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"@
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packssdw\t{%2, %0|%0, %2}
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vpackssdw\t{%2, %1, %0|%0, %1, %2}"
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vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1,*")
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@ -13349,29 +13370,30 @@
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ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
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})
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(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x")
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(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
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(truncate:VI2_AVX2
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(lshiftrt:<ssedoublemode>
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(plus:<ssedoublemode>
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(lshiftrt:<ssedoublemode>
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(mult:<ssedoublemode>
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(sign_extend:<ssedoublemode>
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(match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,x"))
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(match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v"))
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(sign_extend:<ssedoublemode>
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(match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,xm")))
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(match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))
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(const_int 14))
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(match_operand:VI2_AVX2 3 "const1_operand"))
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(const_int 1))))]
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"TARGET_SSSE3 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
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"TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
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&& ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
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"@
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pmulhrsw\t{%2, %0|%0, %2}
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vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
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vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sseimul")
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(set_attr "prefix_data16" "1,*")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "orig,vex")
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(set_attr "prefix" "orig,maybe_evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "*ssse3_pmulhrswv4hi3"
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@ -13743,36 +13765,22 @@
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(set_attr "btver2_decode" "vector,vector")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "avx2_packusdw"
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[(set (match_operand:V16HI 0 "register_operand" "=x")
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(vec_concat:V16HI
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(us_truncate:V8HI
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(match_operand:V8SI 1 "register_operand" "x"))
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(us_truncate:V8HI
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(match_operand:V8SI 2 "nonimmediate_operand" "xm"))))]
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"TARGET_AVX2"
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"vpackusdw\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "vex")
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(set_attr "mode" "OI")])
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(define_insn "sse4_1_packusdw"
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[(set (match_operand:V8HI 0 "register_operand" "=x,x")
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(vec_concat:V8HI
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(us_truncate:V4HI
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(match_operand:V4SI 1 "register_operand" "0,x"))
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(us_truncate:V4HI
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(match_operand:V4SI 2 "nonimmediate_operand" "xm,xm"))))]
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"TARGET_SSE4_1"
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(define_insn "<sse4_1_avx2>_packusdw<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
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(vec_concat:VI2_AVX2
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(us_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 1 "register_operand" "0,v"))
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(us_truncate:<ssehalfvecmode>
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(match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))]
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"TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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"@
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packusdw\t{%2, %0|%0, %2}
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vpackusdw\t{%2, %1, %0|%0, %1, %2}"
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vpackusdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "TI")])
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(set_attr "prefix" "orig,maybe_evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "<sse4_1_avx2>_pblendvb"
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[(set (match_operand:VI1_AVX2 0 "register_operand" "=x,x")
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