From ed4bcdba7c19299844f11c15da6f93116b0b180f Mon Sep 17 00:00:00 2001
From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Thu, 19 Dec 2013 18:29:09 +0000
Subject: [PATCH] neon-testgen.ml (effective_target): Handle "CRYPTO".

[gcc/]
2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/neon-testgen.ml (effective_target): Handle "CRYPTO".

[gcc/testsuite]
2013-12-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	 * lib/target-supports.exp (check_effective_target_arm_crypto_ok):
	 New procedure.
	 (add_options_for_arm_crypto): Likewise.
	 * gcc.target/arm/crypto-vaesdq_u8.c: New test.
	 * gcc.target/arm/crypto-vaeseq_u8.c: Likewise.
	 * gcc.target/arm/crypto-vaesimcq_u8.c: Likewise.
	 * gcc.target/arm/crypto-vaesmcq_u8.c: Likewise.
	 * gcc.target/arm/crypto-vldrq_p128.c: Likewise.
	 * gcc.target/arm/crypto-vmull_high_p64.c: Likewise.
	 * gcc.target/arm/crypto-vmullp64.c: Likewise.
	 * gcc.target/arm/crypto-vsha1cq_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha1h_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha1mq_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha1pq_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha1su0q_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha1su1q_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha256h2q_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha256hq_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha256su0q_u32.c: Likewise.
	 * gcc.target/arm/crypto-vsha256su1q_u32.c: Likewise.
	 * gcc.target/arm/crypto-vstrq_p128.c: Likewise.
	 * gcc.target/arm/neon/vbslQp64: Generate.
	 * gcc.target/arm/neon/vbslp64: Likewise.
	 * gcc.target/arm/neon/vcombinep64: Likewise.
	 * gcc.target/arm/neon/vcreatep64: Likewise.
	 * gcc.target/arm/neon/vdupQ_lanep64: Likewise.
	 * gcc.target/arm/neon/vdupQ_np64: Likewise.
	 * gcc.target/arm/neon/vdup_lanep64: Likewise.
	 * gcc.target/arm/neon/vdup_np64: Likewise.
	 * gcc.target/arm/neon/vextQp64: Likewise.
	 * gcc.target/arm/neon/vextp64: Likewise.
	 * gcc.target/arm/neon/vget_highp64: Likewise.
	 * gcc.target/arm/neon/vget_lowp64: Likewise.
	 * gcc.target/arm/neon/vld1Q_dupp64: Likewise.
	 * gcc.target/arm/neon/vld1Q_lanep64: Likewise.
	 * gcc.target/arm/neon/vld1Qp64: Likewise.
	 * gcc.target/arm/neon/vld1_dupp64: Likewise.
	 * gcc.target/arm/neon/vld1_lanep64: Likewise.
	 * gcc.target/arm/neon/vld1p64: Likewise.
	 * gcc.target/arm/neon/vld2_dupp64: Likewise.
	 * gcc.target/arm/neon/vld2p64: Likewise.
	 * gcc.target/arm/neon/vld3_dupp64: Likewise.
	 * gcc.target/arm/neon/vld3p64: Likewise.
	 * gcc.target/arm/neon/vld4_dupp64: Likewise.
	 * gcc.target/arm/neon/vld4p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQf32_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQf32_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_f32: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_p16: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_p8: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_s16: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_s32: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_s64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_s8: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_u16: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_u32: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_u64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp128_u8: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp16_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp16_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_f32: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_p16: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_p8: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_s16: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_s32: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_s64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_s8: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_u16: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_u32: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_u64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp64_u8: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp8_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQp8_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs16_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs16_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs32_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs32_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs64_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs64_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs8_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQs8_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu16_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu16_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu32_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu32_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu64_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu64_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu8_p128: Likewise.
	 * gcc.target/arm/neon/vreinterpretQu8_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretf32_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretp16_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_f32: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_p16: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_p8: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_s16: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_s32: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_s64: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_s8: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_u16: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_u32: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_u64: Likewise.
	 * gcc.target/arm/neon/vreinterpretp64_u8: Likewise.
	 * gcc.target/arm/neon/vreinterpretp8_p64: Likewise.
	 * gcc.target/arm/neon/vreinterprets16_p64: Likewise.
	 * gcc.target/arm/neon/vreinterprets32_p64: Likewise.
	 * gcc.target/arm/neon/vreinterprets64_p64: Likewise.
	 * gcc.target/arm/neon/vreinterprets8_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretu16_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretu32_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretu64_p64: Likewise.
	 * gcc.target/arm/neon/vreinterpretu8_p64: Likewise.
	 * gcc.target/arm/neon/vsliQ_np64: Likewise.
	 * gcc.target/arm/neon/vsli_np64: Likewise.
	 * gcc.target/arm/neon/vsriQ_np64: Likewise.
	 * gcc.target/arm/neon/vsri_np64: Likewise.
	 * gcc.target/arm/neon/vst1Q_lanep64: Likewise.
	 * gcc.target/arm/neon/vst1Qp64: Likewise.
	 * gcc.target/arm/neon/vst1_lanep64: Likewise.
	 * gcc.target/arm/neon/vst1p64: Likewise.
	 * gcc.target/arm/neon/vst2p64: Likewise.
	 * gcc.target/arm/neon/vst3p64: Likewise.
	 * gcc.target/arm/neon/vst4p64: Likewise.

From-SVN: r206131
---
 gcc/ChangeLog                                 |   4 +
 gcc/config/arm/neon-testgen.ml                |   3 +-
 gcc/testsuite/ChangeLog                       | 127 ++++++++++++++++++
 .../gcc.target/arm/crypto-vaesdq_u8.c         |  22 +++
 .../gcc.target/arm/crypto-vaeseq_u8.c         |  22 +++
 .../gcc.target/arm/crypto-vaesimcq_u8.c       |  20 +++
 .../gcc.target/arm/crypto-vaesmcq_u8.c        |  20 +++
 .../gcc.target/arm/crypto-vldrq_p128.c        |  13 ++
 .../gcc.target/arm/crypto-vmull_high_p64.c    |  15 +++
 .../gcc.target/arm/crypto-vmullp64.c          |  15 +++
 .../gcc.target/arm/crypto-vsha1cq_u32.c       |  18 +++
 .../gcc.target/arm/crypto-vsha1h_u32.c        |  14 ++
 .../gcc.target/arm/crypto-vsha1mq_u32.c       |  18 +++
 .../gcc.target/arm/crypto-vsha1pq_u32.c       |  18 +++
 .../gcc.target/arm/crypto-vsha1su0q_u32.c     |  18 +++
 .../gcc.target/arm/crypto-vsha1su1q_u32.c     |  17 +++
 .../gcc.target/arm/crypto-vsha256h2q_u32.c    |  18 +++
 .../gcc.target/arm/crypto-vsha256hq_u32.c     |  18 +++
 .../gcc.target/arm/crypto-vsha256su0q_u32.c   |  17 +++
 .../gcc.target/arm/crypto-vsha256su1q_u32.c   |  18 +++
 .../gcc.target/arm/crypto-vstrq_p128.c        |  13 ++
 gcc/testsuite/gcc.target/arm/neon/vbslQp64.c  |  22 +++
 gcc/testsuite/gcc.target/arm/neon/vbslp64.c   |  22 +++
 .../gcc.target/arm/neon/vcombinep64.c         |  20 +++
 .../gcc.target/arm/neon/vcreatep64.c          |  19 +++
 .../gcc.target/arm/neon/vdupQ_lanep64.c       |  19 +++
 .../gcc.target/arm/neon/vdupQ_np64.c          |  19 +++
 .../gcc.target/arm/neon/vdup_lanep64.c        |  19 +++
 gcc/testsuite/gcc.target/arm/neon/vdup_np64.c |  19 +++
 gcc/testsuite/gcc.target/arm/neon/vextQp64.c  |  21 +++
 gcc/testsuite/gcc.target/arm/neon/vextp64.c   |  21 +++
 .../gcc.target/arm/neon/vget_highp64.c        |  19 +++
 .../gcc.target/arm/neon/vget_lowp64.c         |  19 +++
 .../gcc.target/arm/neon/vld1Q_dupp64.c        |  19 +++
 .../gcc.target/arm/neon/vld1Q_lanep64.c       |  20 +++
 gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c  |  19 +++
 .../gcc.target/arm/neon/vld1_dupp64.c         |  19 +++
 .../gcc.target/arm/neon/vld1_lanep64.c        |  20 +++
 gcc/testsuite/gcc.target/arm/neon/vld1p64.c   |  19 +++
 .../gcc.target/arm/neon/vld2_dupp64.c         |  19 +++
 gcc/testsuite/gcc.target/arm/neon/vld2p64.c   |  19 +++
 .../gcc.target/arm/neon/vld3_dupp64.c         |  19 +++
 gcc/testsuite/gcc.target/arm/neon/vld3p64.c   |  19 +++
 .../gcc.target/arm/neon/vld4_dupp64.c         |  19 +++
 gcc/testsuite/gcc.target/arm/neon/vld4p64.c   |  19 +++
 .../arm/neon/vreinterpretQf32_p128.c          |  19 +++
 .../arm/neon/vreinterpretQf32_p64.c           |  19 +++
 .../arm/neon/vreinterpretQp128_f32.c          |  19 +++
 .../arm/neon/vreinterpretQp128_p16.c          |  19 +++
 .../arm/neon/vreinterpretQp128_p64.c          |  19 +++
 .../arm/neon/vreinterpretQp128_p8.c           |  19 +++
 .../arm/neon/vreinterpretQp128_s16.c          |  19 +++
 .../arm/neon/vreinterpretQp128_s32.c          |  19 +++
 .../arm/neon/vreinterpretQp128_s64.c          |  19 +++
 .../arm/neon/vreinterpretQp128_s8.c           |  19 +++
 .../arm/neon/vreinterpretQp128_u16.c          |  19 +++
 .../arm/neon/vreinterpretQp128_u32.c          |  19 +++
 .../arm/neon/vreinterpretQp128_u64.c          |  19 +++
 .../arm/neon/vreinterpretQp128_u8.c           |  19 +++
 .../arm/neon/vreinterpretQp16_p128.c          |  19 +++
 .../arm/neon/vreinterpretQp16_p64.c           |  19 +++
 .../arm/neon/vreinterpretQp64_f32.c           |  19 +++
 .../arm/neon/vreinterpretQp64_p128.c          |  19 +++
 .../arm/neon/vreinterpretQp64_p16.c           |  19 +++
 .../gcc.target/arm/neon/vreinterpretQp64_p8.c |  19 +++
 .../arm/neon/vreinterpretQp64_s16.c           |  19 +++
 .../arm/neon/vreinterpretQp64_s32.c           |  19 +++
 .../arm/neon/vreinterpretQp64_s64.c           |  19 +++
 .../gcc.target/arm/neon/vreinterpretQp64_s8.c |  19 +++
 .../arm/neon/vreinterpretQp64_u16.c           |  19 +++
 .../arm/neon/vreinterpretQp64_u32.c           |  19 +++
 .../arm/neon/vreinterpretQp64_u64.c           |  19 +++
 .../gcc.target/arm/neon/vreinterpretQp64_u8.c |  19 +++
 .../arm/neon/vreinterpretQp8_p128.c           |  19 +++
 .../gcc.target/arm/neon/vreinterpretQp8_p64.c |  19 +++
 .../arm/neon/vreinterpretQs16_p128.c          |  19 +++
 .../arm/neon/vreinterpretQs16_p64.c           |  19 +++
 .../arm/neon/vreinterpretQs32_p128.c          |  19 +++
 .../arm/neon/vreinterpretQs32_p64.c           |  19 +++
 .../arm/neon/vreinterpretQs64_p128.c          |  19 +++
 .../arm/neon/vreinterpretQs64_p64.c           |  19 +++
 .../arm/neon/vreinterpretQs8_p128.c           |  19 +++
 .../gcc.target/arm/neon/vreinterpretQs8_p64.c |  19 +++
 .../arm/neon/vreinterpretQu16_p128.c          |  19 +++
 .../arm/neon/vreinterpretQu16_p64.c           |  19 +++
 .../arm/neon/vreinterpretQu32_p128.c          |  19 +++
 .../arm/neon/vreinterpretQu32_p64.c           |  19 +++
 .../arm/neon/vreinterpretQu64_p128.c          |  19 +++
 .../arm/neon/vreinterpretQu64_p64.c           |  19 +++
 .../arm/neon/vreinterpretQu8_p128.c           |  19 +++
 .../gcc.target/arm/neon/vreinterpretQu8_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretf32_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp16_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_f32.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_p16.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_p8.c  |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_s16.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_s32.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_s64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_s8.c  |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_u16.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_u32.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_u64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretp64_u8.c  |  19 +++
 .../gcc.target/arm/neon/vreinterpretp8_p64.c  |  19 +++
 .../gcc.target/arm/neon/vreinterprets16_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterprets32_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterprets64_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterprets8_p64.c  |  19 +++
 .../gcc.target/arm/neon/vreinterpretu16_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretu32_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretu64_p64.c |  19 +++
 .../gcc.target/arm/neon/vreinterpretu8_p64.c  |  19 +++
 .../gcc.target/arm/neon/vsliQ_np64.c          |  21 +++
 gcc/testsuite/gcc.target/arm/neon/vsli_np64.c |  21 +++
 .../gcc.target/arm/neon/vsriQ_np64.c          |  21 +++
 gcc/testsuite/gcc.target/arm/neon/vsri_np64.c |  21 +++
 .../gcc.target/arm/neon/vst1Q_lanep64.c       |  20 +++
 gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c  |  20 +++
 .../gcc.target/arm/neon/vst1_lanep64.c        |  20 +++
 gcc/testsuite/gcc.target/arm/neon/vst1p64.c   |  20 +++
 gcc/testsuite/gcc.target/arm/neon/vst2p64.c   |  20 +++
 gcc/testsuite/gcc.target/arm/neon/vst3p64.c   |  20 +++
 gcc/testsuite/gcc.target/arm/neon/vst4p64.c   |  20 +++
 gcc/testsuite/lib/target-supports.exp         |  24 ++++
 125 files changed, 2456 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vmullp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vbslp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vextQp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vextp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld1p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld2p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld3p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vld4p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vst1p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vst2p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vst3p64.c
 create mode 100644 gcc/testsuite/gcc.target/arm/neon/vst4p64.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3a19c2ec45c..6522c600218 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/arm/neon-testgen.ml (effective_target): Handle "CRYPTO".
+
 2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	 * config/arm/arm.c (enum arm_builtins): Add crypto builtins.
diff --git a/gcc/config/arm/neon-testgen.ml b/gcc/config/arm/neon-testgen.ml
index 543318bfcc6..e1e4e250787 100644
--- a/gcc/config/arm/neon-testgen.ml
+++ b/gcc/config/arm/neon-testgen.ml
@@ -167,6 +167,7 @@ let effective_target features =
                                         | _ -> false)
                      features with
       Requires_feature "FMA" -> "arm_neonv2"
+    | Requires_feature "CRYPTO" -> "arm_crypto"
     | Requires_arch 8 -> "arm_v8_neon"
     | Requires_FP_bit 1 -> "arm_neon_fp16"
     | _ -> assert false
@@ -300,5 +301,5 @@ let test_intrinsic_group dir (opcode, features, shape, name, munge, types) =
 (* Program entry point.  *)
 let _ =
   let directory = if Array.length Sys.argv <> 1 then Sys.argv.(1) else "." in
-    List.iter (test_intrinsic_group directory) (reinterp @ ops)
+    List.iter (test_intrinsic_group directory) (reinterp @ reinterpq @ ops)
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 318550a8f67..7e40136359c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,130 @@
+2013-12-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	 * lib/target-supports.exp (check_effective_target_arm_crypto_ok):
+	 New procedure.
+	 (add_options_for_arm_crypto): Likewise.
+	 * gcc.target/arm/crypto-vaesdq_u8.c: New test.
+	 * gcc.target/arm/crypto-vaeseq_u8.c: Likewise.
+	 * gcc.target/arm/crypto-vaesimcq_u8.c: Likewise.
+	 * gcc.target/arm/crypto-vaesmcq_u8.c: Likewise.
+	 * gcc.target/arm/crypto-vldrq_p128.c: Likewise.
+	 * gcc.target/arm/crypto-vmull_high_p64.c: Likewise.
+	 * gcc.target/arm/crypto-vmullp64.c: Likewise.
+	 * gcc.target/arm/crypto-vsha1cq_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha1h_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha1mq_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha1pq_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha1su0q_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha1su1q_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha256h2q_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha256hq_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha256su0q_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vsha256su1q_u32.c: Likewise.
+	 * gcc.target/arm/crypto-vstrq_p128.c: Likewise.
+	 * gcc.target/arm/neon/vbslQp64: Generate.
+	 * gcc.target/arm/neon/vbslp64: Likewise.
+	 * gcc.target/arm/neon/vcombinep64: Likewise.
+	 * gcc.target/arm/neon/vcreatep64: Likewise.
+	 * gcc.target/arm/neon/vdupQ_lanep64: Likewise.
+	 * gcc.target/arm/neon/vdupQ_np64: Likewise.
+	 * gcc.target/arm/neon/vdup_lanep64: Likewise.
+	 * gcc.target/arm/neon/vdup_np64: Likewise.
+	 * gcc.target/arm/neon/vextQp64: Likewise.
+	 * gcc.target/arm/neon/vextp64: Likewise.
+	 * gcc.target/arm/neon/vget_highp64: Likewise.
+	 * gcc.target/arm/neon/vget_lowp64: Likewise.
+	 * gcc.target/arm/neon/vld1Q_dupp64: Likewise.
+	 * gcc.target/arm/neon/vld1Q_lanep64: Likewise.
+	 * gcc.target/arm/neon/vld1Qp64: Likewise.
+	 * gcc.target/arm/neon/vld1_dupp64: Likewise.
+	 * gcc.target/arm/neon/vld1_lanep64: Likewise.
+	 * gcc.target/arm/neon/vld1p64: Likewise.
+	 * gcc.target/arm/neon/vld2_dupp64: Likewise.
+	 * gcc.target/arm/neon/vld2p64: Likewise.
+	 * gcc.target/arm/neon/vld3_dupp64: Likewise.
+	 * gcc.target/arm/neon/vld3p64: Likewise.
+	 * gcc.target/arm/neon/vld4_dupp64: Likewise.
+	 * gcc.target/arm/neon/vld4p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQf32_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQf32_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_f32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_p16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_p8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_s16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_s32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_s64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_s8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_u16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_u32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_u64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp128_u8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp16_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp16_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_f32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_p16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_p8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_s16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_s32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_s64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_s8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_u16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_u32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_u64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp64_u8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp8_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQp8_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs16_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs16_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs32_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs32_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs64_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs64_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs8_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQs8_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu16_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu16_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu32_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu32_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu64_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu64_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu8_p128: Likewise.
+	 * gcc.target/arm/neon/vreinterpretQu8_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretf32_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp16_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_f32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_p16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_p8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_s16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_s32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_s64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_s8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_u16: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_u32: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_u64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp64_u8: Likewise.
+	 * gcc.target/arm/neon/vreinterpretp8_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterprets16_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterprets32_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterprets64_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterprets8_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretu16_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretu32_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretu64_p64: Likewise.
+	 * gcc.target/arm/neon/vreinterpretu8_p64: Likewise.
+	 * gcc.target/arm/neon/vsliQ_np64: Likewise.
+	 * gcc.target/arm/neon/vsli_np64: Likewise.
+	 * gcc.target/arm/neon/vsriQ_np64: Likewise.
+	 * gcc.target/arm/neon/vsri_np64: Likewise.
+	 * gcc.target/arm/neon/vst1Q_lanep64: Likewise.
+	 * gcc.target/arm/neon/vst1Qp64: Likewise.
+	 * gcc.target/arm/neon/vst1_lanep64: Likewise.
+	 * gcc.target/arm/neon/vst1p64: Likewise.
+	 * gcc.target/arm/neon/vst2p64: Likewise.
+	 * gcc.target/arm/neon/vst3p64: Likewise.
+	 * gcc.target/arm/neon/vst4p64: Likewise.
+
 2013-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* lib/target-supports.exp (add_options_for_arm_crc): New procedure.
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c
new file mode 100644
index 00000000000..e0b25b93cf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b, c;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = i;
+      b[i] = 15 - i;
+    }
+  c = vaesdq_u8 (a, b);
+  return c[0];
+}
+
+/* { dg-final { scan-assembler "aesd.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c
new file mode 100644
index 00000000000..f47864662eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b, c;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = i;
+      b[i] = 15 - i;
+    }
+  c = vaeseq_u8 (a, b);
+  return c[0];
+}
+
+/* { dg-final { scan-assembler "aese.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c
new file mode 100644
index 00000000000..fbbfda609fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    a[i] = i;
+
+  b = vaesimcq_u8 (a);
+  return b[0];
+}
+
+/* { dg-final { scan-assembler "aesimc.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c
new file mode 100644
index 00000000000..cae8bd096b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    a[i] = i;
+
+  b = vaesmcq_u8 (a);
+  return b[0];
+}
+
+/* { dg-final { scan-assembler "aesmc.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c b/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c
new file mode 100644
index 00000000000..96c0e9a755a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (poly128_t* ptr)
+{
+  return vldrq_p128 (ptr);
+}
+
+/* { dg-final { scan-assembler "vld1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c b/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c
new file mode 100644
index 00000000000..1290f31a6a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (void)
+{
+  poly64x2_t a = { 0xdeadbeef, 0xadabcaca };
+  poly64x2_t b = { 0xdcdcdcdc, 0xbdbdbdbd };
+  return vmull_high_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmull.p64.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c b/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c
new file mode 100644
index 00000000000..b788dca52ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (void)
+{
+  poly64_t a = 0xdeadbeef;
+  poly64_t b = 0xadadadad;
+  return vmull_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmull.p64.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
new file mode 100644
index 00000000000..4dc9dee6617
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1cq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1c.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
new file mode 100644
index 00000000000..dee27748524
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t val = 0xdeadbeef;
+  return vsha1h_u32 (val);
+}
+
+/* { dg-final { scan-assembler "sha1h.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
new file mode 100644
index 00000000000..672b93a9747
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1mq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1m.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
new file mode 100644
index 00000000000..ff508e0dc7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1pq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1p.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c
new file mode 100644
index 00000000000..4435d1800b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1su0q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1su0.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c
new file mode 100644
index 00000000000..8610c4de269
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+
+  uint32x4_t res = vsha1su1q_u32 (a, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1su1.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c
new file mode 100644
index 00000000000..4a3e2e15835
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256h2q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256h2.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c
new file mode 100644
index 00000000000..49577f2b724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256hq_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256h.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c
new file mode 100644
index 00000000000..cc4305d38b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+
+  uint32x4_t res = vsha256su0q_u32 (a, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256su0.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c
new file mode 100644
index 00000000000..430f38adc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256su1q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256su1.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c b/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c
new file mode 100644
index 00000000000..acd8af34f66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void
+foo (poly128_t* ptr, poly128_t val)
+{
+  vstrq_p128 (ptr, val);
+}
+
+/* { dg-final { scan-assembler "vst1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
new file mode 100644
index 00000000000..519ee370d1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+  poly64x2_t arg2_poly64x2_t;
+
+  out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp64.c b/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
new file mode 100644
index 00000000000..51929274dbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+  poly64x1_t arg2_poly64x1_t;
+
+  out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
new file mode 100644
index 00000000000..d5e156bdf34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
@@ -0,0 +1,20 @@
+/* Test the `vcombinep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcombinep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
new file mode 100644
index 00000000000..7aedb73fcc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
@@ -0,0 +1,19 @@
+/* Test the `vcreatep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcreatep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly64x1_t = vcreate_p64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
new file mode 100644
index 00000000000..6211413c76c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
new file mode 100644
index 00000000000..68a1d746bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
new file mode 100644
index 00000000000..ab263f17080
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
new file mode 100644
index 00000000000..3b6b7ec312c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x1_t = vdup_n_p64 (arg0_poly64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp64.c b/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
new file mode 100644
index 00000000000..bc5e08aa783
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
@@ -0,0 +1,21 @@
+/* Test the `vextQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp64.c b/gcc/testsuite/gcc.target/arm/neon/vextp64.c
new file mode 100644
index 00000000000..aa1e91f59bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextp64.c
@@ -0,0 +1,21 @@
+/* Test the `vextp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
new file mode 100644
index 00000000000..f2b1b7a9e38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_highp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
new file mode 100644
index 00000000000..94cd3a8ab75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
new file mode 100644
index 00000000000..2d504c163ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
new file mode 100644
index 00000000000..d19267a4ff8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
new file mode 100644
index 00000000000..99ef8767321
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
new file mode 100644
index 00000000000..f2b05c5d1e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
new file mode 100644
index 00000000000..cf09f6cd641
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p64.c b/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
new file mode 100644
index 00000000000..9f182d4419f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1p64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
new file mode 100644
index 00000000000..0531a732dea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p64.c b/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
new file mode 100644
index 00000000000..0a39b37f01a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2p64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
new file mode 100644
index 00000000000..23bf88aa6d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p64.c b/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
new file mode 100644
index 00000000000..cc799289246
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3p64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
new file mode 100644
index 00000000000..bb15964af0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p64.c b/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
new file mode 100644
index 00000000000..b11fb938432
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4p64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
new file mode 100644
index 00000000000..91cac4df5c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p128 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
new file mode 100644
index 00000000000..96909f677d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p64 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
new file mode 100644
index 00000000000..aa7d2e7e7de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_f32 (void)
+{
+  poly128_t out_poly128_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
new file mode 100644
index 00000000000..94f2e9b4afa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p16 (void)
+{
+  poly128_t out_poly128_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
new file mode 100644
index 00000000000..d32007547e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p64 (void)
+{
+  poly128_t out_poly128_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
new file mode 100644
index 00000000000..112b0c6e3cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p8 (void)
+{
+  poly128_t out_poly128_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
new file mode 100644
index 00000000000..4fa06b2382b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s16 (void)
+{
+  poly128_t out_poly128_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
new file mode 100644
index 00000000000..5f17cb81309
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s32 (void)
+{
+  poly128_t out_poly128_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
new file mode 100644
index 00000000000..9b83912b979
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s64 (void)
+{
+  poly128_t out_poly128_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
new file mode 100644
index 00000000000..49e8b74b45a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s8 (void)
+{
+  poly128_t out_poly128_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
new file mode 100644
index 00000000000..d47429aeb5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u16 (void)
+{
+  poly128_t out_poly128_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
new file mode 100644
index 00000000000..57abf79a92e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u32 (void)
+{
+  poly128_t out_poly128_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
new file mode 100644
index 00000000000..4d04daaaa11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u64 (void)
+{
+  poly128_t out_poly128_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
new file mode 100644
index 00000000000..ba07bbc8ac3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u8 (void)
+{
+  poly128_t out_poly128_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
new file mode 100644
index 00000000000..27d0d0afb51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p128 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
new file mode 100644
index 00000000000..a0a3aaff49e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
new file mode 100644
index 00000000000..9f9b1a4ea1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_f32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
new file mode 100644
index 00000000000..3f712951359
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p128 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
new file mode 100644
index 00000000000..897b7cd9d00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
new file mode 100644
index 00000000000..772b268bf8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
new file mode 100644
index 00000000000..29f3f6c1cdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
new file mode 100644
index 00000000000..fae22f65ef2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
new file mode 100644
index 00000000000..8769bc8e6b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
new file mode 100644
index 00000000000..1163cc2b7c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
new file mode 100644
index 00000000000..f2b53260e03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
new file mode 100644
index 00000000000..6b6179ba41f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
new file mode 100644
index 00000000000..655ffd4fafb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
new file mode 100644
index 00000000000..40b40dd11dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
new file mode 100644
index 00000000000..b517a6fdfa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p128 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
new file mode 100644
index 00000000000..9e70b8a0756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
new file mode 100644
index 00000000000..77bfe3882ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p128 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
new file mode 100644
index 00000000000..41890f32aad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p64 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
new file mode 100644
index 00000000000..9a179ae3beb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p128 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
new file mode 100644
index 00000000000..cc7ad95ea9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p64 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
new file mode 100644
index 00000000000..adc1b9bbf0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p128 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
new file mode 100644
index 00000000000..89ab9ccb4b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p64 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
new file mode 100644
index 00000000000..d94090068e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p128 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
new file mode 100644
index 00000000000..a9adec38704
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p64 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
new file mode 100644
index 00000000000..792609246c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p128 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
new file mode 100644
index 00000000000..7a9b538f232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
new file mode 100644
index 00000000000..ce716b0ab1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p128 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
new file mode 100644
index 00000000000..a8b709e0298
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
new file mode 100644
index 00000000000..789973e0a27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p128 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
new file mode 100644
index 00000000000..38071503eaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
new file mode 100644
index 00000000000..54a832cf41c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p128 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
new file mode 100644
index 00000000000..3336e6c24e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
new file mode 100644
index 00000000000..e9714658fc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p64 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
new file mode 100644
index 00000000000..4cd6818db83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
new file mode 100644
index 00000000000..d9ecd6f88c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_f32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
new file mode 100644
index 00000000000..db437279b5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
new file mode 100644
index 00000000000..1fb0131d8d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
new file mode 100644
index 00000000000..528db2d57fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
new file mode 100644
index 00000000000..c6887d7e089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
new file mode 100644
index 00000000000..f2b04164903
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
new file mode 100644
index 00000000000..1866d19fb69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
new file mode 100644
index 00000000000..7903ec26f38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
new file mode 100644
index 00000000000..3d8e9e40f3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
new file mode 100644
index 00000000000..caa0464aac1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
new file mode 100644
index 00000000000..47e1dfa5f4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
new file mode 100644
index 00000000000..f5eff21abb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
new file mode 100644
index 00000000000..127865d169b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p64 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
new file mode 100644
index 00000000000..f8be30b9246
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p64 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
new file mode 100644
index 00000000000..5f7c17bd33e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p64 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
new file mode 100644
index 00000000000..8345963ef3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p64 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
new file mode 100644
index 00000000000..34f920bbd7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
new file mode 100644
index 00000000000..b5f24fbc4b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
new file mode 100644
index 00000000000..741912a4ebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
new file mode 100644
index 00000000000..907b67c157d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
new file mode 100644
index 00000000000..cbb47285e46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
new file mode 100644
index 00000000000..801add49be1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsli_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
new file mode 100644
index 00000000000..d2e48165aa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
new file mode 100644
index 00000000000..0abffc2e0e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsri_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
new file mode 100644
index 00000000000..74a198baf81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
new file mode 100644
index 00000000000..7d1e020f111
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
new file mode 100644
index 00000000000..f8c70c35952
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p64.c b/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
new file mode 100644
index 00000000000..7329fba9d0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_p64 (arg0_poly64_t, arg1_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p64.c b/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
new file mode 100644
index 00000000000..3ccaa5464f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst2p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x2_t arg1_poly64x1x2_t;
+
+  vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p64.c b/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
new file mode 100644
index 00000000000..73ced95448f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst3p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x3_t arg1_poly64x1x3_t;
+
+  vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p64.c b/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
new file mode 100644
index 00000000000..b9f7b168d2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst4p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x4_t arg1_poly64x1x4_t;
+
+  vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 0f9ef4c4f03..af80a698075 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2299,6 +2299,30 @@ proc check_effective_target_arm_unaligned { } {
     }]
 }
 
+# Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
+# -mfloat-abi=softfp.
+proc check_effective_target_arm_crypto_ok {} {
+    if { [check_effective_target_arm32] } {
+	return [check_no_compiler_messages arm_crypto_ok object {
+	  int foo (void)
+	  {
+	     __asm__ volatile ("aese.8 q0, q0");
+	     return 0;
+	  }
+	} "-mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"]
+    } else {
+	return 0
+    }
+}
+
+# Add options for crypto extensions.
+proc add_options_for_arm_crypto { flags } {
+    if { ! [check_effective_target_arm_crypto_ok] } {
+        return "$flags"
+    }
+    return "$flags -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"
+}
+
 # Add the options needed for NEON.  We need either -mfloat-abi=softfp
 # or -mfloat-abi=hard, but if one is already specified by the
 # multilib, use it.  Similarly, if a -mfpu option already enables