invoke.texi: Removed leading '-' from option index entries.
2007-04-24 Daniel Franke <franke.daniel@gmail.com>
* doc/invoke.texi: Removed leading '-' from option index entries.
From-SVN: r124092
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Daniel Franke
Daniel Franke
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@ -1,3 +1,7 @@
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2007-04-24 Daniel Franke <franke.daniel@gmail.com>
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* doc/invoke.texi: Removed leading '-' from option index entries.
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2007-04-23 Zdenek Dvorak <dvorakz@suse.cz>
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* tree-phinodes.c (reserve_phi_args_for_new_edge, remove_phi_node):
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@ -3016,7 +3016,7 @@ cases that are safe.
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@item -Wstrict-overflow
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@item -Wstrict-overflow=@var{n}
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@opindex -Wstrict-overflow
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@opindex Wstrict-overflow
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This option is only active when @option{-fstrict-overflow} is active.
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It warns about cases where the compiler optimizes based on the
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assumption that signed overflow does not occur. Note that it does not
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@ -5232,7 +5232,7 @@ the condition is known to be true or false.
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Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
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@item -fsplit-wide-types
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@opindex -fsplit-wide-types
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@opindex fsplit-wide-types
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When using a type that occupies multiple registers, such as @code{long
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long} on a 32-bit system, split the registers apart and allocate them
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independently. This normally generates better code for those types,
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@ -5640,7 +5640,7 @@ the loop is entered. This usually makes programs run more slowly.
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@option{-funroll-loops},
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@item -fsplit-ivs-in-unroller
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@opindex -fsplit-ivs-in-unroller
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@opindex fsplit-ivs-in-unroller
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Enables expressing of values of induction variables in later iterations
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of the unrolled loop using the value in the first iteration. This breaks
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long dependency chains, thus improving efficiency of the scheduling passes.
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@ -5653,7 +5653,7 @@ on some of the architectures due to restrictions in the CSE pass.
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This optimization is enabled by default.
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@item -fvariable-expansion-in-unroller
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@opindex -fvariable-expansion-in-unroller
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@opindex fvariable-expansion-in-unroller
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With this option, the compiler will create multiple copies of some
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local variables when unrolling a loop which can result in superior code.
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@ -8655,13 +8655,13 @@ warn about constructs contained within header files found via
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@var{dir}. This option is valid only for the C family of languages.
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@item -gused
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@opindex -gused
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@opindex gused
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Emit debugging information for symbols that are used. For STABS
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debugging format, this enables @option{-feliminate-unused-debug-symbols}.
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This is by default ON@.
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@item -gfull
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@opindex -gfull
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@opindex gfull
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Emit debugging information for all symbols and types.
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@item -mmacosx-version-min=@var{version}
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@ -8683,7 +8683,7 @@ applicable. This mode also sets @option{-mno-altivec},
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@option{-mlong-branch} for PowerPC targets.
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@item -mone-byte-bool
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@opindex -mone-byte-bool
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@opindex mone-byte-bool
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Override the defaults for @samp{bool} so that @samp{sizeof(bool)==1}.
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By default @samp{sizeof(bool)} is @samp{4} when compiling for
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Darwin/PowerPC and @samp{1} when compiling for Darwin/x86, so this
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@ -8732,12 +8732,12 @@ This option specifies the @var{executable} that will be loading the build
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output file being linked. See man ld(1) for more information.
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@item -dynamiclib
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@opindex -dynamiclib
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@opindex dynamiclib
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When passed this option, GCC will produce a dynamic library instead of
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an executable when linking, using the Darwin @file{libtool} command.
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@item -force_cpusubtype_ALL
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@opindex -force_cpusubtype_ALL
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@opindex force_cpusubtype_ALL
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This causes GCC's output file to have the @var{ALL} subtype, instead of
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one controlled by the @option{-mcpu} or @option{-march} option.
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@ -10209,7 +10209,7 @@ the file containing the CPU detection code should be compiled without
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these options.
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@item -mcx16
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@opindex -mcx16
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@opindex mcx16
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This option will enable GCC to use CMPXCHG16B instruction in generated code.
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CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword)
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data types. This is useful for high resolution counters that could be updated
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@ -10217,7 +10217,7 @@ by multiple processors (or cores). This instruction is generated as part of
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atomic built-in functions: see @ref{Atomic Builtins} for details.
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@item -msahf
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@opindex -msahf
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@opindex msahf
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This option will enable GCC to use SAHF instruction in generated 64-bit code.
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Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported
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by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and
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@ -10497,8 +10497,8 @@ to 64 bits. These are HP-UX specific flags.
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@item -mno-sched-br-data-spec
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@itemx -msched-br-data-spec
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@opindex -mno-sched-br-data-spec
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@opindex -msched-br-data-spec
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@opindex mno-sched-br-data-spec
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@opindex msched-br-data-spec
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(Dis/En)able data speculative scheduling before reload.
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This will result in generation of the ld.a instructions and
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the corresponding check instructions (ld.c / chk.a).
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@ -10506,8 +10506,8 @@ The default is 'disable'.
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@item -msched-ar-data-spec
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@itemx -mno-sched-ar-data-spec
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@opindex -msched-ar-data-spec
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@opindex -mno-sched-ar-data-spec
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@opindex msched-ar-data-spec
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@opindex mno-sched-ar-data-spec
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(En/Dis)able data speculative scheduling after reload.
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This will result in generation of the ld.a instructions and
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the corresponding check instructions (ld.c / chk.a).
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@ -10515,8 +10515,8 @@ The default is 'enable'.
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@item -mno-sched-control-spec
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@itemx -msched-control-spec
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@opindex -mno-sched-control-spec
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@opindex -msched-control-spec
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@opindex mno-sched-control-spec
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@opindex msched-control-spec
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(Dis/En)able control speculative scheduling. This feature is
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available only during region scheduling (i.e. before reload).
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This will result in generation of the ld.s instructions and
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@ -10525,8 +10525,8 @@ The default is 'disable'.
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@item -msched-br-in-data-spec
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@itemx -mno-sched-br-in-data-spec
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@opindex -msched-br-in-data-spec
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@opindex -mno-sched-br-in-data-spec
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@opindex msched-br-in-data-spec
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@opindex mno-sched-br-in-data-spec
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(En/Dis)able speculative scheduling of the instructions that
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are dependent on the data speculative loads before reload.
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This is effective only with @option{-msched-br-data-spec} enabled.
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@ -10534,8 +10534,8 @@ The default is 'enable'.
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@item -msched-ar-in-data-spec
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@itemx -mno-sched-ar-in-data-spec
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@opindex -msched-ar-in-data-spec
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@opindex -mno-sched-ar-in-data-spec
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@opindex msched-ar-in-data-spec
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@opindex mno-sched-ar-in-data-spec
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(En/Dis)able speculative scheduling of the instructions that
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are dependent on the data speculative loads after reload.
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This is effective only with @option{-msched-ar-data-spec} enabled.
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@ -10543,8 +10543,8 @@ The default is 'enable'.
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@item -msched-in-control-spec
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@itemx -mno-sched-in-control-spec
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@opindex -msched-in-control-spec
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@opindex -mno-sched-in-control-spec
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@opindex msched-in-control-spec
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@opindex mno-sched-in-control-spec
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(En/Dis)able speculative scheduling of the instructions that
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are dependent on the control speculative loads.
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This is effective only with @option{-msched-control-spec} enabled.
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@ -10552,8 +10552,8 @@ The default is 'enable'.
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@item -msched-ldc
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@itemx -mno-sched-ldc
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@opindex -msched-ldc
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@opindex -mno-sched-ldc
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@opindex msched-ldc
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@opindex mno-sched-ldc
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(En/Dis)able use of simple data speculation checks ld.c .
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If disabled, only chk.a instructions will be emitted to check
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data speculative loads.
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@ -10561,8 +10561,8 @@ The default is 'enable'.
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@item -mno-sched-control-ldc
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@itemx -msched-control-ldc
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@opindex -mno-sched-control-ldc
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@opindex -msched-control-ldc
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@opindex mno-sched-control-ldc
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@opindex msched-control-ldc
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(Dis/En)able use of ld.c instructions to check control speculative loads.
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If enabled, in case of control speculative load with no speculatively
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scheduled dependent instructions this load will be emitted as ld.sa and
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@ -10571,14 +10571,14 @@ The default is 'disable'.
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@item -mno-sched-spec-verbose
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@itemx -msched-spec-verbose
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@opindex -mno-sched-spec-verbose
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@opindex -msched-spec-verbose
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@opindex mno-sched-spec-verbose
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@opindex msched-spec-verbose
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(Dis/En)able printing of the information about speculative motions.
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@item -mno-sched-prefer-non-data-spec-insns
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@itemx -msched-prefer-non-data-spec-insns
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@opindex -mno-sched-prefer-non-data-spec-insns
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@opindex -msched-prefer-non-data-spec-insns
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@opindex mno-sched-prefer-non-data-spec-insns
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@opindex msched-prefer-non-data-spec-insns
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If enabled, data speculative instructions will be chosen for schedule
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only if there are no other choices at the moment. This will make
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the use of the data speculation much more conservative.
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@ -10586,8 +10586,8 @@ The default is 'disable'.
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@item -mno-sched-prefer-non-control-spec-insns
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@itemx -msched-prefer-non-control-spec-insns
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@opindex -mno-sched-prefer-non-control-spec-insns
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@opindex -msched-prefer-non-control-spec-insns
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@opindex mno-sched-prefer-non-control-spec-insns
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@opindex msched-prefer-non-control-spec-insns
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If enabled, control speculative instructions will be chosen for schedule
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only if there are no other choices at the moment. This will make
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the use of the control speculation much more conservative.
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@ -10595,8 +10595,8 @@ The default is 'disable'.
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@item -mno-sched-count-spec-in-critical-path
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@itemx -msched-count-spec-in-critical-path
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@opindex -mno-sched-count-spec-in-critical-path
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@opindex -msched-count-spec-in-critical-path
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@opindex mno-sched-count-spec-in-critical-path
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@opindex msched-count-spec-in-critical-path
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If enabled, speculative dependencies will be considered during
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computation of the instructions priorities. This will make the use of the
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speculation a bit more conservative.
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@ -11007,7 +11007,7 @@ Additionally, parameters passed on the stack are also aligned to a
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16-bit boundary even on targets whose API mandates promotion to 32-bit.
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@item -mno-short
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@opindex -mno-short
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@opindex mno-short
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Do not consider type @code{int} to be 16 bits wide. This is the default.
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@item -mnobitfield
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@ -13025,15 +13025,15 @@ These options are defined for Score implementations:
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Compile code for big endian mode. This is the default.
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@item -mel
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@opindex -mel
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@opindex mel
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Compile code for little endian mode.
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@item -mnhwloop
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@opindex -mnhwloop
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@opindex mnhwloop
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Disable generate bcnz instruction.
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@item -muls
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@opindex -muls
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@opindex muls
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Enable generate unaligned load and store instruction.
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@item -mmac
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