backport: re PR target/81305 ([avr] avrtiny uses LDS for SREG in ISR routines which is out of range of LDS.)
gcc/ Backport from 2017-07-05 trunk r249995. PR target/81305 * config/avr/avr.c (avr_out_movhi_mr_r_xmega) [CONSTANT_ADDRESS_P]: Don't depend on "optimize > 0". (out_movhi_r_mr, out_movqi_mr_r): Same. (out_movhi_mr_r, out_movqi_r_mr): Same. (avr_address_cost) [CONSTANT_ADDRESS_P]: Don't depend cost for io_address_operand on "optimize > 0". gcc/testsuite/ Backport from 2017-07-05 trunk r249995, r249996. PR target/81305 * gcc.target/avr/isr-test.h: New file. * gcc.target/avr/torture/isr-01-simple.c: New test. * gcc.target/avr/torture/isr-02-call.c: New test. * gcc.target/avr/torture/isr-03-fixed.c: New test. From-SVN: r249998
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
7a4cadf3b6
commit
edfd992166
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@ -1,3 +1,15 @@
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2017-07-05 Georg-Johann Lay <avr@gjlay.de>
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Backport from 2017-07-05 trunk r249995.
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PR target/81305
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* config/avr/avr.c (avr_out_movhi_mr_r_xmega) [CONSTANT_ADDRESS_P]:
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Don't depend on "optimize > 0".
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(out_movhi_r_mr, out_movqi_mr_r): Same.
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(out_movhi_mr_r, out_movqi_r_mr): Same.
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(avr_address_cost) [CONSTANT_ADDRESS_P]: Don't depend cost for
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io_address_operand on "optimize > 0".
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2017-07-04 Uros Bizjak <ubizjak@gmail.com>
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PR target/81300
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@ -3820,7 +3820,7 @@ out_movqi_r_mr (rtx_insn *insn, rtx op[], int *plen)
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if (CONSTANT_ADDRESS_P (x))
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{
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int n_words = AVR_TINY ? 1 : 2;
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return optimize > 0 && io_address_operand (x, QImode)
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return io_address_operand (x, QImode)
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? avr_asm_len ("in %0,%i1", op, plen, -1)
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: avr_asm_len ("lds %0,%m1", op, plen, -n_words);
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}
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@ -4088,7 +4088,7 @@ out_movhi_r_mr (rtx_insn *insn, rtx op[], int *plen)
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else if (CONSTANT_ADDRESS_P (base))
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{
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int n_words = AVR_TINY ? 2 : 4;
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return optimize > 0 && io_address_operand (base, HImode)
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return io_address_operand (base, HImode)
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? avr_asm_len ("in %A0,%i1" CR_TAB
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"in %B0,%i1+1", op, plen, -2)
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@ -5215,7 +5215,7 @@ out_movqi_mr_r (rtx_insn *insn, rtx op[], int *plen)
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if (CONSTANT_ADDRESS_P (x))
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{
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int n_words = AVR_TINY ? 1 : 2;
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return optimize > 0 && io_address_operand (x, QImode)
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return io_address_operand (x, QImode)
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? avr_asm_len ("out %i0,%1", op, plen, -1)
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: avr_asm_len ("sts %m0,%1", op, plen, -n_words);
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}
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@ -5291,13 +5291,12 @@ avr_out_movhi_mr_r_xmega (rtx_insn *insn, rtx op[], int *plen)
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if (CONSTANT_ADDRESS_P (base))
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{
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int n_words = AVR_TINY ? 2 : 4;
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return optimize > 0 && io_address_operand (base, HImode)
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return io_address_operand (base, HImode)
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? avr_asm_len ("out %i0,%A1" CR_TAB
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"out %i0+1,%B1", op, plen, -2)
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: avr_asm_len ("sts %m0,%A1" CR_TAB
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"sts %m0+1,%B1", op, plen, -n_words);
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"sts %m0+1,%B1", op, plen, -4);
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}
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if (reg_base > 0)
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@ -5477,7 +5476,7 @@ out_movhi_mr_r (rtx_insn *insn, rtx op[], int *plen)
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if (CONSTANT_ADDRESS_P (base))
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{
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int n_words = AVR_TINY ? 2 : 4;
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return optimize > 0 && io_address_operand (base, HImode)
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return io_address_operand (base, HImode)
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? avr_asm_len ("out %i0+1,%B1" CR_TAB
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"out %i0,%A1", op, plen, -2)
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@ -11361,8 +11360,7 @@ avr_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED,
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}
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else if (CONSTANT_ADDRESS_P (x))
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{
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if (optimize > 0
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&& io_address_operand (x, QImode))
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if (io_address_operand (x, QImode))
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cost = 2;
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if (AVR_TINY
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@ -1,3 +1,13 @@
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2017-07-05 Georg-Johann Lay <avr@gjlay.de>
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Backport from 2017-07-05 trunk r249995, r249996.
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PR target/81305
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* gcc.target/avr/isr-test.h: New file.
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* gcc.target/avr/torture/isr-01-simple.c: New test.
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* gcc.target/avr/torture/isr-02-call.c: New test.
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* gcc.target/avr/torture/isr-03-fixed.c: New test.
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2017-07-04 Uros Bizjak <ubizjak@gmail.com>
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PR target/81300
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@ -0,0 +1,282 @@
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#ifndef ISR_TEST_H
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#define ISR_TEST_H
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#include <string.h>
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#define ISR(N,...) \
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__attribute__ ((used, externally_visible , ## __VA_ARGS__)) \
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void __vector_##N (void); \
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void __vector_##N (void)
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#define SFR(ADDR) (*(unsigned char volatile*) (__AVR_SFR_OFFSET__ + (ADDR)))
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#define CORE_SFRS SFR (0x38)
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#define SREG SFR (0x3F)
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#define SPL SFR (0x3D)
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#define EIND SFR (0x3C)
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#define RAMPZ SFR (0x3B)
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#define RAMPY SFR (0x3A)
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#define RAMPX SFR (0x39)
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#define RAMPD SFR (0x38)
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#ifdef __AVR_HAVE_JMP_CALL__
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#define VEC_SIZE 4
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#else
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#define VEC_SIZE 2
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#endif
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#ifdef __AVR_TINY__
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#define FIRST_REG 16
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#else
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#define FIRST_REG 0
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#endif
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#define CR "\n\t"
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typedef struct
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{
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unsigned char sfrs[8];
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unsigned char gprs[32 - FIRST_REG];
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} regs_t;
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regs_t reginfo1, reginfo2;
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__attribute__((noinline))
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static void clear_reginfo (void)
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{
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memset (reginfo1.sfrs, 0, sizeof (reginfo1.sfrs));
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memset (reginfo2.sfrs, 0, sizeof (reginfo2.sfrs));
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}
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__attribute__((noinline))
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static void compare_reginfo (unsigned long gpr_ignore)
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{
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signed char regno;
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const unsigned char *preg1 = ®info1.gprs[0];
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const unsigned char *preg2 = ®info2.gprs[0];
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if (memcmp (®info1, ®info2, 8))
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__builtin_abort();
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gpr_ignore >>= FIRST_REG;
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for (regno = FIRST_REG; regno < 32;
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regno++, preg1++, preg2++, gpr_ignore >>= 1)
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{
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if (gpr_ignore & 1)
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continue;
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if (*preg1 != *preg2)
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{
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static signed char volatile failed_regno;
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failed_regno = regno;
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__builtin_abort();
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}
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}
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}
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/* STore GPR */
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#define ST(regno,M) \
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CR "sts %[" #M "]+8-%[first]+" #regno ", r" #regno
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/* STore SFR */
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#define ST_SFR(sfr, n_sfr, M) \
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CR "in __tmp_reg__,%i[s_" #sfr "]" \
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CR "sts %[" #M "]+" #n_sfr ", __tmp_reg__"
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/* Named asm OPerand for SFR */
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#define OP_SFR(sfr) \
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, [s_ ## sfr] "n" (&(sfr))
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/* Write funny value to SFR */
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#define XX_SFR(sfr) \
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CR "dec r31 $ out %i[s_" #sfr "], r31"
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/* Write 0 to SFR */
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#define OO_SFR(sfr) \
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CR "out %i[s_" #sfr "], __zero_reg__"
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/* Macros for SREG */
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#define ST_SREG(M) ST_SFR (SREG,0,M)
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#define OP_SREG OP_SFR (SREG)
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#define XX_SREG XX_SFR (SREG)
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/* Macros for EIND */
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#if defined __AVR_HAVE_EIJMP_EICALL__
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#define ST_EIND(M) ST_SFR (EIND,1,M)
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#define OP_EIND OP_SFR (EIND)
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#else
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#define ST_EIND(M) /* empty */
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#define OP_EIND /* empty */
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#endif
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/* Macros for RAMPX */
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#if defined (__AVR_HAVE_RAMPX__)
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#define ST_RAMPX(M) ST_SFR (RAMPX,2,M)
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#define OP_RAMPX OP_SFR (RAMPX)
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#define XX_RAMPX XX_SFR (RAMPX)
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#define OO_RAMPX OO_SFR (RAMPX)
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#else
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#define ST_RAMPX(M) /* empty */
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#define OP_RAMPX /* empty */
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#define XX_RAMPX /* empty */
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#define OO_RAMPX /* empty */
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#endif
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/* Macros for RAMPY */
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#if defined (__AVR_HAVE_RAMPY__)
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#define ST_RAMPY(M) ST_SFR (RAMPY,3,M)
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#define OP_RAMPY OP_SFR (RAMPY)
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#define XX_RAMPY XX_SFR (RAMPY)
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#define OO_RAMPY OO_SFR (RAMPY)
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#else
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#define ST_RAMPY(M) /* empty */
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#define OP_RAMPY /* empty */
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#define XX_RAMPY /* empty */
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#define OO_RAMPY /* empty */
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#endif
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/* Macros for RAMPZ */
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#if defined (__AVR_HAVE_RAMPZ__)
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#define ST_RAMPZ(M) ST_SFR (RAMPZ,4,M)
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#define OP_RAMPZ OP_SFR (RAMPZ)
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#define XX_RAMPZ XX_SFR (RAMPZ)
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#define OO_RAMPZ OO_SFR (RAMPZ)
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#else
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#define ST_RAMPZ(M) /* empty */
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#define OP_RAMPZ /* empty */
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#define XX_RAMPZ /* empty */
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#define OO_RAMPZ /* empty */
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#endif
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/* Macros for RAMPD */
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#if defined (__AVR_HAVE_RAMPD__)
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#define ST_RAMPD(M) ST_SFR (RAMPD,5,M)
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#define OP_RAMPD OP_SFR (RAMPD)
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#else
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#define ST_RAMPD(M) /* empty */
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#define OP_RAMPD /* empty */
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#endif
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/* Macros for all GPRs */
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#if defined __AVR_TINY__
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#define ST_REGS_LO(M) /* empty */
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#else
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#define ST_REGS_LO(M) \
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ST(0,M) ST(1,M) ST(2,M) ST(3,M) \
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ST(4,M) ST(5,M) ST(6,M) ST(7,M) \
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ST(8,M) ST(9,M) ST(10,M) ST(11,M) \
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ST(12,M) ST(13,M) ST(14,M) ST(15,M)
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#endif /* AVR_TINY */
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#define ST_REGS_HI(M) \
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ST(16,M) ST(17,M) ST(18,M) ST(19,M) \
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ST(20,M) ST(21,M) ST(22,M) ST(23,M) \
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ST(24,M) ST(25,M) ST(26,M) ST(27,M) \
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ST(28,M) ST(29,M) ST(30,M) ST(31,M)
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__attribute__((used,naked,noinline,noclone))
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static void host_store1 (void)
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{
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__asm __volatile__
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("nop"
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CR ".global do_stores_before"
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CR ".type do_stores_before,@function"
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CR "do_stores_before:"
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/* Funny values to some SFRs */
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CR "ldi r31, 1 + 'Z'"
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XX_RAMPZ
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XX_RAMPY
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XX_RAMPX
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CR "dec __zero_reg__"
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CR "clr r31"
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XX_SREG
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/* Must set I-flag due to RETI of ISR */
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CR "sei"
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/* Store core regs before ISR */
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ST_RAMPX (mem1)
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ST_RAMPY (mem1)
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ST_RAMPZ (mem1)
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ST_RAMPD (mem1)
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ST_EIND (mem1)
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ST_SREG (mem1)
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CR "ldi r31, 0xaa"
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CR "mov __tmp_reg__, r31"
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CR "ldi r31, 31"
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ST_REGS_LO (mem1)
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ST_REGS_HI (mem1)
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CR "ret"
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: /* No outputs */
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: [mem1] "i" (®info1), [first] "n" (FIRST_REG)
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OP_RAMPX
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OP_RAMPY
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OP_RAMPZ
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OP_RAMPD
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OP_EIND
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OP_SREG
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: "memory", "r31");
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}
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__attribute__((used,naked,noinline,noclone))
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static void host_store2 (void)
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{
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__asm __volatile__
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("nop"
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CR ".global do_stores_after"
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CR ".type do_stores_after,@function"
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CR "do_stores_after:"
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/* Store core regs after ISR */
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ST_REGS_LO (mem2)
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ST_REGS_HI (mem2)
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ST_RAMPX (mem2)
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ST_RAMPY (mem2)
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ST_RAMPZ (mem2)
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ST_RAMPD (mem2)
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ST_EIND (mem2)
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ST_SREG (mem2)
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/* Undo funny values */
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CR "clr __zero_reg__"
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OO_RAMPX
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OO_RAMPY
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OO_RAMPZ
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CR "ret"
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: /* No outputs */
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: [mem2] "i" (®info2), [first] "n" (FIRST_REG)
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OP_RAMPX
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OP_RAMPY
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OP_RAMPZ
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OP_RAMPD
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OP_EIND
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OP_SREG
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: "memory");
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}
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#define MK_CALL_ISR(vecno) \
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__asm __volatile__ \
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(/* Funny values to some SFRs */ \
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/* Must set I-flag due to RETI of ISR */ \
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/* Store core regs before ISR */ \
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CR "%~call do_stores_before" \
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/* Execute ISR */ \
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CR "%~call __vectors + %[vect]" \
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/* Store core regs after ISR */ \
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/* Undo funny values */ \
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CR "%~call do_stores_after" \
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: /* No outputs */ \
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: [vect] "i" (VEC_SIZE * (vecno)) \
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, "i" (host_store1) \
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, "i" (host_store2) \
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: "memory", "r31")
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#define MK_RUN_ISR(N, IGMSK) \
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\
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__attribute__((noinline,noclone)) \
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void run_isr_ ## N (void) \
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{ \
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clear_reginfo(); \
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MK_CALL_ISR (N); \
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compare_reginfo (IGMSK); \
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}
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#endif /* ISR_TEST_H */
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@ -0,0 +1,98 @@
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/* { dg-do run } */
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/* { dg-options "-std=c99" } */
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#include "../isr-test.h"
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int volatile v;
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/**********************************************************************/
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ISR (1, signal)
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{
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}
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MK_RUN_ISR (1, 0)
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void test1 (void)
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{
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run_isr_1();
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}
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/**********************************************************************/
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ISR (2, signal)
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{
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v++;
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}
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MK_RUN_ISR (2, 0)
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void test2 (void)
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{
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v = 0;
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run_isr_2();
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if (v != 1)
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__builtin_abort();
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}
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/**********************************************************************/
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ISR (3, signal)
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{
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__asm __volatile__ ("$ lds r27, v"
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"$ swap r27"
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"$ sts v, r27"
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::: "memory", "r27");
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}
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MK_RUN_ISR (3, 0)
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void test3 (void)
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{
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run_isr_3();
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if (v != 0x10)
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__builtin_abort();
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}
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ISR (4, signal)
|
||||
{
|
||||
__asm __volatile__ ("sts v,__zero_reg__" ::: "memory");
|
||||
}
|
||||
|
||||
MK_RUN_ISR (4, 0)
|
||||
|
||||
void test4 (void)
|
||||
{
|
||||
run_isr_4();
|
||||
if (v != 0)
|
||||
__builtin_abort();
|
||||
}
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ISR (5, signal)
|
||||
{
|
||||
__asm __volatile__ ("clt");
|
||||
}
|
||||
|
||||
MK_RUN_ISR (5, 0)
|
||||
|
||||
void test5 (void)
|
||||
{
|
||||
run_isr_5();
|
||||
}
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
int main (void)
|
||||
{
|
||||
test1();
|
||||
test2();
|
||||
test3();
|
||||
test4();
|
||||
test5();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-std=c99" } */
|
||||
|
||||
#include "../isr-test.h"
|
||||
|
||||
int volatile v;
|
||||
|
||||
__attribute__((noinline,noclone))
|
||||
void inc_v (void)
|
||||
{
|
||||
v++;
|
||||
}
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ISR (1, signal)
|
||||
{
|
||||
inc_v();
|
||||
}
|
||||
|
||||
MK_RUN_ISR (1, 0)
|
||||
|
||||
void test1 (void)
|
||||
{
|
||||
run_isr_1();
|
||||
if (v != 1)
|
||||
__builtin_abort();
|
||||
}
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ISR (2, signal)
|
||||
{
|
||||
if (v == 1)
|
||||
inc_v();
|
||||
else
|
||||
v += 2;
|
||||
}
|
||||
|
||||
MK_RUN_ISR (2, 0)
|
||||
|
||||
void test2 (void)
|
||||
{
|
||||
run_isr_2();
|
||||
if (v != 2)
|
||||
__builtin_abort();
|
||||
run_isr_2();
|
||||
if (v != 4)
|
||||
__builtin_abort();
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
int main (void)
|
||||
{
|
||||
test1();
|
||||
test2();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-std=gnu99 -fno-lto -fno-toplevel-reorder" } */
|
||||
|
||||
// No LTO for now due to PR lto/68384.
|
||||
|
||||
#ifdef __AVR_TINY__
|
||||
unsigned char reg2;
|
||||
#else
|
||||
register unsigned char reg2 __asm("r2");
|
||||
#endif
|
||||
|
||||
#include "../isr-test.h"
|
||||
|
||||
#define SET_REG(reg,val) \
|
||||
do { \
|
||||
reg = (val); \
|
||||
__asm __volatile__("" : "+r" (reg)); \
|
||||
} while (0) \
|
||||
|
||||
#define GET_REG(reg) \
|
||||
({ \
|
||||
__asm __volatile__("" : "+r" (reg)); \
|
||||
reg; \
|
||||
})
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ISR (1, signal)
|
||||
{
|
||||
reg2++;
|
||||
}
|
||||
|
||||
MK_RUN_ISR (1, 1ul << 2)
|
||||
|
||||
void test1 (void)
|
||||
{
|
||||
SET_REG (reg2, 0);
|
||||
run_isr_1();
|
||||
if (GET_REG (reg2) != 1)
|
||||
__builtin_abort();
|
||||
}
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
__attribute__((noinline,noclone))
|
||||
void inc_r2 (void)
|
||||
{
|
||||
reg2++;
|
||||
}
|
||||
|
||||
ISR (2, signal)
|
||||
{
|
||||
inc_r2 ();
|
||||
}
|
||||
|
||||
MK_RUN_ISR (2, 1ul << 2)
|
||||
|
||||
void test2 (void)
|
||||
{
|
||||
run_isr_2();
|
||||
if (GET_REG (reg2) != 2)
|
||||
__builtin_abort();
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
ISR (3, signal)
|
||||
{
|
||||
#ifndef __AVR_TINY__
|
||||
register char r4 __asm ("r4");
|
||||
__asm __volatile ("inc %0" : "+r" (r4));
|
||||
__asm __volatile ("inc r5" ::: "r5");
|
||||
#endif
|
||||
}
|
||||
|
||||
MK_RUN_ISR (3, 0)
|
||||
|
||||
void test3 (void)
|
||||
{
|
||||
run_isr_3();
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
#define CLOBB(reg) \
|
||||
do { \
|
||||
__asm __volatile__ ("inc " #reg ::: #reg); \
|
||||
} while (0)
|
||||
|
||||
ISR (4, signal)
|
||||
{
|
||||
char volatile v;
|
||||
v = 1;
|
||||
|
||||
#ifndef __AVR_TINY__
|
||||
CLOBB (r3);
|
||||
CLOBB (r4);
|
||||
CLOBB (r5);
|
||||
CLOBB (r6);
|
||||
CLOBB (r7);
|
||||
CLOBB (r8);
|
||||
CLOBB (r9);
|
||||
CLOBB (r10);
|
||||
CLOBB (r11);
|
||||
CLOBB (r12);
|
||||
CLOBB (r13);
|
||||
CLOBB (r14);
|
||||
CLOBB (r15);
|
||||
CLOBB (r16);
|
||||
CLOBB (r17);
|
||||
#endif
|
||||
|
||||
CLOBB (r18);
|
||||
CLOBB (r19);
|
||||
CLOBB (r20);
|
||||
CLOBB (r21);
|
||||
CLOBB (r22);
|
||||
CLOBB (r23);
|
||||
CLOBB (r24);
|
||||
CLOBB (r25);
|
||||
CLOBB (r26);
|
||||
CLOBB (r27);
|
||||
CLOBB (r30);
|
||||
CLOBB (r31);
|
||||
}
|
||||
|
||||
MK_RUN_ISR (4, 0)
|
||||
|
||||
void test4 (void)
|
||||
{
|
||||
run_isr_4();
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
int main (void)
|
||||
{
|
||||
test1();
|
||||
test2();
|
||||
test3();
|
||||
test4();
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue