Add qdf24xx base tuning support.
gcc/ * config/aarch64/aarch64-cores.def (qdf24xx): Use qdf24xx tuning. * config/aarch64/aarch64.c (qdf24xx_addrcost_table, qdf24xx_regmove_cost, qdf24xx_tunings): New. * config/arm/aarch64-cost-tables.h (qdf24xx_extra_costs): New. * config/arm/arm-cores.def (qdf24xx): Use qdf24xx tuning. * config/arm/arm.c (arm_qdf24xx_tune): New. gcc/testsuite/ * gcc.dg/asr_div1.c: Add aarch64 specific dg-options. From-SVN: r237857
This commit is contained in:
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27f6746184
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ee446d9fbb
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@ -1,3 +1,12 @@
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2016-06-29 Jim Wilson <jim.wilson@linaro.org>
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* config/aarch64/aarch64-cores.def (qdf24xx): Use qdf24xx tuning.
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* config/aarch64/aarch64.c (qdf24xx_addrcost_table,
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qdf24xx_regmove_cost, qdf24xx_tunings): New.
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* config/arm/aarch64-cost-tables.h (qdf24xx_extra_costs): New.
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* config/arm/arm-cores.def (qdf24xx): Use qdf24xx tuning.
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* config/arm/arm.c (arm_qdf24xx_tune): New.
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2016-06-29 Wilco Dijkstra <wdijkstr@arm.com>
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* config/aarch64/aarch64.c (cortexa53_tunings):
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@ -46,7 +46,7 @@ AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AA
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AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")
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AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09")
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AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, "0x53", "0x001")
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AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x51", "0x800")
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AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, "0x51", "0x800")
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AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, "0x43", "0x0a1")
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AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
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@ -250,6 +250,22 @@ static const struct cpu_addrcost_table xgene1_addrcost_table =
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0, /* imm_offset */
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};
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static const struct cpu_addrcost_table qdf24xx_addrcost_table =
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{
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{
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1, /* hi */
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0, /* si */
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0, /* di */
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1, /* ti */
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},
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0, /* pre_modify */
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0, /* post_modify */
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0, /* register_offset */
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0, /* register_sextend */
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0, /* register_zextend */
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0 /* imm_offset */
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};
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static const struct cpu_regmove_cost generic_regmove_cost =
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{
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1, /* GP2GP */
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@ -308,6 +324,15 @@ static const struct cpu_regmove_cost xgene1_regmove_cost =
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2 /* FP2FP */
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};
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static const struct cpu_regmove_cost qdf24xx_regmove_cost =
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{
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2, /* GP2GP */
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/* Avoid the use of int<->fp moves for spilling. */
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6, /* GP2FP */
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6, /* FP2GP */
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4 /* FP2FP */
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};
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/* Generic costs for vector insn classes. */
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static const struct cpu_vector_cost generic_vector_cost =
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{
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@ -647,6 +672,32 @@ static const struct tune_params xgene1_tunings =
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(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
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};
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static const struct tune_params qdf24xx_tunings =
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{
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&qdf24xx_extra_costs,
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&qdf24xx_addrcost_table,
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&qdf24xx_regmove_cost,
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&generic_vector_cost,
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&generic_branch_cost,
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&generic_approx_modes,
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4, /* memmov_cost */
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4, /* issue_rate */
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(AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
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| AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */
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16, /* function_align. */
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8, /* jump_align. */
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16, /* loop_align. */
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2, /* int_reassoc_width. */
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4, /* fp_reassoc_width. */
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1, /* vec_reassoc_width. */
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2, /* min_div_recip_mul_sf. */
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2, /* min_div_recip_mul_df. */
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0, /* max_case_values. */
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64, /* cache_line_size. */
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tune_params::AUTOPREFETCHER_STRONG, /* autoprefetcher_model. */
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(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
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};
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/* Support for fine-grained override of the tuning structures. */
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struct aarch64_tuning_override_function
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{
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@ -537,4 +537,107 @@ const struct cpu_cost_table xgene1_extra_costs =
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}
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};
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const struct cpu_cost_table qdf24xx_extra_costs =
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{
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/* ALU */
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{
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0, /* arith. */
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0, /* logical. */
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0, /* shift. */
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0, /* shift_reg. */
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COSTS_N_INSNS (1), /* arith_shift. */
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COSTS_N_INSNS (1), /* arith_shift_reg. */
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0, /* log_shift. */
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0, /* log_shift_reg. */
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0, /* extend. */
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0, /* extend_arith. */
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0, /* bfi. */
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0, /* bfx. */
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0, /* clz. */
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0, /* rev. */
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0, /* non_exec. */
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true /* non_exec_costs_exec. */
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},
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{
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/* MULT SImode */
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{
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COSTS_N_INSNS (2), /* simple. */
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COSTS_N_INSNS (2), /* flag_setting. */
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COSTS_N_INSNS (2), /* extend. */
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COSTS_N_INSNS (2), /* add. */
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COSTS_N_INSNS (2), /* extend_add. */
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COSTS_N_INSNS (4) /* idiv. */
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},
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/* MULT DImode */
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{
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COSTS_N_INSNS (3), /* simple. */
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0, /* flag_setting (N/A). */
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COSTS_N_INSNS (3), /* extend. */
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COSTS_N_INSNS (3), /* add. */
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COSTS_N_INSNS (3), /* extend_add. */
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COSTS_N_INSNS (9) /* idiv. */
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}
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},
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/* LD/ST */
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{
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COSTS_N_INSNS (2), /* load. */
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COSTS_N_INSNS (2), /* load_sign_extend. */
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COSTS_N_INSNS (2), /* ldrd. */
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COSTS_N_INSNS (2), /* ldm_1st. */
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1, /* ldm_regs_per_insn_1st. */
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2, /* ldm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (2), /* loadf. */
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COSTS_N_INSNS (2), /* loadd. */
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COSTS_N_INSNS (3), /* load_unaligned. */
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0, /* store. */
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0, /* strd. */
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0, /* stm_1st. */
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1, /* stm_regs_per_insn_1st. */
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2, /* stm_regs_per_insn_subsequent. */
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0, /* storef. */
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0, /* stored. */
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COSTS_N_INSNS (1), /* store_unaligned. */
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COSTS_N_INSNS (1), /* loadv. */
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COSTS_N_INSNS (1) /* storev. */
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},
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{
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/* FP SFmode */
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{
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COSTS_N_INSNS (6), /* div. */
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COSTS_N_INSNS (5), /* mult. */
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COSTS_N_INSNS (5), /* mult_addsub. */
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COSTS_N_INSNS (5), /* fma. */
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COSTS_N_INSNS (3), /* addsub. */
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COSTS_N_INSNS (1), /* fpconst. */
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COSTS_N_INSNS (1), /* neg. */
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COSTS_N_INSNS (2), /* compare. */
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COSTS_N_INSNS (4), /* widen. */
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COSTS_N_INSNS (4), /* narrow. */
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COSTS_N_INSNS (4), /* toint. */
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COSTS_N_INSNS (4), /* fromint. */
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COSTS_N_INSNS (2) /* roundint. */
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},
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/* FP DFmode */
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{
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COSTS_N_INSNS (11), /* div. */
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COSTS_N_INSNS (6), /* mult. */
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COSTS_N_INSNS (6), /* mult_addsub. */
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COSTS_N_INSNS (6), /* fma. */
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COSTS_N_INSNS (3), /* addsub. */
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COSTS_N_INSNS (1), /* fpconst. */
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COSTS_N_INSNS (1), /* neg. */
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COSTS_N_INSNS (2), /* compare. */
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COSTS_N_INSNS (4), /* widen. */
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COSTS_N_INSNS (4), /* narrow. */
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COSTS_N_INSNS (4), /* toint. */
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COSTS_N_INSNS (4), /* fromint. */
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COSTS_N_INSNS (2) /* roundint. */
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}
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},
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/* Vector */
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{
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COSTS_N_INSNS (1) /* alu. */
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}
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};
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#endif /* GCC_AARCH_COST_TABLES_H */
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@ -173,7 +173,7 @@ ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED
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ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
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ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
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ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
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ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
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ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
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ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1)
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/* V8 big.LITTLE implementations */
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@ -2052,6 +2052,29 @@ const struct tune_params arm_xgene1_tune =
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tune_params::SCHED_AUTOPREF_OFF
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};
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const struct tune_params arm_qdf24xx_tune =
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{
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arm_9e_rtx_costs,
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&qdf24xx_extra_costs,
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NULL, /* Scheduler cost adjustment. */
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arm_default_branch_cost,
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&arm_default_vec_cost, /* Vectorizer costs. */
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1, /* Constant limit. */
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2, /* Max cond insns. */
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8, /* Memset max inline. */
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4, /* Issue rate. */
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ARM_PREFETCH_BENEFICIAL (0, -1, 64),
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tune_params::PREF_CONST_POOL_FALSE,
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tune_params::PREF_LDRD_TRUE,
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tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */
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tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */
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tune_params::DISPARAGE_FLAGS_ALL,
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tune_params::PREF_NEON_64_FALSE,
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tune_params::PREF_NEON_STRINGOPS_TRUE,
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FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
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tune_params::SCHED_AUTOPREF_FULL
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};
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/* Branches can be dual-issued on Cortex-A5, so conditional execution is
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less appealing. Set max_insns_skipped to a low value. */
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@ -1,3 +1,7 @@
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2016-06-29 Jim Wilson <jim.wilson@linaro.org>
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* gcc.dg/asr_div1.c: Add aarch64 specific dg-options.
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2016-06-29 Cesar Philippidis <cesar@codesourcery.com>
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* gfortran.dg/goacc/asyncwait-2.f95: Updated expected diagnostics.
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@ -1,6 +1,7 @@
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/* Test division by const int generates only one shift. */
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/* { dg-do run } */
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/* { dg-options "-O2 -fdump-rtl-combine-all" } */
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/* { dg-options "-O2 -fdump-rtl-combine-all -mtune=cortex-a53" { target aarch64*-*-* } } */
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/* { dg-require-effective-target int32plus } */
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extern void abort (void);
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