sse.md (*vec_concatv2sf_sse4_1): Do not allow both input operands in memory.
* config/i386/sse.md (*vec_concatv2sf_sse4_1): Do not allow both input operands in memory. (*vec_concatv2si_sse4_1): Ditto. (*vec_concatv2df): Ditto, except for SSE3 and equal input operands. (vec_extract_lo_<mode><mask_name>): Change operand 1 predicate to register_operand. (vec_extract_hi_v32hi): Ditto. (vec_extract_hi_v64hi): Ditto. (<mask_codefor>avx512f_unpckhpd512<mask_name>): Ditto. From-SVN: r222400
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@ -1,3 +1,15 @@
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2015-04-24 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (*vec_concatv2sf_sse4_1): Do not allow both
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input operands in memory.
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(*vec_concatv2si_sse4_1): Ditto.
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(*vec_concatv2df): Ditto, except for SSE3 and equal input operands.
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(vec_extract_lo_<mode><mask_name>): Change operand 1 predicate to
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register_operand.
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(vec_extract_hi_v32hi): Ditto.
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(vec_extract_hi_v64hi): Ditto.
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(<mask_codefor>avx512f_unpckhpd512<mask_name>): Ditto.
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2015-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
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Steven Bosscher <steven@gcc.gnu.org>
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@ -6322,11 +6322,14 @@
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;; Although insertps takes register source, we prefer
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;; unpcklps with register source since it is shorter.
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(define_insn "*vec_concatv2sf_sse4_1"
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[(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x,Yr,*x,x,x,*y ,*y")
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[(set (match_operand:V2SF 0 "register_operand"
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"=Yr,*x,x,Yr,*x,x,x,*y ,*y")
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(vec_concat:V2SF
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(match_operand:SF 1 "nonimmediate_operand" " 0, 0,x, 0,0, x,m, 0 , m")
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(match_operand:SF 2 "vector_move_operand" " Yr,*x,x, m,m, m,C,*ym, C")))]
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"TARGET_SSE4_1"
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(match_operand:SF 1 "nonimmediate_operand"
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" 0, 0,x, 0,0, x,m, 0 , m")
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(match_operand:SF 2 "vector_move_operand"
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" Yr,*x,x, m,m, m,C,*ym, C")))]
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"TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"@
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unpcklps\t{%2, %0|%0, %2}
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unpcklps\t{%2, %0|%0, %2}
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@ -7056,7 +7059,7 @@
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(define_insn "vec_extract_lo_<mode><mask_name>"
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[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>")
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(vec_select:<ssehalfvecmode>
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(match_operand:VI4F_256 1 "nonimmediate_operand" "v")
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(match_operand:VI4F_256 1 "register_operand" "v")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)])))]
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"TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
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@ -7157,7 +7160,7 @@
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(define_insn "vec_extract_hi_v32hi"
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[(set (match_operand:V16HI 0 "nonimmediate_operand" "=v,m")
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(vec_select:V16HI
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(match_operand:V32HI 1 "nonimmediate_operand" "v,v")
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(match_operand:V32HI 1 "register_operand" "v,v")
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(parallel [(const_int 16) (const_int 17)
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(const_int 18) (const_int 19)
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(const_int 20) (const_int 21)
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@ -7245,7 +7248,7 @@
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(define_insn "vec_extract_hi_v64qi"
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[(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m")
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(vec_select:V32QI
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(match_operand:V64QI 1 "nonimmediate_operand" "v,v")
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(match_operand:V64QI 1 "register_operand" "v,v")
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(parallel [(const_int 32) (const_int 33)
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(const_int 34) (const_int 35)
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(const_int 36) (const_int 37)
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@ -7345,7 +7348,7 @@
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[(set (match_operand:V8DF 0 "register_operand" "=v")
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(vec_select:V8DF
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(vec_concat:V16DF
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(match_operand:V8DF 1 "nonimmediate_operand" "v")
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(match_operand:V8DF 1 "register_operand" "v")
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(match_operand:V8DF 2 "nonimmediate_operand" "vm"))
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(parallel [(const_int 1) (const_int 9)
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(const_int 3) (const_int 11)
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@ -8507,7 +8510,9 @@
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(vec_concat:V2DF
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(match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0")
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(match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))]
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"TARGET_SSE"
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"TARGET_SSE
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&& (!(MEM_P (operands[1]) && MEM_P (operands[2]))
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|| (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
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"@
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unpcklpd\t{%2, %0|%0, %2}
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vunpcklpd\t{%2, %1, %0|%0, %1, %2}
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@ -9523,7 +9528,7 @@
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(mult:V4DI
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(sign_extend:V4DI
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(vec_select:V4SI
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(match_operand:V8SI 1 "nonimmediate_operand" "v")
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(match_operand:V8SI 1 "nonimmediate_operand" "%v")
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(parallel [(const_int 0) (const_int 2)
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(const_int 4) (const_int 6)])))
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(sign_extend:V4DI
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@ -12875,11 +12880,14 @@
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})
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(define_insn "*vec_concatv2si_sse4_1"
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[(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,x, Yr,*x,x, x, *y,*y")
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[(set (match_operand:V2SI 0 "register_operand"
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"=Yr,*x,x, Yr,*x,x, x, *y,*y")
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(vec_concat:V2SI
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(match_operand:SI 1 "nonimmediate_operand" " 0, 0,x, 0,0, x,rm, 0,rm")
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(match_operand:SI 2 "vector_move_operand" " rm,rm,rm,Yr,*x,x, C,*ym, C")))]
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"TARGET_SSE4_1"
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(match_operand:SI 1 "nonimmediate_operand"
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" 0, 0,x, 0,0, x,rm, 0,rm")
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(match_operand:SI 2 "vector_move_operand"
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" rm,rm,rm,Yr,*x,x, C,*ym, C")))]
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"TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"@
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pinsrd\t{$1, %2, %0|%0, %2, 1}
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pinsrd\t{$1, %2, %0|%0, %2, 1}
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