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[ARM]Remove vec_shr and vec_shr optabs

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* config/arm/neon.md (vec_shl<mode>, vec_shr<mode>): Remove.

From-SVN: r222568
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Alan Lawrence 2015-04-29 10:13:36 +00:00 committed by Alan Lawrence
parent 32966af8aa
commit ee9da432b6
2 changed files with 4 additions and 65 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2015-04-29 Alan Lawrence <alan.lawrence@arm.com>
* config/arm/neon.md (vec_shl<mode>, vec_shr<mode>): Remove.
2015-04-29 Tom de Vries <tom@codesourcery.com>
PR tree-optimization/65893

65
gcc/config/arm/neon.md
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@ -1194,71 +1194,6 @@
[(set_attr "type" "neon_add_widen")]
)
;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit
;; shift-count granularity. That's good enough for the middle-end's current
;; needs.
;; Note that it's not safe to perform such an operation in big-endian mode,
;; due to element-ordering issues.
(define_expand "vec_shr_<mode>"
[(match_operand:VDQ 0 "s_register_operand" "")
(match_operand:VDQ 1 "s_register_operand" "")
(match_operand:SI 2 "const_multiple_of_8_operand" "")]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
{
rtx zero_reg;
HOST_WIDE_INT num_bits = INTVAL (operands[2]);
const int width = GET_MODE_BITSIZE (<MODE>mode);
const machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode;
rtx (*gen_ext) (rtx, rtx, rtx, rtx) =
(width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi;
if (num_bits == width)
{
emit_move_insn (operands[0], operands[1]);
DONE;
}
zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode));
operands[0] = gen_lowpart (bvecmode, operands[0]);
operands[1] = gen_lowpart (bvecmode, operands[1]);
emit_insn (gen_ext (operands[0], operands[1], zero_reg,
GEN_INT (num_bits / BITS_PER_UNIT)));
DONE;
})
(define_expand "vec_shl_<mode>"
[(match_operand:VDQ 0 "s_register_operand" "")
(match_operand:VDQ 1 "s_register_operand" "")
(match_operand:SI 2 "const_multiple_of_8_operand" "")]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
{
rtx zero_reg;
HOST_WIDE_INT num_bits = INTVAL (operands[2]);
const int width = GET_MODE_BITSIZE (<MODE>mode);
const machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode;
rtx (*gen_ext) (rtx, rtx, rtx, rtx) =
(width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi;
if (num_bits == 0)
{
emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
DONE;
}
num_bits = width - num_bits;
zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode));
operands[0] = gen_lowpart (bvecmode, operands[0]);
operands[1] = gen_lowpart (bvecmode, operands[1]);
emit_insn (gen_ext (operands[0], zero_reg, operands[1],
GEN_INT (num_bits / BITS_PER_UNIT)));
DONE;
})
;; Helpers for quad-word reduction operations
; Add (or smin, smax...) the low N/2 elements of the N-element vector