sse.md (extsuffix): New code attribute.
* config/i386/sse.md (extsuffix): New code attribute.
(sse4_1_<code>v8qiv8hi2): Macroize insn from sse4_1_extendv8qiv8hi2
and sse4_1_zero_extendv8qiv8hi2 using any_extend code iterator.
(sse4_1_<code>v4qiv4si2): Ditto from sse4_1_extendv4qiv4si2
and sse4_1_zero_extendv4qiv4si2.
(sse4_1_<code>v2qiv2di2): Ditto from sse4_1_extendv2qiv2di2
and sse4_1_zero_extendv2qiv2di2.
(sse4_1_<code>v4hiv4si2): Ditto from sse4_1_extendv4hiv4si2
and sse4_1_zero_extendv4hiv4si2.
(sse4_1_<code>v2hiv2di2): Ditto from sse4_1_extendv2hiv2di2
and sse4_1_zero_extendv2hiv2di2.
(sse4_1_extendv2siv2di2): Ditto from sse4_1_extendv2siv2di2
and sse4_1_zero_extendv2siv2di2
(<s>mulv8hi3_highpart): Macroize expander from {u,s}mulv8hi3_highpart
using any_extend code iterator.
(*avx_<s>mulv8hi3_highpart): Macroize insn from
*avx_{u,s}mulv8hi3_highpart using any_extend code iterator.
(*<s>mulv8hi3_highpart): Ditto from *{u,s}mulv8hi3_highpart.
* config/i386/i386.c (ix86_expand_sse4_unpack): Update for renamed
gen_sse4_1_sign_extend* functions.
(struct builtin_description bdesc_args): Ditto.
From-SVN: r163616
This commit is contained in:
Uros Bizjak
parent
4c6e913ce8
commit
ee9dd92eea
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@ -1,3 +1,29 @@
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2010-08-28 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (extsuffix): New code attribute.
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(sse4_1_<code>v8qiv8hi2): Macroize insn from sse4_1_extendv8qiv8hi2
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and sse4_1_zero_extendv8qiv8hi2 using any_extend code iterator.
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(sse4_1_<code>v4qiv4si2): Ditto from sse4_1_extendv4qiv4si2
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and sse4_1_zero_extendv4qiv4si2.
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(sse4_1_<code>v2qiv2di2): Ditto from sse4_1_extendv2qiv2di2
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and sse4_1_zero_extendv2qiv2di2.
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(sse4_1_<code>v4hiv4si2): Ditto from sse4_1_extendv4hiv4si2
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and sse4_1_zero_extendv4hiv4si2.
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(sse4_1_<code>v2hiv2di2): Ditto from sse4_1_extendv2hiv2di2
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and sse4_1_zero_extendv2hiv2di2.
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(sse4_1_extendv2siv2di2): Ditto from sse4_1_extendv2siv2di2
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and sse4_1_zero_extendv2siv2di2
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(<s>mulv8hi3_highpart): Macroize expander from {u,s}mulv8hi3_highpart
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using any_extend code iterator.
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(*avx_<s>mulv8hi3_highpart): Macroize insn from
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*avx_{u,s}mulv8hi3_highpart using any_extend code iterator.
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(*<s>mulv8hi3_highpart): Ditto from *{u,s}mulv8hi3_highpart.
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* config/i386/i386.c (ix86_expand_sse4_unpack): Update for renamed
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gen_sse4_1_sign_extend* functions.
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(struct builtin_description bdesc_args): Ditto.
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2010-08-27 Xinliang David Li <davidxl@google.com>
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PR/45422
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@ -245,10 +271,10 @@
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2010-08-27 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* config/arm/arm.md (enabled): Test the value of arch_enabled
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rather than just using it.
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rather than just using it.
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2010-08-27 Olivier Hainque <hainque@adacore.com>
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Eric Botcazou <ebotcazou@adacore.com>
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Eric Botcazou <ebotcazou@adacore.com>
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* dse.c (group_info.base_mem, get_group_info): Use BLKmode to
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cover all the possible offsets from this base.
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@ -17397,19 +17397,19 @@ ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
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if (unsigned_p)
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unpack = gen_sse4_1_zero_extendv8qiv8hi2;
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else
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unpack = gen_sse4_1_extendv8qiv8hi2;
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unpack = gen_sse4_1_sign_extendv8qiv8hi2;
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break;
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case V8HImode:
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if (unsigned_p)
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unpack = gen_sse4_1_zero_extendv4hiv4si2;
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else
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unpack = gen_sse4_1_extendv4hiv4si2;
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unpack = gen_sse4_1_sign_extendv4hiv4si2;
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break;
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case V4SImode:
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if (unsigned_p)
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unpack = gen_sse4_1_zero_extendv2siv2di2;
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else
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unpack = gen_sse4_1_extendv2siv2di2;
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unpack = gen_sse4_1_sign_extendv2siv2di2;
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break;
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default:
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gcc_unreachable ();
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@ -23075,12 +23075,12 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
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@ -19,6 +19,9 @@
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;; <http://www.gnu.org/licenses/>.
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;; Instruction suffix for sign and zero extensions.
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(define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
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;; 16 byte integral modes handled by SSE
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(define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
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@ -5243,92 +5246,47 @@
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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(define_expand "smulv8hi3_highpart"
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(define_expand "<s>mulv8hi3_highpart"
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[(set (match_operand:V8HI 0 "register_operand" "")
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(truncate:V8HI
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(lshiftrt:V8SI
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(mult:V8SI
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(sign_extend:V8SI
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(any_extend:V8SI
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(match_operand:V8HI 1 "nonimmediate_operand" ""))
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(sign_extend:V8SI
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(any_extend:V8SI
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(match_operand:V8HI 2 "nonimmediate_operand" "")))
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(const_int 16))))]
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"TARGET_SSE2"
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"ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
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(define_insn "*avxv8hi3_highpart"
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(define_insn "*avx_<s>mulv8hi3_highpart"
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(truncate:V8HI
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(lshiftrt:V8SI
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(mult:V8SI
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(sign_extend:V8SI
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(any_extend:V8SI
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(match_operand:V8HI 1 "nonimmediate_operand" "%x"))
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(sign_extend:V8SI
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(any_extend:V8SI
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(match_operand:V8HI 2 "nonimmediate_operand" "xm")))
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(const_int 16))))]
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"TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
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"vpmulhw\t{%2, %1, %0|%0, %1, %2}"
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"vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sseimul")
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(set_attr "prefix" "vex")
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(set_attr "mode" "TI")])
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(define_insn "*smulv8hi3_highpart"
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(define_insn "*<s>mulv8hi3_highpart"
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(truncate:V8HI
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(lshiftrt:V8SI
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(mult:V8SI
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(sign_extend:V8SI
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(any_extend:V8SI
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(match_operand:V8HI 1 "nonimmediate_operand" "%0"))
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(sign_extend:V8SI
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(any_extend:V8SI
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(match_operand:V8HI 2 "nonimmediate_operand" "xm")))
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(const_int 16))))]
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"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
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"pmulhw\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseimul")
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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(define_expand "umulv8hi3_highpart"
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[(set (match_operand:V8HI 0 "register_operand" "")
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(truncate:V8HI
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(lshiftrt:V8SI
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(mult:V8SI
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(zero_extend:V8SI
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(match_operand:V8HI 1 "nonimmediate_operand" ""))
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(zero_extend:V8SI
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(match_operand:V8HI 2 "nonimmediate_operand" "")))
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(const_int 16))))]
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"TARGET_SSE2"
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"ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
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(define_insn "*avx_umulv8hi3_highpart"
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(truncate:V8HI
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(lshiftrt:V8SI
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(mult:V8SI
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(zero_extend:V8SI
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(match_operand:V8HI 1 "nonimmediate_operand" "%x"))
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(zero_extend:V8SI
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(match_operand:V8HI 2 "nonimmediate_operand" "xm")))
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(const_int 16))))]
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"TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
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"vpmulhuw\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sseimul")
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(set_attr "prefix" "vex")
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(set_attr "mode" "TI")])
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(define_insn "*umulv8hi3_highpart"
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(truncate:V8HI
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(lshiftrt:V8SI
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(mult:V8SI
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(zero_extend:V8SI
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(match_operand:V8HI 1 "nonimmediate_operand" "%0"))
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(zero_extend:V8SI
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(match_operand:V8HI 2 "nonimmediate_operand" "xm")))
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(const_int 16))))]
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"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
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"pmulhuw\t{%2, %0|%0, %2}"
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"pmulh<u>w\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseimul")
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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@ -9592,9 +9550,9 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "sse4_1_extendv8qiv8hi2"
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(define_insn "sse4_1_<code>v8qiv8hi2"
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(sign_extend:V8HI
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(any_extend:V8HI
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(vec_select:V8QI
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(match_operand:V16QI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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@ -9606,15 +9564,15 @@
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(const_int 6)
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(const_int 7)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxbw\t{%1, %0|%0, %1}"
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"%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
|
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|
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(define_insn "sse4_1_extendv4qiv4si2"
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(define_insn "sse4_1_<code>v4qiv4si2"
|
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[(set (match_operand:V4SI 0 "register_operand" "=x")
|
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(sign_extend:V4SI
|
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(any_extend:V4SI
|
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(vec_select:V4QI
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(match_operand:V16QI 1 "nonimmediate_operand" "xm")
|
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(parallel [(const_int 0)
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|
|
@ -9622,29 +9580,15 @@
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(const_int 2)
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(const_int 3)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxbd\t{%1, %0|%0, %1}"
|
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"%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
|
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[(set_attr "type" "ssemov")
|
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(set_attr "prefix_extra" "1")
|
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(set_attr "prefix" "maybe_vex")
|
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(set_attr "mode" "TI")])
|
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|
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(define_insn "sse4_1_extendv2qiv2di2"
|
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[(set (match_operand:V2DI 0 "register_operand" "=x")
|
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(sign_extend:V2DI
|
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(vec_select:V2QI
|
||||
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
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(const_int 1)]))))]
|
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"TARGET_SSE4_1"
|
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"%vpmovsxbq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
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(set_attr "prefix_extra" "1")
|
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(set_attr "prefix" "maybe_vex")
|
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(set_attr "mode" "TI")])
|
||||
|
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(define_insn "sse4_1_extendv4hiv4si2"
|
||||
(define_insn "sse4_1_<code>v4hiv4si2"
|
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[(set (match_operand:V4SI 0 "register_operand" "=x")
|
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(sign_extend:V4SI
|
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(any_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
|
|
@ -9652,129 +9596,49 @@
|
|||
(const_int 2)
|
||||
(const_int 3)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovsxwd\t{%1, %0|%0, %1}"
|
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"%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_extendv2hiv2di2"
|
||||
(define_insn "sse4_1_<code>v2qiv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(sign_extend:V2DI
|
||||
(vec_select:V2HI
|
||||
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovsxwq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_extendv2siv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(sign_extend:V2DI
|
||||
(vec_select:V2SI
|
||||
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovsxdq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_zero_extendv8qiv8hi2"
|
||||
[(set (match_operand:V8HI 0 "register_operand" "=x")
|
||||
(zero_extend:V8HI
|
||||
(vec_select:V8QI
|
||||
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)
|
||||
(const_int 2)
|
||||
(const_int 3)
|
||||
(const_int 4)
|
||||
(const_int 5)
|
||||
(const_int 6)
|
||||
(const_int 7)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxbw\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_zero_extendv4qiv4si2"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=x")
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4QI
|
||||
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)
|
||||
(const_int 2)
|
||||
(const_int 3)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxbd\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_zero_extendv2qiv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(any_extend:V2DI
|
||||
(vec_select:V2QI
|
||||
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxbq\t{%1, %0|%0, %1}"
|
||||
"%vpmov<extsuffix>bq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_zero_extendv4hiv4si2"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=x")
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)
|
||||
(const_int 2)
|
||||
(const_int 3)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxwd\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_zero_extendv2hiv2di2"
|
||||
(define_insn "sse4_1_<code>v2hiv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(any_extend:V2DI
|
||||
(vec_select:V2HI
|
||||
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxwq\t{%1, %0|%0, %1}"
|
||||
"%vpmov<extsuffix>wq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "sse4_1_zero_extendv2siv2di2"
|
||||
(define_insn "sse4_1_<code>v2siv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(any_extend:V2DI
|
||||
(vec_select:V2SI
|
||||
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxdq\t{%1, %0|%0, %1}"
|
||||
"%vpmov<extsuffix>dq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
|
|
|
|||
Loading…
Reference in New Issue