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opts: Remove all usages of Report keyword.

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gcc/brig/ChangeLog:

	* lang.opt: Remove usage of Report.

gcc/c-family/ChangeLog:

	* c.opt: Remove usage of Report.

gcc/ChangeLog:

	* common.opt: Remove usage of Report.
	* config/aarch64/aarch64.opt: Ditto.
	* config/alpha/alpha.opt: Ditto.
	* config/arc/arc.opt: Ditto.
	* config/arm/arm.opt: Ditto.
	* config/avr/avr.opt: Ditto.
	* config/bfin/bfin.opt: Ditto.
	* config/bpf/bpf.opt: Ditto.
	* config/c6x/c6x.opt: Ditto.
	* config/cr16/cr16.opt: Ditto.
	* config/cris/cris.opt: Ditto.
	* config/cris/elf.opt: Ditto.
	* config/csky/csky.opt: Ditto.
	* config/darwin.opt: Ditto.
	* config/fr30/fr30.opt: Ditto.
	* config/frv/frv.opt: Ditto.
	* config/ft32/ft32.opt: Ditto.
	* config/gcn/gcn.opt: Ditto.
	* config/i386/cygming.opt: Ditto.
	* config/i386/i386.opt: Ditto.
	* config/ia64/ia64.opt: Ditto.
	* config/ia64/ilp32.opt: Ditto.
	* config/linux-android.opt: Ditto.
	* config/linux.opt: Ditto.
	* config/lm32/lm32.opt: Ditto.
	* config/m32r/m32r.opt: Ditto.
	* config/m68k/m68k.opt: Ditto.
	* config/mcore/mcore.opt: Ditto.
	* config/microblaze/microblaze.opt: Ditto.
	* config/mips/mips.opt: Ditto.
	* config/mmix/mmix.opt: Ditto.
	* config/mn10300/mn10300.opt: Ditto.
	* config/moxie/moxie.opt: Ditto.
	* config/msp430/msp430.opt: Ditto.
	* config/nds32/nds32.opt: Ditto.
	* config/nios2/elf.opt: Ditto.
	* config/nios2/nios2.opt: Ditto.
	* config/nvptx/nvptx.opt: Ditto.
	* config/pa/pa.opt: Ditto.
	* config/pdp11/pdp11.opt: Ditto.
	* config/pru/pru.opt: Ditto.
	* config/riscv/riscv.opt: Ditto.
	* config/rl78/rl78.opt: Ditto.
	* config/rs6000/aix64.opt: Ditto.
	* config/rs6000/linux64.opt: Ditto.
	* config/rs6000/rs6000.opt: Ditto.
	* config/rs6000/sysv4.opt: Ditto.
	* config/rx/elf.opt: Ditto.
	* config/rx/rx.opt: Ditto.
	* config/s390/s390.opt: Ditto.
	* config/s390/tpf.opt: Ditto.
	* config/sh/sh.opt: Ditto.
	* config/sol2.opt: Ditto.
	* config/sparc/long-double-switch.opt: Ditto.
	* config/sparc/sparc.opt: Ditto.
	* config/tilegx/tilegx.opt: Ditto.
	* config/tilepro/tilepro.opt: Ditto.
	* config/v850/v850.opt: Ditto.
	* config/visium/visium.opt: Ditto.
	* config/vms/vms.opt: Ditto.
	* config/vxworks.opt: Ditto.
	* config/xtensa/xtensa.opt: Ditto.

gcc/lto/ChangeLog:

	* lang.opt: Remove usage of Report.
This commit is contained in:
Martin Liska 2020-12-11 17:25:43 +01:00
parent 5137d1ae6a
commit eece52b53b
65 changed files with 1383 additions and 1383 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
gcc/brig/lang.opt
View File

@ -32,7 +32,7 @@ BRIG Separate Alias(d)
BRIG Joined Alias(d) BRIG Joined Alias(d)
fassume-phsa fassume-phsa
BRIG Report Var(flag_assume_phsa) Init(1) Optimization BRIG Var(flag_assume_phsa) Init(1) Optimization
Assume we are finalizing for phsa and its libhsail-rt. Enables additional Assume we are finalizing for phsa and its libhsail-rt. Enables additional
phsa-specific optimizations (default). phsa-specific optimizations (default).

8
gcc/c-family/c.opt
View File

@ -1647,7 +1647,7 @@ C++ ObjC++ Var(flag_no_gnu_keywords, 0)
Recognize GNU-defined keywords. Recognize GNU-defined keywords.
fgnu-runtime fgnu-runtime
ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME) ObjC ObjC++ LTO RejectNegative Var(flag_next_runtime,0) Init(NEXT_OBJC_RUNTIME)
Generate code for GNU runtime environment. Generate code for GNU runtime environment.
fgnu89-inline fgnu89-inline
@ -1691,7 +1691,7 @@ ffriend-injection
C++ ObjC++ WarnRemoved C++ ObjC++ WarnRemoved
fkeep-inline-dllexport fkeep-inline-dllexport
C C++ ObjC ObjC++ Var(flag_keep_inline_dllexport) Init(1) Report Condition(TARGET_DLLIMPORT_DECL_ATTRIBUTES) C C++ ObjC ObjC++ Var(flag_keep_inline_dllexport) Init(1) Condition(TARGET_DLLIMPORT_DECL_ATTRIBUTES)
Don't emit dllexported inline functions unless needed. Don't emit dllexported inline functions unless needed.
flabels-ok flabels-ok
@ -1780,7 +1780,7 @@ C++ ObjC++ Var(flag_new_ttp)
Implement resolution of DR 150 for matching of template template arguments. Implement resolution of DR 150 for matching of template template arguments.
fnext-runtime fnext-runtime
ObjC ObjC++ LTO Report RejectNegative Var(flag_next_runtime) ObjC ObjC++ LTO RejectNegative Var(flag_next_runtime)
Generate code for NeXT (Apple Mac OS X) runtime environment. Generate code for NeXT (Apple Mac OS X) runtime environment.
fnil-receivers fnil-receivers
@ -1821,7 +1821,7 @@ C++ ObjC++ Optimization Var(flag_nothrow_opt)
Treat a throw() exception specification as noexcept to improve code size. Treat a throw() exception specification as noexcept to improve code size.
fobjc-abi-version= fobjc-abi-version=
ObjC ObjC++ LTO Joined Report RejectNegative UInteger Var(flag_objc_abi) ObjC ObjC++ LTO Joined RejectNegative UInteger Var(flag_objc_abi)
Specify which ABI to use for Objective-C family code and meta-data generation. Specify which ABI to use for Objective-C family code and meta-data generation.
; Generate special '- .cxx_construct' and '- .cxx_destruct' methods ; Generate special '- .cxx_construct' and '- .cxx_destruct' methods

584
gcc/common.opt
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File diff suppressed because it is too large Load Diff

18
gcc/config/aarch64/aarch64.opt
View File

@ -64,11 +64,11 @@ EnumValue
Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE)
mbig-endian mbig-endian
Target Report RejectNegative Mask(BIG_END) Target RejectNegative Mask(BIG_END)
Assume target CPU is configured as big endian. Assume target CPU is configured as big endian.
mgeneral-regs-only mgeneral-regs-only
Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
Generate code which uses only the general registers. Generate code which uses only the general registers.
mharden-sls= mharden-sls=
@ -76,15 +76,15 @@ Target RejectNegative Joined Var(aarch64_harden_sls_string)
Generate code to mitigate against straight line speculation. Generate code to mitigate against straight line speculation.
mfix-cortex-a53-835769 mfix-cortex-a53-835769
Target Report Var(aarch64_fix_a53_err835769) Init(2) Save Target Var(aarch64_fix_a53_err835769) Init(2) Save
Workaround for ARM Cortex-A53 Erratum number 835769. Workaround for ARM Cortex-A53 Erratum number 835769.
mfix-cortex-a53-843419 mfix-cortex-a53-843419
Target Report Var(aarch64_fix_a53_err843419) Init(2) Save Target Var(aarch64_fix_a53_err843419) Init(2) Save
Workaround for ARM Cortex-A53 Erratum number 843419. Workaround for ARM Cortex-A53 Erratum number 843419.
mlittle-endian mlittle-endian
Target Report RejectNegative InverseMask(BIG_END) Target RejectNegative InverseMask(BIG_END)
Assume target CPU is configured as little endian. Assume target CPU is configured as little endian.
mcmodel= mcmodel=
@ -92,11 +92,11 @@ Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_C
Specify the code model. Specify the code model.
mstrict-align mstrict-align
Target Report Mask(STRICT_ALIGN) Save Target Mask(STRICT_ALIGN) Save
Don't assume that unaligned accesses are handled by the system. Don't assume that unaligned accesses are handled by the system.
momit-leaf-frame-pointer momit-leaf-frame-pointer
Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save Target Var(flag_omit_leaf_frame_pointer) Init(2) Save
Omit the frame pointer in leaf functions. Omit the frame pointer in leaf functions.
mtls-dialect= mtls-dialect=
@ -153,7 +153,7 @@ EnumValue
Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64) Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
mpc-relative-literal-loads mpc-relative-literal-loads
Target Report Save Var(pcrelative_literal_loads) Init(2) Save Target Save Var(pcrelative_literal_loads) Init(2) Save
PC relative literal loads. PC relative literal loads.
mbranch-protection= mbranch-protection=
@ -260,7 +260,7 @@ TargetVariable
long aarch64_stack_protector_guard_offset = 0 long aarch64_stack_protector_guard_offset = 0
moutline-atomics moutline-atomics
Target Report Var(aarch64_flag_outline_atomics) Init(2) Save Target Var(aarch64_flag_outline_atomics) Init(2) Save
Generate local calls to out-of-line atomic operations. Generate local calls to out-of-line atomic operations.
-param=aarch64-sve-compare-costs= -param=aarch64-sve-compare-costs=

38
gcc/config/alpha/alpha.opt
View File

@ -19,11 +19,11 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
msoft-float msoft-float
Target Report Mask(SOFT_FP) Target Mask(SOFT_FP)
Do not use hardware fp. Do not use hardware fp.
mfp-regs mfp-regs
Target Report Mask(FPREGS) Target Mask(FPREGS)
Use fp registers. Use fp registers.
mgas mgas
@ -35,70 +35,70 @@ Target RejectNegative Mask(IEEE_CONFORMANT)
Request IEEE-conformant math library routines (OSF/1). Request IEEE-conformant math library routines (OSF/1).
mieee mieee
Target Report RejectNegative Mask(IEEE) Target RejectNegative Mask(IEEE)
Emit IEEE-conformant code, without inexact exceptions. Emit IEEE-conformant code, without inexact exceptions.
mieee-with-inexact mieee-with-inexact
Target Report RejectNegative Mask(IEEE_WITH_INEXACT) Target RejectNegative Mask(IEEE_WITH_INEXACT)
mbuild-constants mbuild-constants
Target Report Mask(BUILD_CONSTANTS) Target Mask(BUILD_CONSTANTS)
Do not emit complex integer constants to read-only memory. Do not emit complex integer constants to read-only memory.
mfloat-vax mfloat-vax
Target Report RejectNegative Mask(FLOAT_VAX) Target RejectNegative Mask(FLOAT_VAX)
Use VAX fp. Use VAX fp.
mfloat-ieee mfloat-ieee
Target Report RejectNegative InverseMask(FLOAT_VAX) Target RejectNegative InverseMask(FLOAT_VAX)
Do not use VAX fp. Do not use VAX fp.
mbwx mbwx
Target Report Mask(BWX) Target Mask(BWX)
Emit code for the byte/word ISA extension. Emit code for the byte/word ISA extension.
mmax mmax
Target Report Mask(MAX) Target Mask(MAX)
Emit code for the motion video ISA extension. Emit code for the motion video ISA extension.
mfix mfix
Target Report Mask(FIX) Target Mask(FIX)
Emit code for the fp move and sqrt ISA extension. Emit code for the fp move and sqrt ISA extension.
mcix mcix
Target Report Mask(CIX) Target Mask(CIX)
Emit code for the counting ISA extension. Emit code for the counting ISA extension.
mexplicit-relocs mexplicit-relocs
Target Report Mask(EXPLICIT_RELOCS) Target Mask(EXPLICIT_RELOCS)
Emit code using explicit relocation directives. Emit code using explicit relocation directives.
msmall-data msmall-data
Target Report RejectNegative Mask(SMALL_DATA) Target RejectNegative Mask(SMALL_DATA)
Emit 16-bit relocations to the small data areas. Emit 16-bit relocations to the small data areas.
mlarge-data mlarge-data
Target Report RejectNegative InverseMask(SMALL_DATA) Target RejectNegative InverseMask(SMALL_DATA)
Emit 32-bit relocations to the small data areas. Emit 32-bit relocations to the small data areas.
msmall-text msmall-text
Target Report RejectNegative Mask(SMALL_TEXT) Target RejectNegative Mask(SMALL_TEXT)
Emit direct branches to local functions. Emit direct branches to local functions.
mlarge-text mlarge-text
Target Report RejectNegative InverseMask(SMALL_TEXT) Target RejectNegative InverseMask(SMALL_TEXT)
Emit indirect branches to local functions. Emit indirect branches to local functions.
mtls-kernel mtls-kernel
Target Report Mask(TLS_KERNEL) Target Mask(TLS_KERNEL)
Emit rdval instead of rduniq for thread pointer. Emit rdval instead of rduniq for thread pointer.
mlong-double-128 mlong-double-128
Target Report RejectNegative Mask(LONG_DOUBLE_128) Target RejectNegative Mask(LONG_DOUBLE_128)
Use 128-bit long double. Use 128-bit long double.
mlong-double-64 mlong-double-64
Target Report RejectNegative InverseMask(LONG_DOUBLE_128) Target RejectNegative InverseMask(LONG_DOUBLE_128)
Use 64-bit long double. Use 64-bit long double.
mcpu= mcpu=

110
gcc/config/arc/arc.opt
View File

@ -22,39 +22,39 @@ HeaderInclude
config/arc/arc-opts.h config/arc/arc-opts.h
mbig-endian mbig-endian
Target Report RejectNegative Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Compile code for big endian mode. Compile code for big endian mode.
mlittle-endian mlittle-endian
Target Report RejectNegative InverseMask(BIG_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN)
Compile code for little endian mode. This is the default. Compile code for little endian mode. This is the default.
mno-cond-exec mno-cond-exec
Target Report RejectNegative Mask(NO_COND_EXEC) Target RejectNegative Mask(NO_COND_EXEC)
Disable ARCompact specific pass to generate conditional execution instructions. Disable ARCompact specific pass to generate conditional execution instructions.
mA6 mA6
Target Report Target
Generate ARCompact 32-bit code for ARC600 processor. Generate ARCompact 32-bit code for ARC600 processor.
mARC600 mARC600
Target Report Target
Same as -mA6. Same as -mA6.
mARC601 mARC601
Target Report Target
Generate ARCompact 32-bit code for ARC601 processor. Generate ARCompact 32-bit code for ARC601 processor.
mA7 mA7
Target Report Target
Generate ARCompact 32-bit code for ARC700 processor. Generate ARCompact 32-bit code for ARC700 processor.
mARC700 mARC700
Target Report Target
Same as -mA7. Same as -mA7.
mjli-always mjli-always
Target Report Mask(JLI_ALWAYS) Target Mask(JLI_ALWAYS)
Force all calls to be made via a jli instruction. Force all calls to be made via a jli instruction.
mmpy-option= mmpy-option=
@ -128,15 +128,15 @@ EnumValue
Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
mdiv-rem mdiv-rem
Target Report Mask(DIVREM) Target Mask(DIVREM)
Enable DIV-REM instructions for ARCv2. Enable DIV-REM instructions for ARCv2.
mcode-density mcode-density
Target Report Mask(CODE_DENSITY) Target Mask(CODE_DENSITY)
Enable code density instructions for ARCv2. Enable code density instructions for ARCv2.
mmixed-code mmixed-code
Target Report Mask(MIXED_CODE_SET) Target Mask(MIXED_CODE_SET)
Tweak register allocation to help 16-bit instruction generation. Tweak register allocation to help 16-bit instruction generation.
; originally this was: ; originally this was:
;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
@ -146,91 +146,91 @@ Tweak register allocation to help 16-bit instruction generation.
; We use an explict definition for the negative form because that is the ; We use an explict definition for the negative form because that is the
; actually interesting option, and we want that to have its own comment. ; actually interesting option, and we want that to have its own comment.
mvolatile-cache mvolatile-cache
Target Report RejectNegative Mask(VOLATILE_CACHE_SET) Target RejectNegative Mask(VOLATILE_CACHE_SET)
Use ordinarily cached memory accesses for volatile references. Use ordinarily cached memory accesses for volatile references.
mno-volatile-cache mno-volatile-cache
Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET) Target RejectNegative InverseMask(VOLATILE_CACHE_SET)
Enable cache bypass for volatile references. Enable cache bypass for volatile references.
mbarrel-shifter mbarrel-shifter
Target Report Mask(BARREL_SHIFTER) Target Mask(BARREL_SHIFTER)
Generate instructions supported by barrel shifter. Generate instructions supported by barrel shifter.
mnorm mnorm
Target Report Mask(NORM_SET) Target Mask(NORM_SET)
Generate norm instruction. Generate norm instruction.
mswap mswap
Target Report Mask(SWAP_SET) Target Mask(SWAP_SET)
Generate swap instruction. Generate swap instruction.
mmul64 mmul64
Target Report Mask(MUL64_SET) Target Mask(MUL64_SET)
Generate mul64 and mulu64 instructions. Generate mul64 and mulu64 instructions.
mno-mpy mno-mpy
Target Report Mask(NOMPY_SET) Warn(%qs is deprecated) Target Mask(NOMPY_SET) Warn(%qs is deprecated)
Do not generate mpy instructions for ARC700. Do not generate mpy instructions for ARC700.
mea mea
Target Report Mask(EA_SET) Target Mask(EA_SET)
Generate extended arithmetic instructions, only valid for ARC700. Generate extended arithmetic instructions, only valid for ARC700.
msoft-float msoft-float
Target Report Mask(0) Target Mask(0)
Dummy flag. This is the default unless FPX switches are provided explicitly. Dummy flag. This is the default unless FPX switches are provided explicitly.
mlong-calls mlong-calls
Target Report Mask(LONG_CALLS_SET) Target Mask(LONG_CALLS_SET)
Generate call insns as register indirect calls. Generate call insns as register indirect calls.
mno-brcc mno-brcc
Target Report Mask(NO_BRCC_SET) Target Mask(NO_BRCC_SET)
Do no generate BRcc instructions in arc_reorg. Do no generate BRcc instructions in arc_reorg.
msdata msdata
Target Report InverseMask(NO_SDATA_SET) Target InverseMask(NO_SDATA_SET)
Generate sdata references. This is the default, unless you compile for PIC. Generate sdata references. This is the default, unless you compile for PIC.
mmillicode mmillicode
Target Report Mask(MILLICODE_THUNK_SET) Target Mask(MILLICODE_THUNK_SET)
Generate millicode thunks. Generate millicode thunks.
mspfp mspfp
Target Report Mask(SPFP_COMPACT_SET) Target Mask(SPFP_COMPACT_SET)
FPX: Generate Single Precision FPX (compact) instructions. FPX: Generate Single Precision FPX (compact) instructions.
mspfp-compact mspfp-compact
Target Report Mask(SPFP_COMPACT_SET) MaskExists Target Mask(SPFP_COMPACT_SET) MaskExists
FPX: Generate Single Precision FPX (compact) instructions. FPX: Generate Single Precision FPX (compact) instructions.
mspfp-fast mspfp-fast
Target Report Mask(SPFP_FAST_SET) Target Mask(SPFP_FAST_SET)
FPX: Generate Single Precision FPX (fast) instructions. FPX: Generate Single Precision FPX (fast) instructions.
margonaut margonaut
Target Report Mask(ARGONAUT_SET) Target Mask(ARGONAUT_SET)
FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
mdpfp mdpfp
Target Report Mask(DPFP_COMPACT_SET) Target Mask(DPFP_COMPACT_SET)
FPX: Generate Double Precision FPX (compact) instructions. FPX: Generate Double Precision FPX (compact) instructions.
mdpfp-compact mdpfp-compact
Target Report Mask(DPFP_COMPACT_SET) MaskExists Target Mask(DPFP_COMPACT_SET) MaskExists
FPX: Generate Double Precision FPX (compact) instructions. FPX: Generate Double Precision FPX (compact) instructions.
mdpfp-fast mdpfp-fast
Target Report Mask(DPFP_FAST_SET) Target Mask(DPFP_FAST_SET)
FPX: Generate Double Precision FPX (fast) instructions. FPX: Generate Double Precision FPX (fast) instructions.
mno-dpfp-lrsr mno-dpfp-lrsr
Target Report Mask(DPFP_DISABLE_LRSR) Target Mask(DPFP_DISABLE_LRSR)
Disable LR and SR instructions from using FPX extension aux registers. Disable LR and SR instructions from using FPX extension aux registers.
msimd msimd
Target Report Mask(SIMD_SET) Target Mask(SIMD_SET)
Enable generation of ARC SIMD instructions via target-specific builtins. Enable generation of ARC SIMD instructions via target-specific builtins.
mcpu= mcpu=
@ -242,7 +242,7 @@ Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os. Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
misize misize
Target Report PchIgnore Var(TARGET_DUMPISIZE) Target PchIgnore Var(TARGET_DUMPISIZE)
Annotate assembler instructions with estimated addresses. Annotate assembler instructions with estimated addresses.
mmultcost= mmultcost=
@ -289,7 +289,7 @@ Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
Enable the use of pre/post modify with register displacement. Enable the use of pre/post modify with register displacement.
mmul32x16 mmul32x16
Target Report Mask(MULMAC_32BY16_SET) Target Mask(MULMAC_32BY16_SET)
Generate 32x16 multiply and mac instructions. Generate 32x16 multiply and mac instructions.
; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
@ -346,42 +346,42 @@ Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
; Flags used by the assembler, but for which we define preprocessor ; Flags used by the assembler, but for which we define preprocessor
; macro symbols as well. ; macro symbols as well.
mcrc mcrc
Target Report Warn(%qs is deprecated) Target Warn(%qs is deprecated)
Enable variable polynomial CRC extension. Enable variable polynomial CRC extension.
mdsp-packa mdsp-packa
Target Report Warn(%qs is deprecated) Target Warn(%qs is deprecated)
Enable DSP 3.1 Pack A extensions. Enable DSP 3.1 Pack A extensions.
mdvbf mdvbf
Target Report Warn(%qs is deprecated) Target Warn(%qs is deprecated)
Enable dual viterbi butterfly extension. Enable dual viterbi butterfly extension.
mmac-d16 mmac-d16
Target Report Undocumented Warn(%qs is deprecated) Target Undocumented Warn(%qs is deprecated)
mmac-24 mmac-24
Target Report Undocumented Warn(%qs is deprecated) Target Undocumented Warn(%qs is deprecated)
mtelephony mtelephony
Target Report RejectNegative Warn(%qs is deprecated) Target RejectNegative Warn(%qs is deprecated)
Enable Dual and Single Operand Instructions for Telephony. Enable Dual and Single Operand Instructions for Telephony.
mxy mxy
Target Report Target
Enable XY Memory extension (DSP version 3). Enable XY Memory extension (DSP version 3).
; ARC700 4.10 extension instructions ; ARC700 4.10 extension instructions
mlock mlock
Target Report Target
Enable Locked Load/Store Conditional extension. Enable Locked Load/Store Conditional extension.
mswape mswape
Target Report Target
Enable swap byte ordering extension instruction. Enable swap byte ordering extension instruction.
mrtsc mrtsc
Target Report Warn(%qs is deprecated) Target Warn(%qs is deprecated)
Enable 64-bit Time-Stamp Counter extension instruction. Enable 64-bit Time-Stamp Counter extension instruction.
EB EB
@ -402,7 +402,7 @@ Pass -marclinux_prof option through to linker.
;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
mlra mlra
Target Report Var(arc_lra_flag) Init(1) Save Target Var(arc_lra_flag) Init(1) Save
Use LRA instead of reload. Use LRA instead of reload.
mlra-priority-none mlra-priority-none
@ -426,11 +426,11 @@ multcost=
Target RejectNegative Joined Target RejectNegative Joined
matomic matomic
Target Report Mask(ATOMIC) Target Mask(ATOMIC)
Enable atomic instructions. Enable atomic instructions.
mll64 mll64
Target Report Mask(LL64) Target Mask(LL64)
Enable double load/store instructions for ARC HS. Enable double load/store instructions for ARC HS.
mfpu= mfpu=
@ -484,15 +484,15 @@ mtp-regno=none
Target RejectNegative Var(arc_tp_regno,-1) Target RejectNegative Var(arc_tp_regno,-1)
mbitops mbitops
Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT) Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
Enable use of NPS400 bit operations. Enable use of NPS400 bit operations.
mcmem mcmem
Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT) Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
Enable use of NPS400 xld/xst extension. Enable use of NPS400 xld/xst extension.
munaligned-access munaligned-access
Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
Enable unaligned word and halfword accesses to packed data. Enable unaligned word and halfword accesses to packed data.
mirq-ctrl-saved= mirq-ctrl-saved=
@ -529,13 +529,13 @@ EnumValue
Enum(arc_lpc) String(32) Value(32) Enum(arc_lpc) String(32) Value(32)
mrf16 mrf16
Target Report Mask(RF16) Target Mask(RF16)
Enable 16-entry register file. Enable 16-entry register file.
mbranch-index mbranch-index
Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX) Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX)
Enable use of BI/BIH instructions when available. Enable use of BI/BIH instructions when available.
mcode-density-frame mcode-density-frame
Target Report Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT) Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT)
Enable ENTER_S and LEAVE_S opcodes for ARCv2. Enable ENTER_S and LEAVE_S opcodes for ARCv2.

66
gcc/config/arm/arm.opt
View File

@ -55,22 +55,22 @@ EnumValue
Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX)
mabort-on-noreturn mabort-on-noreturn
Target Report Mask(ABORT_NORETURN) Target Mask(ABORT_NORETURN)
Generate a call to abort if a noreturn function returns. Generate a call to abort if a noreturn function returns.
mapcs mapcs
Target RejectNegative Mask(APCS_FRAME) Undocumented Target RejectNegative Mask(APCS_FRAME) Undocumented
mapcs-frame mapcs-frame
Target Report Mask(APCS_FRAME) Target Mask(APCS_FRAME)
Generate APCS conformant stack frames. Generate APCS conformant stack frames.
mapcs-reentrant mapcs-reentrant
Target Report Mask(APCS_REENT) Target Mask(APCS_REENT)
Generate re-entrant, PIC code. Generate re-entrant, PIC code.
mapcs-stack-check mapcs-stack-check
Target Report Mask(APCS_STACK) Undocumented Target Mask(APCS_STACK) Undocumented
march= march=
Target Save RejectNegative Negative(march=) ToLower Joined Var(arm_arch_string) Target Save RejectNegative Negative(march=) ToLower Joined Var(arm_arch_string)
@ -82,19 +82,19 @@ EnumValue
Enum(arm_arch) String(native) Value(-1) DriverOnly Enum(arm_arch) String(native) Value(-1) DriverOnly
marm marm
Target Report RejectNegative Negative(mthumb) InverseMask(THUMB) Target RejectNegative Negative(mthumb) InverseMask(THUMB)
Generate code in 32 bit ARM state. Generate code in 32 bit ARM state.
mbig-endian mbig-endian
Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END) Target RejectNegative Negative(mlittle-endian) Mask(BIG_END)
Assume target CPU is configured as big endian. Assume target CPU is configured as big endian.
mcallee-super-interworking mcallee-super-interworking
Target Report Mask(CALLEE_INTERWORKING) Target Mask(CALLEE_INTERWORKING)
Thumb: Assume non-static functions may be called from ARM code. Thumb: Assume non-static functions may be called from ARM code.
mcaller-super-interworking mcaller-super-interworking
Target Report Mask(CALLER_INTERWORKING) Target Mask(CALLER_INTERWORKING)
Thumb: Assume function pointers may go to non-Thumb aware code. Thumb: Assume function pointers may go to non-Thumb aware code.
mcpu= mcpu=
@ -123,7 +123,7 @@ EnumValue
Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD) Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD)
mflip-thumb mflip-thumb
Target Report Var(TARGET_FLIP_THUMB) Undocumented Target Var(TARGET_FLIP_THUMB) Undocumented
Switch ARM/Thumb modes on alternating functions for compiler testing. Switch ARM/Thumb modes on alternating functions for compiler testing.
mfp16-format= mfp16-format=
@ -151,15 +151,15 @@ mhard-float
Target RejectNegative Alias(mfloat-abi=, hard) Undocumented Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
mlittle-endian mlittle-endian
Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END) Target RejectNegative Negative(mbig-endian) InverseMask(BIG_END)
Assume target CPU is configured as little endian. Assume target CPU is configured as little endian.
mlong-calls mlong-calls
Target Report Mask(LONG_CALLS) Target Mask(LONG_CALLS)
Generate call insns as indirect calls, if necessary. Generate call insns as indirect calls, if necessary.
mpic-data-is-text-relative mpic-data-is-text-relative
Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) Target Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE)
Assume data segments are relative to text segment. Assume data segments are relative to text segment.
mpic-register= mpic-register=
@ -167,15 +167,15 @@ Target RejectNegative Joined Var(arm_pic_register_string)
Specify the register to be used for PIC addressing. Specify the register to be used for PIC addressing.
mpoke-function-name mpoke-function-name
Target Report Mask(POKE_FUNCTION_NAME) Target Mask(POKE_FUNCTION_NAME)
Store function names in object code. Store function names in object code.
msched-prolog msched-prolog
Target Report Mask(SCHED_PROLOG) Target Mask(SCHED_PROLOG)
Permit scheduling of a function's prologue sequence. Permit scheduling of a function's prologue sequence.
msingle-pic-base msingle-pic-base
Target Report Mask(SINGLE_PIC_BASE) Target Mask(SINGLE_PIC_BASE)
Do not load the PIC register in function prologues. Do not load the PIC register in function prologues.
msoft-float msoft-float
@ -186,11 +186,11 @@ Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFA
Specify the minimum bit alignment of structures. (Deprecated). Specify the minimum bit alignment of structures. (Deprecated).
mthumb mthumb
Target Report RejectNegative Negative(marm) Mask(THUMB) Save Target RejectNegative Negative(marm) Mask(THUMB) Save
Generate code for Thumb state. Generate code for Thumb state.
mthumb-interwork mthumb-interwork
Target Report Mask(INTERWORK) Target Mask(INTERWORK)
Support calls between Thumb and ARM instruction sets. Support calls between Thumb and ARM instruction sets.
mtls-dialect= mtls-dialect=
@ -215,11 +215,11 @@ EnumValue
Enum(arm_tp_type) String(cp15) Value(TP_CP15) Enum(arm_tp_type) String(cp15) Value(TP_CP15)
mtpcs-frame mtpcs-frame
Target Report Mask(TPCS_FRAME) Target Mask(TPCS_FRAME)
Thumb: Generate (non-leaf) stack frames even if not needed. Thumb: Generate (non-leaf) stack frames even if not needed.
mtpcs-leaf-frame mtpcs-leaf-frame
Target Report Mask(TPCS_LEAF_FRAME) Target Mask(TPCS_LEAF_FRAME)
Thumb: Generate (leaf) stack frames even if not needed. Thumb: Generate (leaf) stack frames even if not needed.
mtune= mtune=
@ -227,7 +227,7 @@ Target Save RejectNegative Negative(mtune=) ToLower Joined Var(arm_tune_string)
Tune code for the given processor. Tune code for the given processor.
mprint-tune-info mprint-tune-info
Target Report RejectNegative Var(print_tune_info) Init(0) Target RejectNegative Var(print_tune_info) Init(0)
Print CPU tuning information as comment in assembler file. This is Print CPU tuning information as comment in assembler file. This is
an option used only for regression testing of the compiler and not an option used only for regression testing of the compiler and not
intended for ordinary use in compiling code. intended for ordinary use in compiling code.
@ -238,11 +238,11 @@ EnumValue
Enum(processor_type) String(native) Value(-1) DriverOnly Enum(processor_type) String(native) Value(-1) DriverOnly
mvectorize-with-neon-quad mvectorize-with-neon-quad
Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) Target RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE)
Use Neon quad-word (rather than double-word) registers for vectorization. Use Neon quad-word (rather than double-word) registers for vectorization.
mvectorize-with-neon-double mvectorize-with-neon-double
Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE) Target RejectNegative Mask(NEON_VECTORIZE_DOUBLE)
Use Neon double-word (rather than quad-word) registers for vectorization. Use Neon double-word (rather than quad-word) registers for vectorization.
mverbose-cost-dump mverbose-cost-dump
@ -250,20 +250,20 @@ Common Undocumented Var(arm_verbose_cost) Init(0)
Enable more verbose RTX cost dumps during debug. For GCC developers use only. Enable more verbose RTX cost dumps during debug. For GCC developers use only.
mword-relocations mword-relocations
Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) Target Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
Only generate absolute relocations on word sized values. Only generate absolute relocations on word sized values.
mrestrict-it mrestrict-it
Target Report Var(arm_restrict_it) Init(2) Save Target Var(arm_restrict_it) Init(2) Save
Generate IT blocks appropriate for ARMv8. Generate IT blocks appropriate for ARMv8.
mfix-cortex-m3-ldrd mfix-cortex-m3-ldrd
Target Report Var(fix_cm3_ldrd) Init(2) Target Var(fix_cm3_ldrd) Init(2)
Avoid overlapping destination and address registers on LDRD instructions Avoid overlapping destination and address registers on LDRD instructions
that may trigger Cortex-M3 errata. that may trigger Cortex-M3 errata.
munaligned-access munaligned-access
Target Report Var(unaligned_access) Init(2) Save Target Var(unaligned_access) Init(2) Save
Enable unaligned word and halfword accesses to packed data. Enable unaligned word and halfword accesses to packed data.
mneon-for-64bits mneon-for-64bits
@ -271,23 +271,23 @@ Target WarnRemoved
This option is deprecated and has no effect. This option is deprecated and has no effect.
mslow-flash-data mslow-flash-data
Target Report Var(target_slow_flash_data) Init(0) Target Var(target_slow_flash_data) Init(0)
Assume loading data from flash is slower than fetching instructions. Assume loading data from flash is slower than fetching instructions.
masm-syntax-unified masm-syntax-unified
Target Report Var(inline_asm_unified) Init(0) Save Target Var(inline_asm_unified) Init(0) Save
Assume unified syntax for inline assembly code. Assume unified syntax for inline assembly code.
mpure-code mpure-code
Target Report Var(target_pure_code) Init(0) Target Var(target_pure_code) Init(0)
Do not allow constant data to be placed in code sections. Do not allow constant data to be placed in code sections.
mbe8 mbe8
Target Report RejectNegative Negative(mbe32) Mask(BE8) Target RejectNegative Negative(mbe32) Mask(BE8)
When linking for big-endian targets, generate a BE8 format image. When linking for big-endian targets, generate a BE8 format image.
mbe32 mbe32
Target Report RejectNegative Negative(mbe8) InverseMask(BE8) Target RejectNegative Negative(mbe8) InverseMask(BE8)
When linking for big-endian targets, generate a legacy BE32 format image. When linking for big-endian targets, generate a legacy BE32 format image.
mbranch-cost= mbranch-cost=
@ -295,9 +295,9 @@ Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1)
Cost to assume for a branch insn. Cost to assume for a branch insn.
mgeneral-regs-only mgeneral-regs-only
Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
Generate code which uses the core registers only (r0-r14). Generate code which uses the core registers only (r0-r14).
mfdpic mfdpic
Target Report Mask(FDPIC) Target Mask(FDPIC)
Enable Function Descriptor PIC mode. Enable Function Descriptor PIC mode.

52
gcc/config/avr/avr.opt
View File

@ -19,7 +19,7 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mcall-prologues mcall-prologues
Target Report Mask(CALL_PROLOGUES) Target Mask(CALL_PROLOGUES)
Use subroutines for function prologues and epilogues. Use subroutines for function prologues and epilogues.
mmcu= mmcu=
@ -27,7 +27,7 @@ Target RejectNegative Joined Var(avr_mmcu) MissingArgError(missing device or arc
-mmcu=MCU Select the target MCU. -mmcu=MCU Select the target MCU.
mgas-isr-prologues mgas-isr-prologues
Target Report Var(avr_gasisr_prologues) UInteger Init(0) Target Var(avr_gasisr_prologues) UInteger Init(0)
Allow usage of __gcc_isr pseudo instructions in ISR prologues and epilogues. Allow usage of __gcc_isr pseudo instructions in ISR prologues and epilogues.
mn-flash= mn-flash=
@ -35,100 +35,100 @@ Target RejectNegative Joined Var(avr_n_flash) UInteger Init(-1)
Set the number of 64 KiB flash segments. Set the number of 64 KiB flash segments.
mskip-bug mskip-bug
Target Report Mask(SKIP_BUG) Target Mask(SKIP_BUG)
Indicate presence of a processor erratum. Indicate presence of a processor erratum.
mrmw mrmw
Target Report Mask(RMW) Target Mask(RMW)
Enable Read-Modify-Write (RMW) instructions support/use. Enable Read-Modify-Write (RMW) instructions support/use.
mdeb mdeb
Target Report Undocumented Mask(ALL_DEBUG) Target Undocumented Mask(ALL_DEBUG)
mlog= mlog=
Target RejectNegative Joined Undocumented Var(avr_log_details) Target RejectNegative Joined Undocumented Var(avr_log_details)
mshort-calls mshort-calls
Target Report RejectNegative Mask(SHORT_CALLS) Target RejectNegative Mask(SHORT_CALLS)
Use RJMP / RCALL even though CALL / JMP are available. Use RJMP / RCALL even though CALL / JMP are available.
mint8 mint8
Target Report Mask(INT8) Target Mask(INT8)
Use an 8-bit 'int' type. Use an 8-bit 'int' type.
mno-interrupts mno-interrupts
Target Report RejectNegative Mask(NO_INTERRUPTS) Target RejectNegative Mask(NO_INTERRUPTS)
Change the stack pointer without disabling interrupts. Change the stack pointer without disabling interrupts.
mbranch-cost= mbranch-cost=
Target Report Joined RejectNegative UInteger Var(avr_branch_cost) Init(0) Target Joined RejectNegative UInteger Var(avr_branch_cost) Init(0)
Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 0. Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 0.
mmain-is-OS_task mmain-is-OS_task
Target Report Mask(MAIN_IS_OS_TASK) Target Mask(MAIN_IS_OS_TASK)
Treat main as if it had attribute OS_task. Treat main as if it had attribute OS_task.
morder1 morder1
Target Report Undocumented Mask(ORDER_1) Target Undocumented Mask(ORDER_1)
morder2 morder2
Target Report Undocumented Mask(ORDER_2) Target Undocumented Mask(ORDER_2)
mtiny-stack mtiny-stack
Target Report Mask(TINY_STACK) Target Mask(TINY_STACK)
Change only the low 8 bits of the stack pointer. Change only the low 8 bits of the stack pointer.
mrelax mrelax
Target Report Target
Relax branches. Relax branches.
mpmem-wrap-around mpmem-wrap-around
Target Report Target
Make the linker relaxation machine assume that a program counter wrap-around occurs. Make the linker relaxation machine assume that a program counter wrap-around occurs.
maccumulate-args maccumulate-args
Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Target Mask(ACCUMULATE_OUTGOING_ARGS)
Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf. Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf.
mstrict-X mstrict-X
Target Report Var(avr_strict_X) Init(0) Target Var(avr_strict_X) Init(0)
When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X. When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X.
;; For rationale behind -msp8 see explanation in avr.h. ;; For rationale behind -msp8 see explanation in avr.h.
msp8 msp8
Target Report RejectNegative Var(avr_sp8) Init(0) Target RejectNegative Var(avr_sp8) Init(0)
The device has no SPH special function register. This option will be overridden by the compiler driver with the correct setting if presence/absence of SPH can be deduced from -mmcu=MCU. The device has no SPH special function register. This option will be overridden by the compiler driver with the correct setting if presence/absence of SPH can be deduced from -mmcu=MCU.
Waddr-space-convert Waddr-space-convert
Warning C Report Var(avr_warn_addr_space_convert) Init(0) Warning C Var(avr_warn_addr_space_convert) Init(0)
Warn if the address space of an address is changed. Warn if the address space of an address is changed.
Wmisspelled-isr Wmisspelled-isr
Warning C C++ Report Var(avr_warn_misspelled_isr) Init(1) Warning C C++ Var(avr_warn_misspelled_isr) Init(1)
Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default. Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default.
mfract-convert-truncate mfract-convert-truncate
Target Report Mask(FRACT_CONV_TRUNC) Target Mask(FRACT_CONV_TRUNC)
Allow to use truncation instead of rounding towards zero for fractional fixed-point types. Allow to use truncation instead of rounding towards zero for fractional fixed-point types.
mabsdata mabsdata
Target Report Mask(ABSDATA) Target Mask(ABSDATA)
Assume that all data in static storage can be accessed by LDS / STS. This option is only useful for reduced Tiny devices. Assume that all data in static storage can be accessed by LDS / STS. This option is only useful for reduced Tiny devices.
mdouble= mdouble=
Target Report Joined RejectNegative Var(avr_double) Init(0) Enum(avr_bits_e) Target Joined RejectNegative Var(avr_double) Init(0) Enum(avr_bits_e)
-mdouble=<BITS> Use <BITS> bits wide double type. -mdouble=<BITS> Use <BITS> bits wide double type.
mlong-double= mlong-double=
Target Report Joined RejectNegative Var(avr_long_double) Init(0) Enum(avr_bits_e) Target Joined RejectNegative Var(avr_long_double) Init(0) Enum(avr_bits_e)
-mlong-double=<BITS> Use <BITS> bits wide long double type. -mlong-double=<BITS> Use <BITS> bits wide long double type.
nodevicelib nodevicelib
Driver Target Report RejectNegative Driver Target RejectNegative
Do not link against the device-specific library lib<MCU>.a. Do not link against the device-specific library lib<MCU>.a.
nodevicespecs nodevicespecs
Driver Target Report RejectNegative Driver Target RejectNegative
Do not use the device-specific specs file device-specs/specs-<MCU>. Do not use the device-specific specs file device-specs/specs-<MCU>.
Enum Enum

34
gcc/config/bfin/bfin.opt
View File

@ -44,28 +44,28 @@ Target RejectNegative Joined
Specify the name of the target CPU. Specify the name of the target CPU.
momit-leaf-frame-pointer momit-leaf-frame-pointer
Target Report Mask(OMIT_LEAF_FRAME_POINTER) Target Mask(OMIT_LEAF_FRAME_POINTER)
Omit frame pointer for leaf functions. Omit frame pointer for leaf functions.
mlow64k mlow64k
Target Report Mask(LOW_64K) Target Mask(LOW_64K)
Program is entirely located in low 64k of memory. Program is entirely located in low 64k of memory.
mcsync-anomaly mcsync-anomaly
Target Report Var(bfin_csync_anomaly) Init(-1) Target Var(bfin_csync_anomaly) Init(-1)
Work around a hardware anomaly by adding a number of NOPs before a Work around a hardware anomaly by adding a number of NOPs before a
CSYNC or SSYNC instruction. CSYNC or SSYNC instruction.
mspecld-anomaly mspecld-anomaly
Target Report Var(bfin_specld_anomaly) Init(-1) Target Var(bfin_specld_anomaly) Init(-1)
Avoid speculative loads to work around a hardware anomaly. Avoid speculative loads to work around a hardware anomaly.
mid-shared-library mid-shared-library
Target Report Mask(ID_SHARED_LIBRARY) Target Mask(ID_SHARED_LIBRARY)
Enabled ID based shared library. Enabled ID based shared library.
mleaf-id-shared-library mleaf-id-shared-library
Target Report Mask(LEAF_ID_SHARED_LIBRARY) Target Mask(LEAF_ID_SHARED_LIBRARY)
Generate code that won't be linked against any other ID shared libraries, Generate code that won't be linked against any other ID shared libraries,
but may be used as a shared library. but may be used as a shared library.
@ -74,45 +74,45 @@ Target RejectNegative Joined UInteger Var(bfin_library_id)
ID of shared library to build. ID of shared library to build.
msep-data msep-data
Target Report Mask(SEP_DATA) Target Mask(SEP_DATA)
Enable separate data segment. Enable separate data segment.
mlong-calls mlong-calls
Target Report Mask(LONG_CALLS) Target Mask(LONG_CALLS)
Avoid generating pc-relative calls; use indirection. Avoid generating pc-relative calls; use indirection.
mfast-fp mfast-fp
Target Report Mask(FAST_FP) Target Mask(FAST_FP)
Link with the fast floating-point library. Link with the fast floating-point library.
mfdpic mfdpic
Target Report Mask(FDPIC) Target Mask(FDPIC)
Enable Function Descriptor PIC mode. Enable Function Descriptor PIC mode.
minline-plt minline-plt
Target Report Mask(INLINE_PLT) Target Mask(INLINE_PLT)
Enable inlining of PLT in function calls. Enable inlining of PLT in function calls.
mstack-check-l1 mstack-check-l1
Target Report Mask(STACK_CHECK_L1) Target Mask(STACK_CHECK_L1)
Do stack checking using bounds in L1 scratch memory. Do stack checking using bounds in L1 scratch memory.
mmulticore mmulticore
Target Report Mask(MULTICORE) Target Mask(MULTICORE)
Enable multicore support. Enable multicore support.
mcorea mcorea
Target Report Mask(COREA) Target Mask(COREA)
Build for Core A. Build for Core A.
mcoreb mcoreb
Target Report Mask(COREB) Target Mask(COREB)
Build for Core B. Build for Core B.
msdram msdram
Target Report Mask(SDRAM) Target Mask(SDRAM)
Build for SDRAM. Build for SDRAM.
micplb micplb
Target Report Mask(ICPLB) Target Mask(ICPLB)
Assume ICPLBs are enabled at runtime. Assume ICPLBs are enabled at runtime.

6
gcc/config/bpf/bpf.opt
View File

@ -111,17 +111,17 @@ Enum(bpf_kernel) String(5.2) Value(LINUX_V5_2)
; Use xBPF extensions. ; Use xBPF extensions.
mxbpf mxbpf
Target Report Mask(XBPF) Target Mask(XBPF)
Generate xBPF. Generate xBPF.
; Selecting big endian or little endian targets. ; Selecting big endian or little endian targets.
mbig-endian mbig-endian
Target RejectNegative Report Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Generate big-endian eBPF. Generate big-endian eBPF.
mlittle-endian mlittle-endian
Target RejectNegative Report InverseMask(BIG_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN)
Generate little-endian eBPF. Generate little-endian eBPF.
mframe-limit= mframe-limit=

6
gcc/config/c6x/c6x.opt
View File

@ -26,11 +26,11 @@ SourceInclude
config/c6x/c6x-opts.h config/c6x/c6x-opts.h
mbig-endian mbig-endian
Target Report RejectNegative Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order. Use big-endian byte order.
mlittle-endian mlittle-endian
Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
Use little-endian byte order. Use little-endian byte order.
msim msim
@ -59,7 +59,7 @@ Target Mask(DSBT)
Compile for the DSBT shared library ABI. Compile for the DSBT shared library ABI.
mlong-calls mlong-calls
Target Report Mask(LONG_CALLS) Target Mask(LONG_CALLS)
Avoid generating pc-relative calls; use indirection. Avoid generating pc-relative calls; use indirection.
march= march=

4
gcc/config/cr16/cr16.opt
View File

@ -23,11 +23,11 @@ Target
Use simulator runtime. Use simulator runtime.
mbit-ops mbit-ops
Target Report Mask(BIT_OPS) Target Mask(BIT_OPS)
Generate SBIT, CBIT instructions. Generate SBIT, CBIT instructions.
mmac mmac
Target Report Mask(MAC) Target Mask(MAC)
Support multiply accumulate instructions. Support multiply accumulate instructions.
mdebug-addr mdebug-addr

64
gcc/config/cris/cris.opt
View File

@ -41,111 +41,111 @@
; driver-like program that gets a mapping of I/O registers (all ; driver-like program that gets a mapping of I/O registers (all
; on the same page, including the TLB registers). ; on the same page, including the TLB registers).
mmul-bug-workaround mmul-bug-workaround
Target Report Mask(MUL_BUG) Target Mask(MUL_BUG)
Work around bug in multiplication instruction. Work around bug in multiplication instruction.
; TARGET_ETRAX4_ADD: Instruction-set additions from Etrax 4 and up. ; TARGET_ETRAX4_ADD: Instruction-set additions from Etrax 4 and up.
; (Just "lz".) ; (Just "lz".)
metrax4 metrax4
Target Report Mask(ETRAX4_ADD) Target Mask(ETRAX4_ADD)
Compile for ETRAX 4 (CRIS v3). Compile for ETRAX 4 (CRIS v3).
; See cris_handle_option. ; See cris_handle_option.
metrax100 metrax100
Target Report RejectNegative Target RejectNegative
Compile for ETRAX 100 (CRIS v8). Compile for ETRAX 100 (CRIS v8).
; See cris_handle_option. ; See cris_handle_option.
mno-etrax100 mno-etrax100
Target Report RejectNegative Undocumented Target RejectNegative Undocumented
mpdebug mpdebug
Target Report Mask(PDEBUG) Target Mask(PDEBUG)
Emit verbose debug information in assembly code. Emit verbose debug information in assembly code.
; TARGET_CCINIT: Whether to use condition-codes generated by ; TARGET_CCINIT: Whether to use condition-codes generated by
; insns other than the immediately preceding compare/test insn. ; insns other than the immediately preceding compare/test insn.
; Used to check for errors in notice_update_cc. ; Used to check for errors in notice_update_cc.
mcc-init mcc-init
Target Report Mask(CCINIT) Target Mask(CCINIT)
Do not use condition codes from normal instructions. Do not use condition codes from normal instructions.
; TARGET_SIDE_EFFECT_PREFIXES: Whether to use side-effect ; TARGET_SIDE_EFFECT_PREFIXES: Whether to use side-effect
; patterns. Used to debug the [rx=ry+i] type patterns. ; patterns. Used to debug the [rx=ry+i] type patterns.
mside-effects mside-effects
Target Report RejectNegative Mask(SIDE_EFFECT_PREFIXES) Undocumented Target RejectNegative Mask(SIDE_EFFECT_PREFIXES) Undocumented
mno-side-effects mno-side-effects
Target Report RejectNegative InverseMask(SIDE_EFFECT_PREFIXES) Target RejectNegative InverseMask(SIDE_EFFECT_PREFIXES)
Do not emit addressing modes with side-effect assignment. Do not emit addressing modes with side-effect assignment.
; TARGET_STACK_ALIGN: Whether to *keep* (not force) alignment of ; TARGET_STACK_ALIGN: Whether to *keep* (not force) alignment of
; stack at 16 (or 32, depending on TARGET_ALIGN_BY_32) bits. ; stack at 16 (or 32, depending on TARGET_ALIGN_BY_32) bits.
mstack-align mstack-align
Target Report RejectNegative Mask(STACK_ALIGN) Undocumented Target RejectNegative Mask(STACK_ALIGN) Undocumented
mno-stack-align mno-stack-align
Target Report RejectNegative InverseMask(STACK_ALIGN) Target RejectNegative InverseMask(STACK_ALIGN)
Do not tune stack alignment. Do not tune stack alignment.
; TARGET_DATA_ALIGN: Whether to do alignment on individual ; TARGET_DATA_ALIGN: Whether to do alignment on individual
; modifiable objects. ; modifiable objects.
mdata-align mdata-align
Target Report RejectNegative Mask(DATA_ALIGN) Undocumented Target RejectNegative Mask(DATA_ALIGN) Undocumented
mno-data-align mno-data-align
Target Report RejectNegative InverseMask(DATA_ALIGN) Target RejectNegative InverseMask(DATA_ALIGN)
Do not tune writable data alignment. Do not tune writable data alignment.
; TARGET_CONST_ALIGN: Whether to do alignment on individual ; TARGET_CONST_ALIGN: Whether to do alignment on individual
; non-modifiable objects. ; non-modifiable objects.
mconst-align mconst-align
Target Report RejectNegative Mask(CONST_ALIGN) Undocumented Target RejectNegative Mask(CONST_ALIGN) Undocumented
mno-const-align mno-const-align
Target Report RejectNegative InverseMask(CONST_ALIGN) Target RejectNegative InverseMask(CONST_ALIGN)
Do not tune code and read-only data alignment. Do not tune code and read-only data alignment.
; See cris_handle_option. ; See cris_handle_option.
m32-bit m32-bit
Target Report RejectNegative Undocumented Target RejectNegative Undocumented
; See cris_handle_option. ; See cris_handle_option.
m32bit m32bit
Target Report RejectNegative Target RejectNegative
Align code and data to 32 bits. Align code and data to 32 bits.
; See cris_handle_option. ; See cris_handle_option.
m16-bit m16-bit
Target Report RejectNegative Undocumented Target RejectNegative Undocumented
; See cris_handle_option. ; See cris_handle_option.
m16bit m16bit
Target Report RejectNegative Undocumented Target RejectNegative Undocumented
; See cris_handle_option. ; See cris_handle_option.
m8-bit m8-bit
Target Report RejectNegative Undocumented Target RejectNegative Undocumented
; See cris_handle_option. ; See cris_handle_option.
m8bit m8bit
Target Report RejectNegative Target RejectNegative
Don't align items in code or data. Don't align items in code or data.
; TARGET_PROLOGUE_EPILOGUE: Whether or not to omit function ; TARGET_PROLOGUE_EPILOGUE: Whether or not to omit function
; prologue and epilogue. ; prologue and epilogue.
mprologue-epilogue mprologue-epilogue
Target Report RejectNegative Mask(PROLOGUE_EPILOGUE) Undocumented Target RejectNegative Mask(PROLOGUE_EPILOGUE) Undocumented
mno-prologue-epilogue mno-prologue-epilogue
Target Report RejectNegative InverseMask(PROLOGUE_EPILOGUE) Target RejectNegative InverseMask(PROLOGUE_EPILOGUE)
Do not emit function prologue or epilogue. Do not emit function prologue or epilogue.
; We have to handle this m-option here since we can't wash it ; We have to handle this m-option here since we can't wash it
; off in both CC1_SPEC and CC1PLUS_SPEC. ; off in both CC1_SPEC and CC1PLUS_SPEC.
mbest-lib-options mbest-lib-options
Target Report RejectNegative Target RejectNegative
Use the most feature-enabling options allowed by other options. Use the most feature-enabling options allowed by other options.
; FIXME: The following comment relates to gcc before cris.opt. ; FIXME: The following comment relates to gcc before cris.opt.
@ -154,37 +154,37 @@ Use the most feature-enabling options allowed by other options.
; gcc.c to forget it, if there's a "later" -mbest-lib-options. ; gcc.c to forget it, if there's a "later" -mbest-lib-options.
; Kludgy, but needed for some multilibbed files. ; Kludgy, but needed for some multilibbed files.
moverride-best-lib-options moverride-best-lib-options
Target Report RejectNegative Target RejectNegative
Override -mbest-lib-options. Override -mbest-lib-options.
mcpu= mcpu=
Target Report RejectNegative Joined Undocumented Var(cris_cpu_str) Target RejectNegative Joined Undocumented Var(cris_cpu_str)
march= march=
Target Report RejectNegative Joined Var(cris_cpu_str) Target RejectNegative Joined Var(cris_cpu_str)
-march=ARCH Generate code for the specified chip or CPU version. -march=ARCH Generate code for the specified chip or CPU version.
mtune= mtune=
Target Report RejectNegative Joined Var(cris_tune_str) Target RejectNegative Joined Var(cris_tune_str)
-mtune=ARCH Tune alignment for the specified chip or CPU version. -mtune=ARCH Tune alignment for the specified chip or CPU version.
mmax-stackframe= mmax-stackframe=
Target Report RejectNegative Joined Var(cris_max_stackframe_str) Target RejectNegative Joined Var(cris_max_stackframe_str)
-mmax-stackframe=SIZE Warn when a stackframe is larger than the specified size. -mmax-stackframe=SIZE Warn when a stackframe is larger than the specified size.
max-stackframe= max-stackframe=
Target Report RejectNegative Joined Undocumented Var(cris_max_stackframe_str) Target RejectNegative Joined Undocumented Var(cris_max_stackframe_str)
mtrap-using-break8 mtrap-using-break8
Target Report Var(cris_trap_using_break8) Init(2) Target Var(cris_trap_using_break8) Init(2)
Emit traps as \"break 8\", default for CRIS v3 and up. If disabled, calls to abort() are used. Emit traps as \"break 8\", default for CRIS v3 and up. If disabled, calls to abort() are used.
mtrap-unaligned-atomic mtrap-unaligned-atomic
Target Report Var(cris_trap_unaligned_atomic) Init(2) Target Var(cris_trap_unaligned_atomic) Init(2)
Emit checks causing \"break 8\" instructions to execute when applying atomic builtins on misaligned memory. Emit checks causing \"break 8\" instructions to execute when applying atomic builtins on misaligned memory.
munaligned-atomic-may-use-library munaligned-atomic-may-use-library
Target Report Var(cris_atomics_calling_libfunc) Init(2) Target Var(cris_atomics_calling_libfunc) Init(2)
Handle atomic builtins that may be applied to unaligned data by calling library functions. Overrides -mtrap-unaligned-atomic. Handle atomic builtins that may be applied to unaligned data by calling library functions. Overrides -mtrap-unaligned-atomic.
; TARGET_SVINTO: Currently this just affects alignment. FIXME: ; TARGET_SVINTO: Currently this just affects alignment. FIXME:

2
gcc/config/cris/elf.opt
View File

@ -19,7 +19,7 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
melf melf
Target Report RejectNegative Undocumented Target RejectNegative Undocumented
sim sim
Driver JoinedOrMissing Driver JoinedOrMissing

60
gcc/config/csky/csky.opt
View File

@ -27,7 +27,7 @@ config/csky/csky_opts.h
; For backward compatibility only. ; For backward compatibility only.
march=ck803s march=ck803s
Target Report Var(flag_arch_ck803s) Undocumented Target Var(flag_arch_ck803s) Undocumented
march= march=
Target RejectNegative ToLower Joined Enum(csky_arch) Var(csky_arch_option) Save Target RejectNegative ToLower Joined Enum(csky_arch) Var(csky_arch_option) Save
@ -40,18 +40,18 @@ Specify the target processor.
;; Endianness options. ;; Endianness options.
mbig-endian mbig-endian
Target RejectNegative Report Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Generate big-endian code. Generate big-endian code.
EB EB
Target RejectNegative Report Alias(mbig-endian) Undocumented Target RejectNegative Alias(mbig-endian) Undocumented
mlittle-endian mlittle-endian
Target RejectNegative Report InverseMask(BIG_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN)
Generate little-endian code. Generate little-endian code.
EL EL
Target RejectNegative Report Alias(mlittle-endian) Undocumented Target RejectNegative Alias(mlittle-endian) Undocumented
;; Floating point options. These affect code generation but not ;; Floating point options. These affect code generation but not
;; assembly. ;; assembly.
@ -90,11 +90,11 @@ Target RejectNegative Joined Enum(csky_fpu) Var(csky_fpu_index) Init(TARGET_FPU_
Specify the target floating-point hardware/format. Specify the target floating-point hardware/format.
mdouble-float mdouble-float
Target Report Var(TARGET_DOUBLE_FLOAT) Init(-1) Target Var(TARGET_DOUBLE_FLOAT) Init(-1)
Generate C-SKY FPU double float instructions (default for hard float). Generate C-SKY FPU double float instructions (default for hard float).
mfdivdu mfdivdu
Target Report Var(TARGET_FDIVDU) Init(-1) Target Var(TARGET_FDIVDU) Init(-1)
Generate frecipd/fsqrtd/fdivd instructions (default for hard float). Generate frecipd/fsqrtd/fdivd instructions (default for hard float).
;; Instruction set extensions. Most of these don't affect code ;; Instruction set extensions. Most of these don't affect code
@ -102,95 +102,95 @@ Generate frecipd/fsqrtd/fdivd instructions (default for hard float).
;; There are builtin preprocessor defines for each of these. ;; There are builtin preprocessor defines for each of these.
melrw melrw
Target Report Var(TARGET_ELRW) Init(-1) Target Var(TARGET_ELRW) Init(-1)
Enable the extended LRW instruction (default for CK801). Enable the extended LRW instruction (default for CK801).
mistack mistack
Target Report Mask(ISTACK) Target Mask(ISTACK)
Enable interrupt stack instructions. Enable interrupt stack instructions.
mmp mmp
Target Report RejectNegative Mask(MP) Target RejectNegative Mask(MP)
Enable multiprocessor instructions. Enable multiprocessor instructions.
mcp mcp
Target Report RejectNegative Mask(CP) Target RejectNegative Mask(CP)
Enable coprocessor instructions. Enable coprocessor instructions.
mcache mcache
Target Report RejectNegative Mask(CACHE) Target RejectNegative Mask(CACHE)
Enable cache prefetch instructions. Enable cache prefetch instructions.
msecurity msecurity
Target Report RejectNegative Mask(SECURITY) Target RejectNegative Mask(SECURITY)
Enable C-SKY SECURE instructions. Enable C-SKY SECURE instructions.
mmac mmac
Target Report RejectNegative Alias(msecurity) Undocumented Target RejectNegative Alias(msecurity) Undocumented
mtrust mtrust
Target Report RejectNegative Mask(TRUST) Target RejectNegative Mask(TRUST)
Enable C-SKY TRUST instructions. Enable C-SKY TRUST instructions.
mdsp mdsp
Target Report RejectNegative Var(TARGET_DSP) Target RejectNegative Var(TARGET_DSP)
Enable C-SKY DSP instructions. Enable C-SKY DSP instructions.
medsp medsp
Target Report RejectNegative Mask(EDSP) Target RejectNegative Mask(EDSP)
Enable C-SKY Enhanced DSP instructions. Enable C-SKY Enhanced DSP instructions.
mvdsp mvdsp
Target Report RejectNegative Mask(VDSP) Target RejectNegative Mask(VDSP)
Enable C-SKY Vector DSP instructions. Enable C-SKY Vector DSP instructions.
;; Code generation options not passed to the assembler. ;; Code generation options not passed to the assembler.
mdiv mdiv
Target Report Var(TARGET_DIV) Init(-1) Target Var(TARGET_DIV) Init(-1)
Generate divide instructions. Generate divide instructions.
msmart msmart
Target Report Var(TARGET_MINI_REGISTERS) Init(-1) Target Var(TARGET_MINI_REGISTERS) Init(-1)
Generate code for Smart Mode. Generate code for Smart Mode.
mhigh-registers mhigh-registers
Target Report Var(TARGET_HIGH_REGISTERS) Init(-1) Target Var(TARGET_HIGH_REGISTERS) Init(-1)
Enable use of R16-R31 (default). Enable use of R16-R31 (default).
manchor manchor
Target Report Var(TARGET_ANCHOR) Target Var(TARGET_ANCHOR)
Generate code using global anchor symbol addresses. Generate code using global anchor symbol addresses.
mpushpop mpushpop
Target Report Var(TARGET_PUSHPOP) Init(1) Target Var(TARGET_PUSHPOP) Init(1)
Generate push/pop instructions (default). Generate push/pop instructions (default).
mmultiple-stld mmultiple-stld
Target Report Var(TARGET_MULTIPLE_STLD) Init(-1) Target Var(TARGET_MULTIPLE_STLD) Init(-1)
Generate stm/ldm instructions (default). Generate stm/ldm instructions (default).
mstm mstm
Target Report Alias(mmultiple-stld) Undocumented Target Alias(mmultiple-stld) Undocumented
mconstpool mconstpool
Target Report Var(TARGET_CONSTANT_POOL) Init(-1) Target Var(TARGET_CONSTANT_POOL) Init(-1)
Generate constant pools in the compiler instead of assembler. Generate constant pools in the compiler instead of assembler.
mstack-size mstack-size
Target Report Var(TARGET_STACK_SIZE) Init(0) Target Var(TARGET_STACK_SIZE) Init(0)
Emit .stack_size directives. Emit .stack_size directives.
mccrt mccrt
Target Report Var(TARGET_LIBCCRT) Init(0) Target Var(TARGET_LIBCCRT) Init(0)
Generate code for C-SKY compiler runtime instead of libgcc. Generate code for C-SKY compiler runtime instead of libgcc.
mbranch-cost= mbranch-cost=
Target Report Joined RejectNegative UInteger Var(csky_branch_cost) Init(1) Target Joined RejectNegative UInteger Var(csky_branch_cost) Init(1)
Set the branch costs to roughly the specified number of instructions. Set the branch costs to roughly the specified number of instructions.
msched-prolog msched-prolog
Target Report Var(flag_sched_prolog) Init(0) Target Var(flag_sched_prolog) Init(0)
Permit scheduling of function prologue and epilogue sequences. Permit scheduling of function prologue and epilogue sequences.
msim msim

24
gcc/config/darwin.opt
View File

@ -30,7 +30,7 @@ dependency-file
C ObjC C++ ObjC++ Separate Alias(MF) MissingArgError(missing filename after %qs) C ObjC C++ ObjC++ Separate Alias(MF) MissingArgError(missing filename after %qs)
fapple-kext fapple-kext
Target Report C++ Var(flag_apple_kext) Target C++ Var(flag_apple_kext)
Generate code for darwin loadable kernel extensions. Generate code for darwin loadable kernel extensions.
iframework iframework
@ -38,28 +38,28 @@ Target RejectNegative C ObjC C++ ObjC++ Joined Separate
-iframework <dir> Add <dir> to the end of the system framework include path. -iframework <dir> Add <dir> to the end of the system framework include path.
mconstant-cfstrings mconstant-cfstrings
Target Report Var(darwin_constant_cfstrings) Init(1) Target Var(darwin_constant_cfstrings) Init(1)
Generate compile-time CFString objects. Generate compile-time CFString objects.
Wnonportable-cfstrings Wnonportable-cfstrings
Target Report Var(darwin_warn_nonportable_cfstrings) Init(1) Warning Target Var(darwin_warn_nonportable_cfstrings) Init(1) Warning
Warn if constant CFString objects contain non-portable characters. Warn if constant CFString objects contain non-portable characters.
; Use new-style pic stubs if this is true, x86 only so far. ; Use new-style pic stubs if this is true, x86 only so far.
matt-stubs matt-stubs
Target Report Var(darwin_macho_att_stub) Init(1) Target Var(darwin_macho_att_stub) Init(1)
Generate AT&T-style stubs for Mach-O. Generate AT&T-style stubs for Mach-O.
mdynamic-no-pic mdynamic-no-pic
Target Common Report Mask(MACHO_DYNAMIC_NO_PIC) Target Common Mask(MACHO_DYNAMIC_NO_PIC)
Generate code suitable for executables (NOT shared libs). Generate code suitable for executables (NOT shared libs).
mfix-and-continue mfix-and-continue
Target Report Var(darwin_fix_and_continue) Target Var(darwin_fix_and_continue)
Generate code suitable for fast turn around debugging. Generate code suitable for fast turn around debugging.
mkernel mkernel
Target Report Var(flag_mkernel) Target Var(flag_mkernel)
Generate code for the kernel or loadable kernel extensions. Generate code for the kernel or loadable kernel extensions.
; The Init here is for the convenience of GCC developers, so that cc1 ; The Init here is for the convenience of GCC developers, so that cc1
@ -67,24 +67,24 @@ Generate code for the kernel or loadable kernel extensions.
; driver will always pass a -mmacosx-version-min, so in normal use the ; driver will always pass a -mmacosx-version-min, so in normal use the
; Init is never used. ; Init is never used.
mmacosx-version-min= mmacosx-version-min=
Target RejectNegative Joined Report Var(darwin_macosx_version_min) Init(DEF_MIN_OSX_VERSION) Target RejectNegative Joined Var(darwin_macosx_version_min) Init(DEF_MIN_OSX_VERSION)
The earliest macOS version on which this program will run. The earliest macOS version on which this program will run.
; Really, only relevant to PowerPC which has a 4 byte bool by default. ; Really, only relevant to PowerPC which has a 4 byte bool by default.
mone-byte-bool mone-byte-bool
Target RejectNegative Report Var(darwin_one_byte_bool) Target RejectNegative Var(darwin_one_byte_bool)
Set sizeof(bool) to 1. Set sizeof(bool) to 1.
msymbol-stubs msymbol-stubs
Target Report Var(darwin_symbol_stubs) Init(0) Target Var(darwin_symbol_stubs) Init(0)
Force generation of external symbol indirection stubs. Force generation of external symbol indirection stubs.
; Some code-gen may be improved / adjusted if the linker is sufficiently modern. ; Some code-gen may be improved / adjusted if the linker is sufficiently modern.
mtarget-linker= mtarget-linker=
Target RejectNegative Joined Report Alias(mtarget-linker) Target RejectNegative Joined Alias(mtarget-linker)
mtarget-linker mtarget-linker
Target RejectNegative Joined Separate Report Var(darwin_target_linker) Init(LD64_VERSION) Target RejectNegative Joined Separate Var(darwin_target_linker) Init(LD64_VERSION)
-mtarget-linker <version> Specify that ld64 <version> is the toolchain linker for the current invocation. -mtarget-linker <version> Specify that ld64 <version> is the toolchain linker for the current invocation.
; Driver options. ; Driver options.

2
gcc/config/fr30/fr30.opt
View File

@ -19,7 +19,7 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
msmall-model msmall-model
Target Report Mask(SMALL_MODEL) Target Mask(SMALL_MODEL)
Assume small address space. Assume small address space.
mno-lsim mno-lsim

62
gcc/config/frv/frv.opt
View File

@ -26,19 +26,19 @@ Variable
frv_cpu_t frv_cpu_type = CPU_TYPE frv_cpu_t frv_cpu_type = CPU_TYPE
macc-4 macc-4
Target Report RejectNegative Mask(ACC_4) Target RejectNegative Mask(ACC_4)
Use 4 media accumulators. Use 4 media accumulators.
macc-8 macc-8
Target Report RejectNegative InverseMask(ACC_4, ACC_8) Target RejectNegative InverseMask(ACC_4, ACC_8)
Use 8 media accumulators. Use 8 media accumulators.
malign-labels malign-labels
Target Report Mask(ALIGN_LABELS) Target Mask(ALIGN_LABELS)
Enable label alignment optimizations. Enable label alignment optimizations.
malloc-cc malloc-cc
Target Report RejectNegative Mask(ALLOC_CC) Target RejectNegative Mask(ALLOC_CC)
Dynamically allocate cc registers. Dynamically allocate cc registers.
; We used to default the branch cost to 2, but it was changed it to 1 to avoid ; We used to default the branch cost to 2, but it was changed it to 1 to avoid
@ -49,7 +49,7 @@ Target RejectNegative Joined UInteger Var(frv_branch_cost_int) Init(1)
Set the cost of branches. Set the cost of branches.
mcond-exec mcond-exec
Target Report Mask(COND_EXEC) Target Mask(COND_EXEC)
Enable conditional execution other than moves/scc. Enable conditional execution other than moves/scc.
mcond-exec-insns= mcond-exec-insns=
@ -61,7 +61,7 @@ Target RejectNegative Joined UInteger Var(frv_condexec_temps) Init(4)
Change the number of temporary registers that are available to conditionally-executed sequences. Change the number of temporary registers that are available to conditionally-executed sequences.
mcond-move mcond-move
Target Report Mask(COND_MOVE) Target Mask(COND_MOVE)
Enable conditional moves. Enable conditional moves.
mcpu= mcpu=
@ -118,75 +118,75 @@ mdebug-stack
Target Undocumented Var(TARGET_DEBUG_STACK) Target Undocumented Var(TARGET_DEBUG_STACK)
mdouble mdouble
Target Report Mask(DOUBLE) Target Mask(DOUBLE)
Use fp double instructions. Use fp double instructions.
mdword mdword
Target Report Mask(DWORD) Target Mask(DWORD)
Change the ABI to allow double word insns. Change the ABI to allow double word insns.
mfdpic mfdpic
Target Report Mask(FDPIC) Target Mask(FDPIC)
Enable Function Descriptor PIC mode. Enable Function Descriptor PIC mode.
mfixed-cc mfixed-cc
Target Report RejectNegative InverseMask(ALLOC_CC, FIXED_CC) Target RejectNegative InverseMask(ALLOC_CC, FIXED_CC)
Just use icc0/fcc0. Just use icc0/fcc0.
mfpr-32 mfpr-32
Target Report RejectNegative Mask(FPR_32) Target RejectNegative Mask(FPR_32)
Only use 32 FPRs. Only use 32 FPRs.
mfpr-64 mfpr-64
Target Report RejectNegative InverseMask(FPR_32, FPR_64) Target RejectNegative InverseMask(FPR_32, FPR_64)
Use 64 FPRs. Use 64 FPRs.
mgpr-32 mgpr-32
Target Report RejectNegative Mask(GPR_32) Target RejectNegative Mask(GPR_32)
Only use 32 GPRs. Only use 32 GPRs.
mgpr-64 mgpr-64
Target Report RejectNegative InverseMask(GPR_32, GPR_64) Target RejectNegative InverseMask(GPR_32, GPR_64)
Use 64 GPRs. Use 64 GPRs.
mgprel-ro mgprel-ro
Target Report Mask(GPREL_RO) Target Mask(GPREL_RO)
Enable use of GPREL for read-only data in FDPIC. Enable use of GPREL for read-only data in FDPIC.
mhard-float mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
Use hardware floating point. Use hardware floating point.
minline-plt minline-plt
Target Report Mask(INLINE_PLT) Target Mask(INLINE_PLT)
Enable inlining of PLT in function calls. Enable inlining of PLT in function calls.
mlibrary-pic mlibrary-pic
Target Report Mask(LIBPIC) Target Mask(LIBPIC)
Enable PIC support for building libraries. Enable PIC support for building libraries.
mlinked-fp mlinked-fp
Target Report Mask(LINKED_FP) Target Mask(LINKED_FP)
Follow the EABI linkage requirements. Follow the EABI linkage requirements.
mlong-calls mlong-calls
Target Report Mask(LONG_CALLS) Target Mask(LONG_CALLS)
Disallow direct calls to global functions. Disallow direct calls to global functions.
mmedia mmedia
Target Report Mask(MEDIA) Target Mask(MEDIA)
Use media instructions. Use media instructions.
mmuladd mmuladd
Target Report Mask(MULADD) Target Mask(MULADD)
Use multiply add/subtract instructions. Use multiply add/subtract instructions.
mmulti-cond-exec mmulti-cond-exec
Target Report Mask(MULTI_CE) Target Mask(MULTI_CE)
Enable optimizing &&/|| in conditional execution. Enable optimizing &&/|| in conditional execution.
mnested-cond-exec mnested-cond-exec
Target Report Mask(NESTED_CE) Target Mask(NESTED_CE)
Enable nested conditional execution optimizations. Enable nested conditional execution optimizations.
; Not used by the compiler proper. ; Not used by the compiler proper.
@ -195,15 +195,15 @@ Target RejectNegative
Do not mark ABI switches in e_flags. Do not mark ABI switches in e_flags.
moptimize-membar moptimize-membar
Target Report Mask(OPTIMIZE_MEMBAR) Target Mask(OPTIMIZE_MEMBAR)
Remove redundant membars. Remove redundant membars.
mpack mpack
Target Report Mask(PACK) Target Mask(PACK)
Pack VLIW instructions. Pack VLIW instructions.
mscc mscc
Target Report Mask(SCC) Target Mask(SCC)
Enable setting GPRs to the result of comparisons. Enable setting GPRs to the result of comparisons.
msched-lookahead= msched-lookahead=
@ -211,15 +211,15 @@ Target RejectNegative Joined UInteger Var(frv_sched_lookahead) Init(4)
Change the amount of scheduler lookahead. Change the amount of scheduler lookahead.
msoft-float msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT) Target RejectNegative Mask(SOFT_FLOAT)
Use software floating point. Use software floating point.
mTLS mTLS
Target Report RejectNegative Mask(BIG_TLS) Target RejectNegative Mask(BIG_TLS)
Assume a large TLS segment. Assume a large TLS segment.
mtls mtls
Target Report RejectNegative InverseMask(BIG_TLS) Target RejectNegative InverseMask(BIG_TLS)
Do not assume a large TLS segment. Do not assume a large TLS segment.
; Not used by the compiler proper. ; Not used by the compiler proper.
@ -233,5 +233,5 @@ Target RejectNegative
Link with the library-pic libraries. Link with the library-pic libraries.
mvliw-branch mvliw-branch
Target Report Mask(VLIW_BRANCH) Target Mask(VLIW_BRANCH)
Allow branches to be packed with other instructions. Allow branches to be packed with other instructions.

12
gcc/config/ft32/ft32.opt
View File

@ -19,25 +19,25 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
msim msim
Target Report Mask(SIM) Target Mask(SIM)
Target the software simulator. Target the software simulator.
mlra mlra
Target Report Var(ft32_lra_flag) Init(0) Save Target Var(ft32_lra_flag) Init(0) Save
Use LRA instead of reload. Use LRA instead of reload.
mnodiv mnodiv
Target Report Mask(NODIV) Target Mask(NODIV)
Avoid use of the DIV and MOD instructions. Avoid use of the DIV and MOD instructions.
mft32b mft32b
Target Report Mask(FT32B) Target Mask(FT32B)
Target the FT32B architecture. Target the FT32B architecture.
mcompress mcompress
Target Report Mask(COMPRESS) Target Mask(COMPRESS)
Enable FT32B code compression. Enable FT32B code compression.
mnopm mnopm
Target Report Mask(NOPM) Target Mask(NOPM)
Avoid placing any readable data in program memory. Avoid placing any readable data in program memory.

12
gcc/config/gcn/gcn.opt
View File

@ -43,31 +43,31 @@ Target RejectNegative Joined ToLower Enum(gpu_type) Var(gcn_tune) Init(PROCESSOR
Specify the name of the target GPU. Specify the name of the target GPU.
m32 m32
Target Report RejectNegative InverseMask(ABI64) Target RejectNegative InverseMask(ABI64)
Generate code for a 32-bit ABI. Generate code for a 32-bit ABI.
m64 m64
Target Report RejectNegative Mask(ABI64) Target RejectNegative Mask(ABI64)
Generate code for a 64-bit ABI. Generate code for a 64-bit ABI.
mgomp mgomp
Target Report RejectNegative Target RejectNegative
Enable OpenMP GPU offloading. Enable OpenMP GPU offloading.
bool flag_bypass_init_error = false bool flag_bypass_init_error = false
mbypass-init-error mbypass-init-error
Target Report RejectNegative Var(flag_bypass_init_error) Target RejectNegative Var(flag_bypass_init_error)
bool flag_worker_partitioning = false bool flag_worker_partitioning = false
macc-experimental-workers macc-experimental-workers
Target Report Var(flag_worker_partitioning) Init(0) Target Var(flag_worker_partitioning) Init(0)
int stack_size_opt = -1 int stack_size_opt = -1
mstack-size= mstack-size=
Target Report RejectNegative Joined UInteger Var(stack_size_opt) Init(-1) Target RejectNegative Joined UInteger Var(stack_size_opt) Init(-1)
-mstack-size=<number> Set the private segment size per wave-front, in bytes. -mstack-size=<number> Set the private segment size per wave-front, in bytes.
Wopenacc-dims Wopenacc-dims

6
gcc/config/i386/cygming.opt
View File

@ -27,7 +27,7 @@ Target RejectNegative
Generate code for a DLL. Generate code for a DLL.
mnop-fun-dllimport mnop-fun-dllimport
Target Report Var(TARGET_NOP_FUN_DLLIMPORT) Target Var(TARGET_NOP_FUN_DLLIMPORT)
Ignore dllimport for functions. Ignore dllimport for functions.
mthreads mthreads
@ -51,14 +51,14 @@ Target Condition({defined (USE_CYGWIN_LIBSTDCXX_WRAPPERS)})
Compile code that relies on Cygwin DLL wrappers to support C++ operator new/delete replacement. Compile code that relies on Cygwin DLL wrappers to support C++ operator new/delete replacement.
fset-stack-executable fset-stack-executable
Common Report Var(flag_setstackexecutable) Init(1) Optimization Common Var(flag_setstackexecutable) Init(1) Optimization
For nested functions on stack executable permission is set. For nested functions on stack executable permission is set.
posix posix
Driver Driver
fwritable-relocated-rdata fwritable-relocated-rdata
Common Report Var(flag_writable_rel_rdata) Init(0) Common Var(flag_writable_rel_rdata) Init(0)
Put relocated read-only data into .data section. Put relocated read-only data into .data section.
; Retain blank line above ; Retain blank line above

304
gcc/config/i386/i386.opt
View File

@ -194,35 +194,35 @@ enum ix86_veclibabi x_ix86_veclibabi_type
;; x86 options ;; x86 options
m128bit-long-double m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save Target RejectNegative Mask(128BIT_LONG_DOUBLE) Save
sizeof(long double) is 16. sizeof(long double) is 16.
m80387 m80387
Target Report Mask(80387) Save Target Mask(80387) Save
Use hardware fp. Use hardware fp.
m96bit-long-double m96bit-long-double
Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save Target RejectNegative InverseMask(128BIT_LONG_DOUBLE) Save
sizeof(long double) is 12. sizeof(long double) is 12.
mlong-double-80 mlong-double-80
Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save Target RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
Use 80-bit long double. Use 80-bit long double.
mlong-double-64 mlong-double-64
Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save Target RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
Use 64-bit long double. Use 64-bit long double.
mlong-double-128 mlong-double-128
Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save Target RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
Use 128-bit long double. Use 128-bit long double.
maccumulate-outgoing-args maccumulate-outgoing-args
Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save Target Mask(ACCUMULATE_OUTGOING_ARGS) Save
Reserve space for outgoing arguments in the function prologue. Reserve space for outgoing arguments in the function prologue.
malign-double malign-double
Target Report Mask(ALIGN_DOUBLE) Save Target Mask(ALIGN_DOUBLE) Save
Align some doubles on dword boundary. Align some doubles on dword boundary.
malign-functions= malign-functions=
@ -238,7 +238,7 @@ Target RejectNegative Joined UInteger
Loop code aligned to this power of 2. Loop code aligned to this power of 2.
malign-stringops malign-stringops
Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save Target RejectNegative InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
Align destination of the string operations. Align destination of the string operations.
malign-data= malign-data=
@ -325,15 +325,15 @@ mcpu=
Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
mfancy-math-387 mfancy-math-387
Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save Target RejectNegative InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
Generate sin, cos, sqrt for FPU. Generate sin, cos, sqrt for FPU.
mforce-drap mforce-drap
Target Report Var(ix86_force_drap) Target Var(ix86_force_drap)
Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack.
mfp-ret-in-387 mfp-ret-in-387
Target Report Mask(FLOAT_RETURNS) Save Target Mask(FLOAT_RETURNS) Save
Return values of functions in FPU registers. Return values of functions in FPU registers.
mfpmath= mfpmath=
@ -370,50 +370,50 @@ Target RejectNegative Mask(80387) Save
Use hardware fp. Use hardware fp.
mieee-fp mieee-fp
Target Report Mask(IEEE_FP) Save Target Mask(IEEE_FP) Save
Use IEEE math for fp comparisons. Use IEEE math for fp comparisons.
minline-all-stringops minline-all-stringops
Target Report Mask(INLINE_ALL_STRINGOPS) Save Target Mask(INLINE_ALL_STRINGOPS) Save
Inline all known string operations. Inline all known string operations.
minline-stringops-dynamically minline-stringops-dynamically
Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save Target Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
Inline memset/memcpy string operations, but perform inline version only for small blocks. Inline memset/memcpy string operations, but perform inline version only for small blocks.
mintel-syntax mintel-syntax
Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
mms-bitfields mms-bitfields
Target Report Mask(MS_BITFIELD_LAYOUT) Save Target Mask(MS_BITFIELD_LAYOUT) Save
Use native (MS) bitfield layout. Use native (MS) bitfield layout.
mno-align-stringops mno-align-stringops
Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save Target RejectNegative Mask(NO_ALIGN_STRINGOPS) Undocumented Save
mno-fancy-math-387 mno-fancy-math-387
Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save Target RejectNegative Mask(NO_FANCY_MATH_387) Undocumented Save
mno-push-args mno-push-args
Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save Target RejectNegative Mask(NO_PUSH_ARGS) Undocumented Save
mno-red-zone mno-red-zone
Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save Target RejectNegative Mask(NO_RED_ZONE) Undocumented Save
momit-leaf-frame-pointer momit-leaf-frame-pointer
Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save Target Mask(OMIT_LEAF_FRAME_POINTER) Save
Omit the frame pointer in leaf functions. Omit the frame pointer in leaf functions.
mpc32 mpc32
Target RejectNegative Report Target RejectNegative
Set 80387 floating-point precision to 32-bit. Set 80387 floating-point precision to 32-bit.
mpc64 mpc64
Target RejectNegative Report Target RejectNegative
Set 80387 floating-point precision to 64-bit. Set 80387 floating-point precision to 64-bit.
mpc80 mpc80
Target RejectNegative Report Target RejectNegative
Set 80387 floating-point precision to 80-bit. Set 80387 floating-point precision to 80-bit.
mpreferred-stack-boundary= mpreferred-stack-boundary=
@ -425,11 +425,11 @@ Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
Assume incoming stack aligned to this power of 2. Assume incoming stack aligned to this power of 2.
mpush-args mpush-args
Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save Target InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
Use push instructions to save outgoing arguments. Use push instructions to save outgoing arguments.
mred-zone mred-zone
Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save Target RejectNegative InverseMask(NO_RED_ZONE, RED_ZONE) Save
Use red-zone in the x86-64 code. Use red-zone in the x86-64 code.
mregparm= mregparm=
@ -437,7 +437,7 @@ Target RejectNegative Joined UInteger Var(ix86_regparm)
Number of registers used to pass integer arguments. Number of registers used to pass integer arguments.
mrtd mrtd
Target Report Mask(RTD) Save Target Mask(RTD) Save
Alternate calling convention. Alternate calling convention.
msoft-float msoft-float
@ -449,11 +449,11 @@ Target RejectNegative Mask(SSEREGPARM) Save
Use SSE register passing conventions for SF and DF mode. Use SSE register passing conventions for SF and DF mode.
mstackrealign mstackrealign
Target Report Var(ix86_force_align_arg_pointer) Target Var(ix86_force_align_arg_pointer)
Realign stack in prologue. Realign stack in prologue.
mstack-arg-probe mstack-arg-probe
Target Report Mask(STACK_PROBE) Save Target Mask(STACK_PROBE) Save
Enable stack probing. Enable stack probing.
mmemcpy-strategy= mmemcpy-strategy=
@ -511,7 +511,7 @@ EnumValue
Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
mtls-direct-seg-refs mtls-direct-seg-refs
Target Report Mask(TLS_DIRECT_SEG_REFS) Target Mask(TLS_DIRECT_SEG_REFS)
Use direct references against %gs when accessing tls data. Use direct references against %gs when accessing tls data.
mtune= mtune=
@ -530,7 +530,7 @@ mdump-tune-features
Target RejectNegative Var(ix86_dump_tunes) Target RejectNegative Var(ix86_dump_tunes)
miamcu miamcu
Target Report Mask(IAMCU) Target Mask(IAMCU)
Generate code that conforms to Intel MCU psABI. Generate code that conforms to Intel MCU psABI.
mabi= mabi=
@ -548,7 +548,7 @@ EnumValue
Enum(calling_abi) String(ms) Value(MS_ABI) Enum(calling_abi) String(ms) Value(MS_ABI)
mcall-ms2sysv-xlogues mcall-ms2sysv-xlogues
Target Report Mask(CALL_MS2SYSV_XLOGUES) Save Target Mask(CALL_MS2SYSV_XLOGUES) Save
Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls. Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls.
mveclibabi= mveclibabi=
@ -566,28 +566,28 @@ EnumValue
Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
mvect8-ret-in-mem mvect8-ret-in-mem
Target Report Mask(VECT8_RETURNS) Save Target Mask(VECT8_RETURNS) Save
Return 8-byte vectors in memory. Return 8-byte vectors in memory.
mrecip mrecip
Target Report Mask(RECIP) Save Target Mask(RECIP) Save
Generate reciprocals instead of divss and sqrtss. Generate reciprocals instead of divss and sqrtss.
mrecip= mrecip=
Target Report RejectNegative Joined Var(ix86_recip_name) Target RejectNegative Joined Var(ix86_recip_name)
Control generation of reciprocal estimates. Control generation of reciprocal estimates.
mcld mcld
Target Report Mask(CLD) Save Target Mask(CLD) Save
Generate cld instruction in the function prologue. Generate cld instruction in the function prologue.
mvzeroupper mvzeroupper
Target Report Mask(VZEROUPPER) Save Target Mask(VZEROUPPER) Save
Generate vzeroupper instruction before a transfer of control flow out of Generate vzeroupper instruction before a transfer of control flow out of
the function. the function.
mstv mstv
Target Report Mask(STV) Save Target Mask(STV) Save
Disable Scalar to Vector optimization pass transforming 64-bit integer Disable Scalar to Vector optimization pass transforming 64-bit integer
computations into a vector ones. computations into a vector ones.
@ -601,7 +601,7 @@ Target Alias(mprefer-vector-width=, 128, 256)
Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
mprefer-vector-width= mprefer-vector-width=
Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save Target RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save
Use given register vector width instructions instead of maximum register width in the auto-vectorizer. Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
Enum Enum
@ -623,63 +623,63 @@ Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
;; ISA support ;; ISA support
m32 m32
Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save Target RejectNegative Negative(m64) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
Generate 32bit i386 code. Generate 32bit i386 code.
m64 m64
Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save Target RejectNegative Negative(mx32) Mask(ABI_64) Var(ix86_isa_flags) Save
Generate 64bit x86-64 code. Generate 64bit x86-64 code.
mx32 mx32
Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save Target RejectNegative Negative(m16) Mask(ABI_X32) Var(ix86_isa_flags) Save
Generate 32bit x86-64 code. Generate 32bit x86-64 code.
m16 m16
Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save Target RejectNegative Negative(m32) Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
Generate 16bit i386 code. Generate 16bit i386 code.
mmmx mmmx
Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save Target Mask(ISA_MMX) Var(ix86_isa_flags) Save
Support MMX built-in functions. Support MMX built-in functions.
m3dnow m3dnow
Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save Target Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
Support 3DNow! built-in functions. Support 3DNow! built-in functions.
m3dnowa m3dnowa
Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save Target Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
Support Athlon 3Dnow! built-in functions. Support Athlon 3Dnow! built-in functions.
msse msse
Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save Target Mask(ISA_SSE) Var(ix86_isa_flags) Save
Support MMX and SSE built-in functions and code generation. Support MMX and SSE built-in functions and code generation.
msse2 msse2
Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save Target Mask(ISA_SSE2) Var(ix86_isa_flags) Save
Support MMX, SSE and SSE2 built-in functions and code generation. Support MMX, SSE and SSE2 built-in functions and code generation.
msse3 msse3
Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save Target Mask(ISA_SSE3) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
mssse3 mssse3
Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save Target Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
msse4.1 msse4.1
Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save Target Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
msse4.2 msse4.2
Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Target Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
msse4 msse4
Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Target RejectNegative Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
mno-sse4 mno-sse4
Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save Target RejectNegative InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
Do not support SSE4.1 and SSE4.2 built-in functions and code generation. Do not support SSE4.1 and SSE4.2 built-in functions and code generation.
msse5 msse5
@ -687,262 +687,262 @@ Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
;; Deprecated ;; Deprecated
mavx mavx
Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save Target Mask(ISA_AVX) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
mavx2 mavx2
Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save Target Mask(ISA_AVX2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation.
mavx512f mavx512f
Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation.
mavx512pf mavx512pf
Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation.
mavx512er mavx512er
Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation.
mavx512cd mavx512cd
Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation.
mavx512dq mavx512dq
Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation.
mavx512bw mavx512bw
Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation.
mavx512vl mavx512vl
Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation.
mavx512ifma mavx512ifma
Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation.
mavx512vbmi mavx512vbmi
Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation.
mavx5124fmaps mavx5124fmaps
Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save Target Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation.
mavx5124vnniw mavx5124vnniw
Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save Target Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation.
mavx512vpopcntdq mavx512vpopcntdq
Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation.
mavx512vbmi2 mavx512vbmi2
Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation.
mavx512vnni mavx512vnni
Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save
Support AVX512VNNI built-in functions and code generation. Support AVX512VNNI built-in functions and code generation.
mavx512bitalg mavx512bitalg
Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save Target Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation.
mavx512vp2intersect mavx512vp2intersect
Target Report Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save Target Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save
Support AVX512VP2INTERSECT built-in functions and code generation. Support AVX512VP2INTERSECT built-in functions and code generation.
mfma mfma
Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save Target Mask(ISA_FMA) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation.
msse4a msse4a
Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save Target Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation.
mfma4 mfma4
Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save Target Mask(ISA_FMA4) Var(ix86_isa_flags) Save
Support FMA4 built-in functions and code generation. Support FMA4 built-in functions and code generation.
mxop mxop
Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save Target Mask(ISA_XOP) Var(ix86_isa_flags) Save
Support XOP built-in functions and code generation. Support XOP built-in functions and code generation.
mlwp mlwp
Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save Target Mask(ISA_LWP) Var(ix86_isa_flags) Save
Support LWP built-in functions and code generation. Support LWP built-in functions and code generation.
mabm mabm
Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save Target Mask(ISA_ABM) Var(ix86_isa_flags) Save
Support code generation of Advanced Bit Manipulation (ABM) instructions. Support code generation of Advanced Bit Manipulation (ABM) instructions.
mpopcnt mpopcnt
Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save Target Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
Support code generation of popcnt instruction. Support code generation of popcnt instruction.
mpconfig mpconfig
Target Report Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save Target Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save
Support PCONFIG built-in functions and code generation. Support PCONFIG built-in functions and code generation.
mwbnoinvd mwbnoinvd
Target Report Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save Target Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save
Support WBNOINVD built-in functions and code generation. Support WBNOINVD built-in functions and code generation.
mptwrite mptwrite
Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save Target Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save
Support PTWRITE built-in functions and code generation. Support PTWRITE built-in functions and code generation.
muintr muintr
Target Report Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save Target Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save
Support UINTR built-in functions and code generation. Support UINTR built-in functions and code generation.
msgx msgx
Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save Target Mask(ISA2_SGX) Var(ix86_isa_flags2) Save
Support SGX built-in functions and code generation. Support SGX built-in functions and code generation.
mrdpid mrdpid
Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save Target Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save
Support RDPID built-in functions and code generation. Support RDPID built-in functions and code generation.
mgfni mgfni
Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save Target Mask(ISA_GFNI) Var(ix86_isa_flags) Save
Support GFNI built-in functions and code generation. Support GFNI built-in functions and code generation.
mvaes mvaes
Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save Target Mask(ISA2_VAES) Var(ix86_isa_flags2) Save
Support VAES built-in functions and code generation. Support VAES built-in functions and code generation.
mvpclmulqdq mvpclmulqdq
Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save Target Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save
Support VPCLMULQDQ built-in functions and code generation. Support VPCLMULQDQ built-in functions and code generation.
mbmi mbmi
Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save Target Mask(ISA_BMI) Var(ix86_isa_flags) Save
Support BMI built-in functions and code generation. Support BMI built-in functions and code generation.
mbmi2 mbmi2
Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save Target Mask(ISA_BMI2) Var(ix86_isa_flags) Save
Support BMI2 built-in functions and code generation. Support BMI2 built-in functions and code generation.
mlzcnt mlzcnt
Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save Target Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
Support LZCNT built-in function and code generation. Support LZCNT built-in function and code generation.
mhle mhle
Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save Target Mask(ISA2_HLE) Var(ix86_isa_flags2) Save
Support Hardware Lock Elision prefixes. Support Hardware Lock Elision prefixes.
mrdseed mrdseed
Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save Target Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
Support RDSEED instruction. Support RDSEED instruction.
mprfchw mprfchw
Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save Target Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
Support PREFETCHW instruction. Support PREFETCHW instruction.
madx madx
Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save Target Mask(ISA_ADX) Var(ix86_isa_flags) Save
Support flag-preserving add-carry instructions. Support flag-preserving add-carry instructions.
mclflushopt mclflushopt
Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save Target Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
Support CLFLUSHOPT instructions. Support CLFLUSHOPT instructions.
mclwb mclwb
Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save Target Mask(ISA_CLWB) Var(ix86_isa_flags) Save
Support CLWB instruction. Support CLWB instruction.
mpcommit mpcommit
Target WarnRemoved Target WarnRemoved
mfxsr mfxsr
Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save Target Mask(ISA_FXSR) Var(ix86_isa_flags) Save
Support FXSAVE and FXRSTOR instructions. Support FXSAVE and FXRSTOR instructions.
mxsave mxsave
Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save Target Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
Support XSAVE and XRSTOR instructions. Support XSAVE and XRSTOR instructions.
mxsaveopt mxsaveopt
Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save Target Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
Support XSAVEOPT instruction. Support XSAVEOPT instruction.
mxsavec mxsavec
Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save Target Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
Support XSAVEC instructions. Support XSAVEC instructions.
mxsaves mxsaves
Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save Target Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
Support XSAVES and XRSTORS instructions. Support XSAVES and XRSTORS instructions.
mtbm mtbm
Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save Target Mask(ISA_TBM) Var(ix86_isa_flags) Save
Support TBM built-in functions and code generation. Support TBM built-in functions and code generation.
mcx16 mcx16
Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save Target Mask(ISA2_CX16) Var(ix86_isa_flags2) Save
Support code generation of cmpxchg16b instruction. Support code generation of cmpxchg16b instruction.
msahf msahf
Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save Target Mask(ISA_SAHF) Var(ix86_isa_flags) Save
Support code generation of sahf instruction in 64bit x86-64 code. Support code generation of sahf instruction in 64bit x86-64 code.
mmovbe mmovbe
Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save Target Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save
Support code generation of movbe instruction. Support code generation of movbe instruction.
mcrc32 mcrc32
Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save Target Mask(ISA_CRC32) Var(ix86_isa_flags) Save
Support code generation of crc32 instruction. Support code generation of crc32 instruction.
maes maes
Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save Target Mask(ISA_AES) Var(ix86_isa_flags) Save
Support AES built-in functions and code generation. Support AES built-in functions and code generation.
msha msha
Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save Target Mask(ISA_SHA) Var(ix86_isa_flags) Save
Support SHA1 and SHA256 built-in functions and code generation. Support SHA1 and SHA256 built-in functions and code generation.
mpclmul mpclmul
Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save Target Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
Support PCLMUL built-in functions and code generation. Support PCLMUL built-in functions and code generation.
msse2avx msse2avx
Target Report Var(ix86_sse2avx) Target Var(ix86_sse2avx)
Encode SSE instructions with VEX prefix. Encode SSE instructions with VEX prefix.
mfsgsbase mfsgsbase
Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save Target Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
Support FSGSBASE built-in functions and code generation. Support FSGSBASE built-in functions and code generation.
mrdrnd mrdrnd
Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save Target Mask(ISA_RDRND) Var(ix86_isa_flags) Save
Support RDRND built-in functions and code generation. Support RDRND built-in functions and code generation.
mf16c mf16c
Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save Target Mask(ISA_F16C) Var(ix86_isa_flags) Save
Support F16C built-in functions and code generation. Support F16C built-in functions and code generation.
mprefetchwt1 mprefetchwt1
Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save Target Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
Support PREFETCHWT1 built-in functions and code generation. Support PREFETCHWT1 built-in functions and code generation.
mfentry mfentry
Target Report Var(flag_fentry) Target Var(flag_fentry)
Emit profiling counter call at function entry before prologue. Emit profiling counter call at function entry before prologue.
mrecord-mcount mrecord-mcount
Target Report Var(flag_record_mcount) Target Var(flag_record_mcount)
Generate __mcount_loc section with all mcount or __fentry__ calls. Generate __mcount_loc section with all mcount or __fentry__ calls.
mnop-mcount mnop-mcount
Target Report Var(flag_nop_mcount) Target Var(flag_nop_mcount)
Generate mcount/__fentry__ calls as nops. To activate they need to be Generate mcount/__fentry__ calls as nops. To activate they need to be
patched in. patched in.
@ -955,23 +955,23 @@ Target RejectNegative Joined Var(fentry_section)
Set name of section to record mrecord-mcount calls. Set name of section to record mrecord-mcount calls.
mskip-rax-setup mskip-rax-setup
Target Report Var(flag_skip_rax_setup) Target Var(flag_skip_rax_setup)
Skip setting up RAX register when passing variable arguments. Skip setting up RAX register when passing variable arguments.
m8bit-idiv m8bit-idiv
Target Report Mask(USE_8BIT_IDIV) Save Target Mask(USE_8BIT_IDIV) Save
Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check.
mavx256-split-unaligned-load mavx256-split-unaligned-load
Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save Target Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
Split 32-byte AVX unaligned load. Split 32-byte AVX unaligned load.
mavx256-split-unaligned-store mavx256-split-unaligned-store
Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save Target Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
Split 32-byte AVX unaligned store. Split 32-byte AVX unaligned store.
mrtm mrtm
Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save Target Mask(ISA_RTM) Var(ix86_isa_flags) Save
Support RTM built-in functions and code generation. Support RTM built-in functions and code generation.
mmpx mmpx
@ -979,15 +979,15 @@ Target WarnRemoved
Removed in GCC 9. This switch has no effect. Removed in GCC 9. This switch has no effect.
mmwaitx mmwaitx
Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save Target Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save
Support MWAITX and MONITORX built-in functions and code generation. Support MWAITX and MONITORX built-in functions and code generation.
mclzero mclzero
Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save Target Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save
Support CLZERO built-in functions and code generation. Support CLZERO built-in functions and code generation.
mpku mpku
Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save Target Mask(ISA_PKU) Var(ix86_isa_flags) Save
Support PKU built-in functions and code generation. Support PKU built-in functions and code generation.
mstack-protector-guard= mstack-protector-guard=
@ -1026,34 +1026,34 @@ mmitigate-rop
Target WarnRemoved Target WarnRemoved
mgeneral-regs-only mgeneral-regs-only
Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save Target RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
Generate code which uses only the general registers. Generate code which uses only the general registers.
mshstk mshstk
Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save Target Mask(ISA_SHSTK) Var(ix86_isa_flags) Save
Enable shadow stack built-in functions from Control-flow Enforcement Enable shadow stack built-in functions from Control-flow Enforcement
Technology (CET). Technology (CET).
mcet-switch mcet-switch
Target Report Undocumented Var(flag_cet_switch) Init(0) Target Undocumented Var(flag_cet_switch) Init(0)
Turn on CET instrumentation for switch statements that use a jump table and Turn on CET instrumentation for switch statements that use a jump table and
an indirect jump. an indirect jump.
mmanual-endbr mmanual-endbr
Target Report Var(flag_manual_endbr) Init(0) Target Var(flag_manual_endbr) Init(0)
Insert ENDBR instruction at function entry only via cf_check attribute Insert ENDBR instruction at function entry only via cf_check attribute
for CET instrumentation. for CET instrumentation.
mforce-indirect-call mforce-indirect-call
Target Report Var(flag_force_indirect_call) Init(0) Target Var(flag_force_indirect_call) Init(0)
Make all function calls indirect. Make all function calls indirect.
mindirect-branch= mindirect-branch=
Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
Convert indirect call and jump to call and return thunks. Convert indirect call and jump to call and return thunks.
mfunction-return= mfunction-return=
Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep)
Convert function return to call and return thunk. Convert function return to call and return thunk.
Enum Enum
@ -1073,27 +1073,27 @@ EnumValue
Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
mindirect-branch-register mindirect-branch-register
Target Report Var(ix86_indirect_branch_register) Init(0) Target Var(ix86_indirect_branch_register) Init(0)
Force indirect call and jump via register. Force indirect call and jump via register.
mmovdiri mmovdiri
Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save Target Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save
Support MOVDIRI built-in functions and code generation. Support MOVDIRI built-in functions and code generation.
mmovdir64b mmovdir64b
Target Report Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save Target Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save
Support MOVDIR64B built-in functions and code generation. Support MOVDIR64B built-in functions and code generation.
mwaitpkg mwaitpkg
Target Report Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save Target Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save
Support WAITPKG built-in functions and code generation. Support WAITPKG built-in functions and code generation.
mcldemote mcldemote
Target Report Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save Target Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save
Support CLDEMOTE built-in functions and code generation. Support CLDEMOTE built-in functions and code generation.
minstrument-return= minstrument-return=
Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none) Target RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none)
Instrument function exit in instrumented functions with __fentry__. Instrument function exit in instrumented functions with __fentry__.
Enum Enum
@ -1110,55 +1110,55 @@ EnumValue
Enum(instrument_return) String(nop5) Value(instrument_return_nop5) Enum(instrument_return) String(nop5) Value(instrument_return_nop5)
mrecord-return mrecord-return
Target Report Var(ix86_flag_record_return) Init(0) Target Var(ix86_flag_record_return) Init(0)
Generate a __return_loc section pointing to all return instrumentation code. Generate a __return_loc section pointing to all return instrumentation code.
mavx512bf16 mavx512bf16
Target Report Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save Target Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
AVX512BF16 built-in functions and code generation. AVX512BF16 built-in functions and code generation.
menqcmd menqcmd
Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save Target Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save
Support ENQCMD built-in functions and code generation. Support ENQCMD built-in functions and code generation.
mserialize mserialize
Target Report Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save Target Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save
Support SERIALIZE built-in functions and code generation. Support SERIALIZE built-in functions and code generation.
mtsxldtrk mtsxldtrk
Target Report Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save Target Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save
Support TSXLDTRK built-in functions and code generation. Support TSXLDTRK built-in functions and code generation.
mamx-tile mamx-tile
Target Report Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save Target Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save
Support AMX-TILE built-in functions and code generation. Support AMX-TILE built-in functions and code generation.
mamx-int8 mamx-int8
Target Report Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save Target Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save
Support AMX-INT8 built-in functions and code generation. Support AMX-INT8 built-in functions and code generation.
mamx-bf16 mamx-bf16
Target Report Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save Target Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save
Support AMX-BF16 built-in functions and code generation. Support AMX-BF16 built-in functions and code generation.
mhreset mhreset
Target Report Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save Target Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save
Support HRESET built-in functions and code generation. Support HRESET built-in functions and code generation.
mkl mkl
Target Report Mask(ISA2_KL) Var(ix86_isa_flags2) Save Target Mask(ISA2_KL) Var(ix86_isa_flags2) Save
Support KL built-in functions and code generation. Support KL built-in functions and code generation.
mwidekl mwidekl
Target Report Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save Target Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save
Support WIDEKL built-in functions and code generation. Support WIDEKL built-in functions and code generation.
mavxvnni mavxvnni
Target Report Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save Target Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and
AVXVNNI built-in functions and code generation. AVXVNNI built-in functions and code generation.
mneeded mneeded
Target Report Var(ix86_needed) Save Target Var(ix86_needed) Save
Emit GNU_PROPERTY_X86_ISA_1_NEEDED GNU property. Emit GNU_PROPERTY_X86_ISA_1_NEEDED GNU property.

68
gcc/config/ia64/ia64.opt
View File

@ -24,23 +24,23 @@ Variable
enum processor_type ia64_tune = PROCESSOR_ITANIUM2 enum processor_type ia64_tune = PROCESSOR_ITANIUM2
mbig-endian mbig-endian
Target Report RejectNegative Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Generate big endian code. Generate big endian code.
mlittle-endian mlittle-endian
Target Report RejectNegative InverseMask(BIG_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN)
Generate little endian code. Generate little endian code.
mgnu-as mgnu-as
Target Report Mask(GNU_AS) Target Mask(GNU_AS)
Generate code for GNU as. Generate code for GNU as.
mgnu-ld mgnu-ld
Target Report Mask(GNU_LD) Target Mask(GNU_LD)
Generate code for GNU ld. Generate code for GNU ld.
mvolatile-asm-stop mvolatile-asm-stop
Target Report Mask(VOL_ASM_STOP) Target Mask(VOL_ASM_STOP)
Emit stop bits before and after volatile extended asms. Emit stop bits before and after volatile extended asms.
mregister-names mregister-names
@ -48,65 +48,65 @@ Target Mask(REG_NAMES)
Use in/loc/out register names. Use in/loc/out register names.
mno-sdata mno-sdata
Target Report RejectNegative Mask(NO_SDATA) Target RejectNegative Mask(NO_SDATA)
msdata msdata
Target Report RejectNegative InverseMask(NO_SDATA) Target RejectNegative InverseMask(NO_SDATA)
Enable use of sdata/scommon/sbss. Enable use of sdata/scommon/sbss.
mno-pic mno-pic
Target Report RejectNegative Mask(NO_PIC) Target RejectNegative Mask(NO_PIC)
Generate code without GP reg. Generate code without GP reg.
mconstant-gp mconstant-gp
Target Report RejectNegative Mask(CONST_GP) Target RejectNegative Mask(CONST_GP)
gp is constant (but save/restore gp on indirect calls). gp is constant (but save/restore gp on indirect calls).
mauto-pic mauto-pic
Target Report RejectNegative Mask(AUTO_PIC) Target RejectNegative Mask(AUTO_PIC)
Generate self-relocatable code. Generate self-relocatable code.
minline-float-divide-min-latency minline-float-divide-min-latency
Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1) Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
Generate inline floating point division, optimize for latency. Generate inline floating point division, optimize for latency.
minline-float-divide-max-throughput minline-float-divide-max-throughput
Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2) Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
Generate inline floating point division, optimize for throughput. Generate inline floating point division, optimize for throughput.
mno-inline-float-divide mno-inline-float-divide
Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0) Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
minline-int-divide-min-latency minline-int-divide-min-latency
Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1) Target RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
Generate inline integer division, optimize for latency. Generate inline integer division, optimize for latency.
minline-int-divide-max-throughput minline-int-divide-max-throughput
Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2) Target RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
Generate inline integer division, optimize for throughput. Generate inline integer division, optimize for throughput.
mno-inline-int-divide mno-inline-int-divide
Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0) Target RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
Do not inline integer division. Do not inline integer division.
minline-sqrt-min-latency minline-sqrt-min-latency
Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1) Target RejectNegative Var(TARGET_INLINE_SQRT, 1)
Generate inline square root, optimize for latency. Generate inline square root, optimize for latency.
minline-sqrt-max-throughput minline-sqrt-max-throughput
Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2) Target RejectNegative Var(TARGET_INLINE_SQRT, 2)
Generate inline square root, optimize for throughput. Generate inline square root, optimize for throughput.
mno-inline-sqrt mno-inline-sqrt
Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0) Target RejectNegative Var(TARGET_INLINE_SQRT, 0)
Do not inline square root. Do not inline square root.
mdwarf2-asm mdwarf2-asm
Target Report Mask(DWARF2_ASM) Target Mask(DWARF2_ASM)
Enable DWARF line debug info via GNU as. Enable DWARF line debug info via GNU as.
mearly-stop-bits mearly-stop-bits
Target Report Mask(EARLY_STOP_BITS) Target Mask(EARLY_STOP_BITS)
Enable earlier placing stop bits for better scheduling. Enable earlier placing stop bits for better scheduling.
mfixed-range= mfixed-range=
@ -132,35 +132,35 @@ EnumValue
Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2) Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2)
msched-br-data-spec msched-br-data-spec
Target Report Var(mflag_sched_br_data_spec) Init(0) Target Var(mflag_sched_br_data_spec) Init(0)
Use data speculation before reload. Use data speculation before reload.
msched-ar-data-spec msched-ar-data-spec
Target Report Var(mflag_sched_ar_data_spec) Init(1) Target Var(mflag_sched_ar_data_spec) Init(1)
Use data speculation after reload. Use data speculation after reload.
msched-control-spec msched-control-spec
Target Report Var(mflag_sched_control_spec) Init(2) Target Var(mflag_sched_control_spec) Init(2)
Use control speculation. Use control speculation.
msched-br-in-data-spec msched-br-in-data-spec
Target Report Var(mflag_sched_br_in_data_spec) Init(1) Target Var(mflag_sched_br_in_data_spec) Init(1)
Use in block data speculation before reload. Use in block data speculation before reload.
msched-ar-in-data-spec msched-ar-in-data-spec
Target Report Var(mflag_sched_ar_in_data_spec) Init(1) Target Var(mflag_sched_ar_in_data_spec) Init(1)
Use in block data speculation after reload. Use in block data speculation after reload.
msched-in-control-spec msched-in-control-spec
Target Report Var(mflag_sched_in_control_spec) Init(1) Target Var(mflag_sched_in_control_spec) Init(1)
Use in block control speculation. Use in block control speculation.
msched-spec-ldc msched-spec-ldc
Target Report Var(mflag_sched_spec_ldc) Init(1) Target Var(mflag_sched_spec_ldc) Init(1)
Use simple data speculation check. Use simple data speculation check.
msched-spec-control-ldc msched-spec-control-ldc
Target Report Var(mflag_sched_spec_control_ldc) Init(0) Target Var(mflag_sched_spec_control_ldc) Init(0)
Use simple data speculation check for control speculation. Use simple data speculation check for control speculation.
msched-prefer-non-data-spec-insns msched-prefer-non-data-spec-insns
@ -170,15 +170,15 @@ msched-prefer-non-control-spec-insns
Target WarnRemoved Target WarnRemoved
msched-count-spec-in-critical-path msched-count-spec-in-critical-path
Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0) Target Var(mflag_sched_count_spec_in_critical_path) Init(0)
Count speculative dependencies while calculating priority of instructions. Count speculative dependencies while calculating priority of instructions.
msched-stop-bits-after-every-cycle msched-stop-bits-after-every-cycle
Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1) Target Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
Place a stop bit after every cycle when scheduling. Place a stop bit after every cycle when scheduling.
msched-fp-mem-deps-zero-cost msched-fp-mem-deps-zero-cost
Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0) Target Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group. Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group.
msched-max-memory-insns= msched-max-memory-insns=
@ -186,11 +186,11 @@ Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1. Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1.
msched-max-memory-insns-hard-limit msched-max-memory-insns-hard-limit
Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0) Target Var(mflag_sched_mem_insns_hard_limit) Init(0)
Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached). Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached).
msel-sched-dont-check-control-spec msel-sched-dont-check-control-spec
Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0) Target Var(mflag_sel_sched_dont_check_control_spec) Init(0)
Don't generate checks for control speculation in selective scheduling. Don't generate checks for control speculation in selective scheduling.
; This comment is to ensure we retain the blank line above. ; This comment is to ensure we retain the blank line above.

4
gcc/config/ia64/ilp32.opt
View File

@ -1,7 +1,7 @@
milp32 milp32
Target Report RejectNegative Mask(ILP32) Target RejectNegative Mask(ILP32)
Generate ILP32 code. Generate ILP32 code.
mlp64 mlp64
Target Report RejectNegative InverseMask(ILP32) Target RejectNegative InverseMask(ILP32)
Generate LP64 code. Generate LP64 code.

2
gcc/config/linux-android.opt
View File

@ -19,7 +19,7 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mandroid mandroid
Target Report Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0) Target Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0)
Generate code for the Android platform. Generate code for the Android platform.
tno-android-cc tno-android-cc

8
gcc/config/linux.opt
View File

@ -20,17 +20,17 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mbionic mbionic
Target Report RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc) Target RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc)
Use Bionic C library. Use Bionic C library.
mglibc mglibc
Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc) Target RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc)
Use GNU C library. Use GNU C library.
muclibc muclibc
Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl) Target RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl)
Use uClibc C library. Use uClibc C library.
mmusl mmusl
Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic) Target RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic)
Use musl C library. Use musl C library.

10
gcc/config/lm32/lm32.opt
View File

@ -20,21 +20,21 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mmultiply-enabled mmultiply-enabled
Target Report Mask(MULTIPLY_ENABLED) Target Mask(MULTIPLY_ENABLED)
Enable multiply instructions. Enable multiply instructions.
mdivide-enabled mdivide-enabled
Target Report Mask(DIVIDE_ENABLED) Target Mask(DIVIDE_ENABLED)
Enable divide and modulus instructions. Enable divide and modulus instructions.
mbarrel-shift-enabled mbarrel-shift-enabled
Target Report Mask(BARREL_SHIFT_ENABLED) Target Mask(BARREL_SHIFT_ENABLED)
Enable barrel shift instructions. Enable barrel shift instructions.
msign-extend-enabled msign-extend-enabled
Target Report Mask(SIGN_EXTEND_ENABLED) Target Mask(SIGN_EXTEND_ENABLED)
Enable sign extend instructions. Enable sign extend instructions.
muser-enabled muser-enabled
Target Report Mask(USER_ENABLED) Target Mask(USER_ENABLED)
Enable user-defined instructions. Enable user-defined instructions.

14
gcc/config/m32r/m32r.opt
View File

@ -30,11 +30,11 @@ Variable
enum m32r_sdata m32r_sdata_selected = M32R_SDATA_DEFAULT enum m32r_sdata m32r_sdata_selected = M32R_SDATA_DEFAULT
m32rx m32rx
Target Report RejectNegative Mask(M32RX) Target RejectNegative Mask(M32RX)
Compile for the m32rx. Compile for the m32rx.
m32r2 m32r2
Target Report RejectNegative Mask(M32R2) Target RejectNegative Mask(M32R2)
Compile for the m32r2. Compile for the m32r2.
m32r m32r
@ -42,15 +42,15 @@ Target RejectNegative
Compile for the m32r. Compile for the m32r.
malign-loops malign-loops
Target Report Mask(ALIGN_LOOPS) Target Mask(ALIGN_LOOPS)
Align all loops to 32 byte boundary. Align all loops to 32 byte boundary.
mbranch-cost=1 mbranch-cost=1
Target Report RejectNegative Mask(BRANCH_COST) Target RejectNegative Mask(BRANCH_COST)
Prefer branches over conditional execution. Prefer branches over conditional execution.
mbranch-cost=2 mbranch-cost=2
Target Report RejectNegative InverseMask(BRANCH_COST) Target RejectNegative InverseMask(BRANCH_COST)
Give branches their default cost. Give branches their default cost.
mdebug mdebug
@ -66,11 +66,11 @@ Target RejectNegative Joined UInteger Var(m32r_cache_flush_trap) Init(CACHE_FLUS
Specify cache flush trap number. Specify cache flush trap number.
missue-rate=1 missue-rate=1
Target Report RejectNegative Mask(LOW_ISSUE_RATE) Target RejectNegative Mask(LOW_ISSUE_RATE)
Only issue one instruction per cycle. Only issue one instruction per cycle.
missue-rate=2 missue-rate=2
Target Report RejectNegative InverseMask(LOW_ISSUE_RATE) Target RejectNegative InverseMask(LOW_ISSUE_RATE)
Allow two instructions to be issued per cycle. Allow two instructions to be issued per cycle.
mmodel= mmodel=

24
gcc/config/m68k/m68k.opt
View File

@ -95,7 +95,7 @@ Target RejectNegative Mask(HARD_FLOAT)
Generate code that uses 68881 floating-point instructions. Generate code that uses 68881 floating-point instructions.
malign-int malign-int
Target Report Mask(ALIGN_INT) Target Mask(ALIGN_INT)
Align variables on a 32-bit boundary. Align variables on a 32-bit boundary.
march= march=
@ -103,7 +103,7 @@ Target RejectNegative Joined Enum(m68k_isa) Var(m68k_arch_option)
Specify the name of the target architecture. Specify the name of the target architecture.
mbitfield mbitfield
Target Report Mask(BITFIELD) Target Mask(BITFIELD)
Use the bit-field instructions. Use the bit-field instructions.
mc68000 mc68000
@ -127,7 +127,7 @@ Target RejectNegative Alias(mcpu=, 68332)
Generate code for a cpu32. Generate code for a cpu32.
mdiv mdiv
Target Report Mask(CF_HWDIV) Target Mask(CF_HWDIV)
Use hardware division instructions on ColdFire. Use hardware division instructions on ColdFire.
mfidoa mfidoa
@ -139,11 +139,11 @@ Target RejectNegative Mask(HARD_FLOAT)
Generate code which uses hardware floating point instructions. Generate code which uses hardware floating point instructions.
mid-shared-library mid-shared-library
Target Report Mask(ID_SHARED_LIBRARY) Target Mask(ID_SHARED_LIBRARY)
Enable ID based shared library. Enable ID based shared library.
mlong-jump-table-offsets mlong-jump-table-offsets
Target Report RejectNegative Mask(LONG_JUMP_TABLE_OFFSETS) Target RejectNegative Mask(LONG_JUMP_TABLE_OFFSETS)
Use 32-bit offsets in jump tables rather than 16-bit offsets. Use 32-bit offsets in jump tables rather than 16-bit offsets.
mnobitfield mnobitfield
@ -159,15 +159,15 @@ Target RejectNegative InverseMask(SHORT)
Consider type 'int' to be 32 bits wide. Consider type 'int' to be 32 bits wide.
mpcrel mpcrel
Target Report Mask(PCREL) Target Mask(PCREL)
Generate pc-relative code. Generate pc-relative code.
mrtd mrtd
Target Report Mask(RTD) Target Mask(RTD)
Use different calling convention using 'rtd'. Use different calling convention using 'rtd'.
msep-data msep-data
Target Report Mask(SEP_DATA) Target Mask(SEP_DATA)
Enable separate data segment. Enable separate data segment.
mshared-library-id= mshared-library-id=
@ -175,7 +175,7 @@ Target RejectNegative Joined UInteger
ID of shared library to build. ID of shared library to build.
mshort mshort
Target Report Mask(SHORT) Target Mask(SHORT)
Consider type 'int' to be 16 bits wide. Consider type 'int' to be 16 bits wide.
msoft-float msoft-float
@ -183,7 +183,7 @@ Target RejectNegative InverseMask(HARD_FLOAT)
Generate code with library calls for floating point. Generate code with library calls for floating point.
mstrict-align mstrict-align
Target Report Mask(STRICT_ALIGNMENT) Target Mask(STRICT_ALIGNMENT)
Do not use unaligned memory references. Do not use unaligned memory references.
mtune= mtune=
@ -191,9 +191,9 @@ Target RejectNegative Joined Enum(uarch_type) Var(m68k_tune_option) Init(unk_arc
Tune for the specified target CPU or architecture. Tune for the specified target CPU or architecture.
mxgot mxgot
Target Report Mask(XGOT) Target Mask(XGOT)
Support more than 8192 GOT entries on ColdFire. Support more than 8192 GOT entries on ColdFire.
mxtls mxtls
Target Report Mask(XTLS) Target Mask(XTLS)
Support TLS segment larger than 64K. Support TLS segment larger than 64K.

22
gcc/config/mcore/mcore.opt
View File

@ -19,35 +19,35 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
m210 m210
Target RejectNegative Report InverseMask(M340) Target RejectNegative InverseMask(M340)
Generate code for the M*Core M210. Generate code for the M*Core M210.
m340 m340
Target RejectNegative Report Mask(M340) Target RejectNegative Mask(M340)
Generate code for the M*Core M340. Generate code for the M*Core M340.
m4byte-functions m4byte-functions
Target Report Mask(OVERALIGN_FUNC) Target Mask(OVERALIGN_FUNC)
Force functions to be aligned to a 4 byte boundary. Force functions to be aligned to a 4 byte boundary.
mbig-endian mbig-endian
Target RejectNegative Report InverseMask(LITTLE_END) Target RejectNegative InverseMask(LITTLE_END)
Generate big-endian code. Generate big-endian code.
mcallgraph-data mcallgraph-data
Target Report Mask(CG_DATA) Target Mask(CG_DATA)
Emit call graph information. Emit call graph information.
mdiv mdiv
Target Report Mask(DIV) Target Mask(DIV)
Use the divide instruction. Use the divide instruction.
mhardlit mhardlit
Target Report Mask(HARDLIT) Target Mask(HARDLIT)
Inline constants if it can be done in 2 insns or less. Inline constants if it can be done in 2 insns or less.
mlittle-endian mlittle-endian
Target RejectNegative Report Mask(LITTLE_END) Target RejectNegative Mask(LITTLE_END)
Generate little-endian code. Generate little-endian code.
; Not used by the compiler proper. ; Not used by the compiler proper.
@ -56,11 +56,11 @@ Target RejectNegative
Assume that run-time support has been provided, so omit -lsim from the linker command line. Assume that run-time support has been provided, so omit -lsim from the linker command line.
mrelax-immediates mrelax-immediates
Target Report Mask(RELAX_IMM) Target Mask(RELAX_IMM)
Use arbitrary sized immediates in bit operations. Use arbitrary sized immediates in bit operations.
mslow-bytes mslow-bytes
Target Report Mask(SLOW_BYTES) Target Mask(SLOW_BYTES)
Prefer word accesses over byte accesses. Prefer word accesses over byte accesses.
; Maximum size we are allowed to grow the stack in a single operation. ; Maximum size we are allowed to grow the stack in a single operation.
@ -71,5 +71,5 @@ Target RejectNegative Joined UInteger Var(mcore_stack_increment) Init(STACK_UNIT
Set the maximum amount for a single stack increment operation. Set the maximum amount for a single stack increment operation.
mwide-bitfields mwide-bitfields
Target Report Mask(W_FIELD) Target Mask(W_FIELD)
Always treat bitfields as int-sized. Always treat bitfields as int-sized.

8
gcc/config/microblaze/microblaze.opt
View File

@ -36,11 +36,11 @@ Zxl-mode-xmdstub
Driver Driver
msoft-float msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT) Target RejectNegative Mask(SOFT_FLOAT)
Use software emulation for floating point (default). Use software emulation for floating point (default).
mhard-float mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
Use hardware floating point instructions. Use hardware floating point instructions.
msmall-divides msmall-divides
@ -56,11 +56,11 @@ Target Mask(MEMCPY)
Don't optimize block moves, use memcpy. Don't optimize block moves, use memcpy.
mbig-endian mbig-endian
Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Target RejectNegative InverseMask(LITTLE_ENDIAN)
Assume target CPU is configured as big endian. Assume target CPU is configured as big endian.
mlittle-endian mlittle-endian
Target Report RejectNegative Mask(LITTLE_ENDIAN) Target RejectNegative Mask(LITTLE_ENDIAN)
Assume target CPU is configured as little endian. Assume target CPU is configured as little endian.
mxl-soft-mul mxl-soft-mul

164
gcc/config/mips/mips.opt
View File

@ -51,15 +51,15 @@ EnumValue
Enum(mips_abi) String(eabi) Value(ABI_EABI) Enum(mips_abi) String(eabi) Value(ABI_EABI)
mabicalls mabicalls
Target Report Mask(ABICALLS) Target Mask(ABICALLS)
Generate code that can be used in SVR4-style dynamic objects. Generate code that can be used in SVR4-style dynamic objects.
mmad mmad
Target Report Var(TARGET_MAD) Target Var(TARGET_MAD)
Use PMC-style 'mad' instructions. Use PMC-style 'mad' instructions.
mimadd mimadd
Target Report Mask(IMADD) Target Mask(IMADD)
Use integer madd/msub instructions. Use integer madd/msub instructions.
march= march=
@ -71,15 +71,15 @@ Target RejectNegative Joined UInteger Var(mips_branch_cost)
-mbranch-cost=COST Set the cost of branches to roughly COST instructions. -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
mbranch-likely mbranch-likely
Target Report Mask(BRANCHLIKELY) Target Mask(BRANCHLIKELY)
Use Branch Likely instructions, overriding the architecture default. Use Branch Likely instructions, overriding the architecture default.
mflip-mips16 mflip-mips16
Target Report Var(TARGET_FLIP_MIPS16) Target Var(TARGET_FLIP_MIPS16)
Switch on/off MIPS16 ASE on alternating functions for compiler testing. Switch on/off MIPS16 ASE on alternating functions for compiler testing.
mcheck-zero-division mcheck-zero-division
Target Report Mask(CHECK_ZERO_DIV) Target Mask(CHECK_ZERO_DIV)
Trap on integer divide by zero. Trap on integer divide by zero.
mcode-readable= mcode-readable=
@ -100,27 +100,27 @@ EnumValue
Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO) Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
mdivide-breaks mdivide-breaks
Target Report RejectNegative Mask(DIVIDE_BREAKS) Target RejectNegative Mask(DIVIDE_BREAKS)
Use branch-and-break sequences to check for integer divide by zero. Use branch-and-break sequences to check for integer divide by zero.
mdivide-traps mdivide-traps
Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS) Target RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
Use trap instructions to check for integer divide by zero. Use trap instructions to check for integer divide by zero.
mdmx mdmx
Target Report RejectNegative Var(TARGET_MDMX) Target RejectNegative Var(TARGET_MDMX)
Allow the use of MDMX instructions. Allow the use of MDMX instructions.
mdouble-float mdouble-float
Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT) Target RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations. Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
mdsp mdsp
Target Report Var(TARGET_DSP) Target Var(TARGET_DSP)
Use MIPS-DSP instructions. Use MIPS-DSP instructions.
mdspr2 mdspr2
Target Report Var(TARGET_DSPR2) Target Var(TARGET_DSPR2)
Use MIPS-DSP REV 2 instructions. Use MIPS-DSP REV 2 instructions.
mdebug mdebug
@ -130,83 +130,83 @@ mdebugd
Target Var(TARGET_DEBUG_D_MODE) Undocumented Target Var(TARGET_DEBUG_D_MODE) Undocumented
meb meb
Target Report RejectNegative Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order. Use big-endian byte order.
mel mel
Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
Use little-endian byte order. Use little-endian byte order.
membedded-data membedded-data
Target Report Var(TARGET_EMBEDDED_DATA) Target Var(TARGET_EMBEDDED_DATA)
Use ROM instead of RAM. Use ROM instead of RAM.
meva meva
Target Report Var(TARGET_EVA) Target Var(TARGET_EVA)
Use Enhanced Virtual Addressing instructions. Use Enhanced Virtual Addressing instructions.
mexplicit-relocs mexplicit-relocs
Target Report Mask(EXPLICIT_RELOCS) Target Mask(EXPLICIT_RELOCS)
Use NewABI-style %reloc() assembly operators. Use NewABI-style %reloc() assembly operators.
mextern-sdata mextern-sdata
Target Report Var(TARGET_EXTERN_SDATA) Init(1) Target Var(TARGET_EXTERN_SDATA) Init(1)
Use -G for data that is not defined by the current object. Use -G for data that is not defined by the current object.
mfix-24k mfix-24k
Target Report Var(TARGET_FIX_24K) Target Var(TARGET_FIX_24K)
Work around certain 24K errata. Work around certain 24K errata.
mfix-r4000 mfix-r4000
Target Report Mask(FIX_R4000) Target Mask(FIX_R4000)
Work around certain R4000 errata. Work around certain R4000 errata.
mfix-r4400 mfix-r4400
Target Report Mask(FIX_R4400) Target Mask(FIX_R4400)
Work around certain R4400 errata. Work around certain R4400 errata.
mfix-r5900 mfix-r5900
Target Report Mask(FIX_R5900) Target Mask(FIX_R5900)
Work around the R5900 short loop erratum. Work around the R5900 short loop erratum.
mfix-rm7000 mfix-rm7000
Target Report Var(TARGET_FIX_RM7000) Target Var(TARGET_FIX_RM7000)
Work around certain RM7000 errata. Work around certain RM7000 errata.
mfix-r10000 mfix-r10000
Target Report Mask(FIX_R10000) Target Mask(FIX_R10000)
Work around certain R10000 errata. Work around certain R10000 errata.
mfix-sb1 mfix-sb1
Target Report Var(TARGET_FIX_SB1) Target Var(TARGET_FIX_SB1)
Work around errata for early SB-1 revision 2 cores. Work around errata for early SB-1 revision 2 cores.
mfix-vr4120 mfix-vr4120
Target Report Var(TARGET_FIX_VR4120) Target Var(TARGET_FIX_VR4120)
Work around certain VR4120 errata. Work around certain VR4120 errata.
mfix-vr4130 mfix-vr4130
Target Report Var(TARGET_FIX_VR4130) Target Var(TARGET_FIX_VR4130)
Work around VR4130 mflo/mfhi errata. Work around VR4130 mflo/mfhi errata.
mfix4300 mfix4300
Target Report Var(TARGET_4300_MUL_FIX) Target Var(TARGET_4300_MUL_FIX)
Work around an early 4300 hardware bug. Work around an early 4300 hardware bug.
mfp-exceptions mfp-exceptions
Target Report Var(TARGET_FP_EXCEPTIONS) Init(1) Target Var(TARGET_FP_EXCEPTIONS) Init(1)
FP exceptions are enabled. FP exceptions are enabled.
mfp32 mfp32
Target Report RejectNegative InverseMask(FLOAT64) Target RejectNegative InverseMask(FLOAT64)
Use 32-bit floating-point registers. Use 32-bit floating-point registers.
mfpxx mfpxx
Target Report RejectNegative Mask(FLOATXX) Target RejectNegative Mask(FLOATXX)
Conform to the o32 FPXX ABI. Conform to the o32 FPXX ABI.
mfp64 mfp64
Target Report RejectNegative Mask(FLOAT64) Target RejectNegative Mask(FLOAT64)
Use 64-bit floating-point registers. Use 64-bit floating-point registers.
mflush-func= mflush-func=
@ -232,31 +232,31 @@ EnumValue
Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY) Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY)
mgp32 mgp32
Target Report RejectNegative InverseMask(64BIT) Target RejectNegative InverseMask(64BIT)
Use 32-bit general registers. Use 32-bit general registers.
mgp64 mgp64
Target Report RejectNegative Mask(64BIT) Target RejectNegative Mask(64BIT)
Use 64-bit general registers. Use 64-bit general registers.
mgpopt mgpopt
Target Report Var(TARGET_GPOPT) Init(1) Target Var(TARGET_GPOPT) Init(1)
Use GP-relative addressing to access small data. Use GP-relative addressing to access small data.
mplt mplt
Target Report Var(TARGET_PLT) Target Var(TARGET_PLT)
When generating -mabicalls code, allow executables to use PLTs and copy relocations. When generating -mabicalls code, allow executables to use PLTs and copy relocations.
mhard-float mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI) Target RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
Allow the use of hardware floating-point ABI and instructions. Allow the use of hardware floating-point ABI and instructions.
minterlink-compressed minterlink-compressed
Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0) Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
Generate code that is link-compatible with MIPS16 and microMIPS code. Generate code that is link-compatible with MIPS16 and microMIPS code.
minterlink-mips16 minterlink-mips16
Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0) Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
An alias for minterlink-compressed provided for backward-compatibility. An alias for minterlink-compressed provided for backward-compatibility.
mips mips
@ -264,59 +264,59 @@ Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_opti
-mipsN Generate code for ISA level N. -mipsN Generate code for ISA level N.
mips16 mips16
Target Report RejectNegative Mask(MIPS16) Target RejectNegative Mask(MIPS16)
Generate MIPS16 code. Generate MIPS16 code.
mips3d mips3d
Target Report RejectNegative Var(TARGET_MIPS3D) Target RejectNegative Var(TARGET_MIPS3D)
Use MIPS-3D instructions. Use MIPS-3D instructions.
mllsc mllsc
Target Report Mask(LLSC) Target Mask(LLSC)
Use ll, sc and sync instructions. Use ll, sc and sync instructions.
mlocal-sdata mlocal-sdata
Target Report Var(TARGET_LOCAL_SDATA) Init(1) Target Var(TARGET_LOCAL_SDATA) Init(1)
Use -G for object-local data. Use -G for object-local data.
mlong-calls mlong-calls
Target Report Var(TARGET_LONG_CALLS) Target Var(TARGET_LONG_CALLS)
Use indirect calls. Use indirect calls.
mlong32 mlong32
Target Report RejectNegative InverseMask(LONG64, LONG32) Target RejectNegative InverseMask(LONG64, LONG32)
Use a 32-bit long type. Use a 32-bit long type.
mlong64 mlong64
Target Report RejectNegative Mask(LONG64) Target RejectNegative Mask(LONG64)
Use a 64-bit long type. Use a 64-bit long type.
mmcount-ra-address mmcount-ra-address
Target Report Var(TARGET_MCOUNT_RA_ADDRESS) Target Var(TARGET_MCOUNT_RA_ADDRESS)
Pass the address of the ra save location to _mcount in $12. Pass the address of the ra save location to _mcount in $12.
mmemcpy mmemcpy
Target Report Mask(MEMCPY) Target Mask(MEMCPY)
Don't optimize block moves. Don't optimize block moves.
mmicromips mmicromips
Target Report Mask(MICROMIPS) Target Mask(MICROMIPS)
Use microMIPS instructions. Use microMIPS instructions.
mmsa mmsa
Target Report Mask(MSA) Target Mask(MSA)
Use MIPS MSA Extension instructions. Use MIPS MSA Extension instructions.
mmt mmt
Target Report Var(TARGET_MT) Target Var(TARGET_MT)
Allow the use of MT instructions. Allow the use of MT instructions.
mno-float mno-float
Target Report RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT) Target RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT)
Prevent the use of all floating-point operations. Prevent the use of all floating-point operations.
mmcu mmcu
Target Report Var(TARGET_MCU) Target Var(TARGET_MCU)
Use MCU instructions. Use MCU instructions.
mno-flush-func mno-flush-func
@ -324,19 +324,19 @@ Target RejectNegative
Do not use a cache-flushing function before calling stack trampolines. Do not use a cache-flushing function before calling stack trampolines.
mno-mdmx mno-mdmx
Target Report RejectNegative Var(TARGET_MDMX, 0) Target RejectNegative Var(TARGET_MDMX, 0)
Do not use MDMX instructions. Do not use MDMX instructions.
mno-mips16 mno-mips16
Target Report RejectNegative InverseMask(MIPS16) Target RejectNegative InverseMask(MIPS16)
Generate normal-mode code. Generate normal-mode code.
mno-mips3d mno-mips3d
Target Report RejectNegative Var(TARGET_MIPS3D, 0) Target RejectNegative Var(TARGET_MIPS3D, 0)
Do not use MIPS-3D instructions. Do not use MIPS-3D instructions.
mpaired-single mpaired-single
Target Report Mask(PAIRED_SINGLE_FLOAT) Target Mask(PAIRED_SINGLE_FLOAT)
Use paired-single floating-point instructions. Use paired-single floating-point instructions.
mr10k-cache-barrier= mr10k-cache-barrier=
@ -357,47 +357,47 @@ EnumValue
Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE) Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
mrelax-pic-calls mrelax-pic-calls
Target Report Mask(RELAX_PIC_CALLS) Target Mask(RELAX_PIC_CALLS)
Try to allow the linker to turn PIC calls into direct calls. Try to allow the linker to turn PIC calls into direct calls.
mshared mshared
Target Report Var(TARGET_SHARED) Init(1) Target Var(TARGET_SHARED) Init(1)
When generating -mabicalls code, make the code suitable for use in shared libraries. When generating -mabicalls code, make the code suitable for use in shared libraries.
msingle-float msingle-float
Target Report RejectNegative Mask(SINGLE_FLOAT) Target RejectNegative Mask(SINGLE_FLOAT)
Restrict the use of hardware floating-point instructions to 32-bit operations. Restrict the use of hardware floating-point instructions to 32-bit operations.
msmartmips msmartmips
Target Report Mask(SMARTMIPS) Target Mask(SMARTMIPS)
Use SmartMIPS instructions. Use SmartMIPS instructions.
msoft-float msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT_ABI) Target RejectNegative Mask(SOFT_FLOAT_ABI)
Prevent the use of all hardware floating-point instructions. Prevent the use of all hardware floating-point instructions.
msplit-addresses msplit-addresses
Target Report Mask(SPLIT_ADDRESSES) Target Mask(SPLIT_ADDRESSES)
Optimize lui/addiu address loads. Optimize lui/addiu address loads.
msym32 msym32
Target Report Var(TARGET_SYM32) Target Var(TARGET_SYM32)
Assume all symbols have 32-bit values. Assume all symbols have 32-bit values.
msynci msynci
Target Report Mask(SYNCI) Target Mask(SYNCI)
Use synci instruction to invalidate i-cache. Use synci instruction to invalidate i-cache.
mlra mlra
Target Report Var(mips_lra_flag) Init(1) Save Target Var(mips_lra_flag) Init(1) Save
Use LRA instead of reload. Use LRA instead of reload.
mlxc1-sxc1 mlxc1-sxc1
Target Report Var(mips_lxc1_sxc1) Init(1) Target Var(mips_lxc1_sxc1) Init(1)
Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable. Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
mmadd4 mmadd4
Target Report Var(mips_madd4) Init(1) Target Var(mips_madd4) Init(1)
Use 4-operand madd.s/madd.d and related instructions where applicable. Use 4-operand madd.s/madd.d and related instructions where applicable.
mtune= mtune=
@ -405,50 +405,50 @@ Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_va
-mtune=PROCESSOR Optimize the output for PROCESSOR. -mtune=PROCESSOR Optimize the output for PROCESSOR.
muninit-const-in-rodata muninit-const-in-rodata
Target Report Var(TARGET_UNINIT_CONST_IN_RODATA) Target Var(TARGET_UNINIT_CONST_IN_RODATA)
Put uninitialized constants in ROM (needs -membedded-data). Put uninitialized constants in ROM (needs -membedded-data).
mvirt mvirt
Target Report Var(TARGET_VIRT) Target Var(TARGET_VIRT)
Use Virtualization (VZ) instructions. Use Virtualization (VZ) instructions.
mxpa mxpa
Target Report Var(TARGET_XPA) Target Var(TARGET_XPA)
Use eXtended Physical Address (XPA) instructions. Use eXtended Physical Address (XPA) instructions.
mcrc mcrc
Target Report Var(TARGET_CRC) Target Var(TARGET_CRC)
Use Cyclic Redundancy Check (CRC) instructions. Use Cyclic Redundancy Check (CRC) instructions.
mginv mginv
Target Report Var(TARGET_GINV) Target Var(TARGET_GINV)
Use Global INValidate (GINV) instructions. Use Global INValidate (GINV) instructions.
mvr4130-align mvr4130-align
Target Report Mask(VR4130_ALIGN) Target Mask(VR4130_ALIGN)
Perform VR4130-specific alignment optimizations. Perform VR4130-specific alignment optimizations.
mxgot mxgot
Target Report Var(TARGET_XGOT) Target Var(TARGET_XGOT)
Lift restrictions on GOT size. Lift restrictions on GOT size.
modd-spreg modd-spreg
Target Report Mask(ODD_SPREG) Target Mask(ODD_SPREG)
Enable use of odd-numbered single-precision registers. Enable use of odd-numbered single-precision registers.
mframe-header-opt mframe-header-opt
Target Report Var(flag_frame_header_optimization) Optimization Target Var(flag_frame_header_optimization) Optimization
Optimize frame header. Optimize frame header.
noasmopt noasmopt
Driver Driver
mload-store-pairs mload-store-pairs
Target Report Var(TARGET_LOAD_STORE_PAIRS) Init(1) Target Var(TARGET_LOAD_STORE_PAIRS) Init(1)
Enable load/store bonding. Enable load/store bonding.
mcompact-branches= mcompact-branches=
Target RejectNegative JoinedOrMissing Var(mips_cb) Report Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL) Target RejectNegative JoinedOrMissing Var(mips_cb) Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
Specify the compact branch usage policy. Specify the compact branch usage policy.
Enum Enum
@ -465,13 +465,13 @@ EnumValue
Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS) Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)
mloongson-mmi mloongson-mmi
Target Report Mask(LOONGSON_MMI) Target Mask(LOONGSON_MMI)
Use Loongson MultiMedia extensions Instructions (MMI) instructions. Use Loongson MultiMedia extensions Instructions (MMI) instructions.
mloongson-ext mloongson-ext
Target Report Mask(LOONGSON_EXT) Target Mask(LOONGSON_EXT)
Use Loongson EXTension (EXT) instructions. Use Loongson EXTension (EXT) instructions.
mloongson-ext2 mloongson-ext2
Target Report Var(TARGET_LOONGSON_EXT2) Target Var(TARGET_LOONGSON_EXT2)
Use Loongson EXTension R2 (EXT2) instructions. Use Loongson EXTension R2 (EXT2) instructions.

34
gcc/config/mmix/mmix.opt
View File

@ -20,48 +20,48 @@
; FIXME: Get rid of this one. ; FIXME: Get rid of this one.
mlibfuncs mlibfuncs
Target Report Mask(LIBFUNC) Target Mask(LIBFUNC)
For intrinsics library: pass all parameters in registers. For intrinsics library: pass all parameters in registers.
mabi=mmixware mabi=mmixware
Target Report RejectNegative InverseMask(ABI_GNU) Target RejectNegative InverseMask(ABI_GNU)
Use register stack for parameters and return value. Use register stack for parameters and return value.
mabi=gnu mabi=gnu
Target Report RejectNegative Mask(ABI_GNU) Target RejectNegative Mask(ABI_GNU)
Use call-clobbered registers for parameters and return value. Use call-clobbered registers for parameters and return value.
; FIXME: Provide a way to *load* the epsilon register. ; FIXME: Provide a way to *load* the epsilon register.
mepsilon mepsilon
Target Report Mask(FCMP_EPSILON) Target Mask(FCMP_EPSILON)
Use epsilon-respecting floating point compare instructions. Use epsilon-respecting floating point compare instructions.
mzero-extend mzero-extend
Target Report Mask(ZERO_EXTEND) Target Mask(ZERO_EXTEND)
Use zero-extending memory loads, not sign-extending ones. Use zero-extending memory loads, not sign-extending ones.
mknuthdiv mknuthdiv
Target Report Mask(KNUTH_DIVISION) Target Mask(KNUTH_DIVISION)
Generate divide results with reminder having the same sign as the divisor (not the dividend). Generate divide results with reminder having the same sign as the divisor (not the dividend).
mtoplevel-symbols mtoplevel-symbols
Target Report Mask(TOPLEVEL_SYMBOLS) Target Mask(TOPLEVEL_SYMBOLS)
Prepend global symbols with \":\" (for use with PREFIX). Prepend global symbols with \":\" (for use with PREFIX).
mno-set-program-start mno-set-program-start
Target Report RejectNegative Target RejectNegative
Do not provide a default start-address 0x100 of the program. Do not provide a default start-address 0x100 of the program.
melf melf
Target Report RejectNegative Target RejectNegative
Link to emit program in ELF format (rather than mmo). Link to emit program in ELF format (rather than mmo).
mbranch-predict mbranch-predict
Target Report RejectNegative Mask(BRANCH_PREDICT) Target RejectNegative Mask(BRANCH_PREDICT)
Use P-mnemonics for branches statically predicted as taken. Use P-mnemonics for branches statically predicted as taken.
mno-branch-predict mno-branch-predict
Target Report RejectNegative InverseMask(BRANCH_PREDICT) Target RejectNegative InverseMask(BRANCH_PREDICT)
Don't use P-mnemonics for branches. Don't use P-mnemonics for branches.
; We use the term "base address" since that's what Knuth uses. The base ; We use the term "base address" since that's what Knuth uses. The base
@ -75,25 +75,25 @@ Don't use P-mnemonics for branches.
; registers, and you'll not find out until link time whether you ; registers, and you'll not find out until link time whether you
; should have compiled with -mno-base-addresses. ; should have compiled with -mno-base-addresses.
mbase-addresses mbase-addresses
Target Report RejectNegative Mask(BASE_ADDRESSES) Target RejectNegative Mask(BASE_ADDRESSES)
Use addresses that allocate global registers. Use addresses that allocate global registers.
mno-base-addresses mno-base-addresses
Target Report RejectNegative InverseMask(BASE_ADDRESSES) Target RejectNegative InverseMask(BASE_ADDRESSES)
Do not use addresses that allocate global registers. Do not use addresses that allocate global registers.
msingle-exit msingle-exit
Target Report RejectNegative InverseMask(USE_RETURN_INSN) Target RejectNegative InverseMask(USE_RETURN_INSN)
Generate a single exit point for each function. Generate a single exit point for each function.
mno-single-exit mno-single-exit
Target Report RejectNegative Mask(USE_RETURN_INSN) Target RejectNegative Mask(USE_RETURN_INSN)
Do not generate a single exit point for each function. Do not generate a single exit point for each function.
mset-program-start= mset-program-start=
Target Report RejectNegative Joined Target RejectNegative Joined
Set start-address of the program. Set start-address of the program.
mset-data-start= mset-data-start=
Target Report RejectNegative Joined Target RejectNegative Joined
Set start-address of data. Set start-address of data.

10
gcc/config/mn10300/mn10300.opt
View File

@ -34,7 +34,7 @@ Target
Target the AM33/2.0 processor. Target the AM33/2.0 processor.
mam34 mam34
Target Report Target
Target the AM34 processor. Target the AM34 processor.
mtune= mtune=
@ -42,7 +42,7 @@ Target RejectNegative Joined Var(mn10300_tune_string)
Tune code for the given processor. Tune code for the given processor.
mmult-bug mmult-bug
Target Report Mask(MULT_BUG) Target Mask(MULT_BUG)
Work around hardware multiply bug. Work around hardware multiply bug.
; Ignored by the compiler ; Ignored by the compiler
@ -55,13 +55,13 @@ Target RejectNegative
Enable linker relaxations. Enable linker relaxations.
mreturn-pointer-on-d0 mreturn-pointer-on-d0
Target Report Mask(PTR_A0D0) Target Mask(PTR_A0D0)
Return pointers in both a0 and d0. Return pointers in both a0 and d0.
mliw mliw
Target Report Mask(ALLOW_LIW) Target Mask(ALLOW_LIW)
Allow gcc to generate LIW instructions. Allow gcc to generate LIW instructions.
msetlb msetlb
Target Report Mask(ALLOW_SETLB) Target Mask(ALLOW_SETLB)
Allow gcc to generate the SETLB and Lcc instructions. Allow gcc to generate the SETLB and Lcc instructions.

6
gcc/config/moxie/moxie.opt
View File

@ -19,15 +19,15 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
meb meb
Target RejectNegative Report InverseMask(LITTLE_ENDIAN) Target RejectNegative InverseMask(LITTLE_ENDIAN)
Generate big-endian code. Generate big-endian code.
mel mel
Target RejectNegative Report Mask(LITTLE_ENDIAN) Target RejectNegative Mask(LITTLE_ENDIAN)
Generate little-endian code. Generate little-endian code.
mmul.x mmul.x
Target Report Mask(HAS_MULX) Target Mask(HAS_MULX)
Enable MUL.X and UMUL.X instructions. Enable MUL.X and UMUL.X instructions.
; Ignored by the compiler ; Ignored by the compiler

34
gcc/config/msp430/msp430.opt
View File

@ -3,7 +3,7 @@ Target
Use simulator runtime. Use simulator runtime.
mtiny-printf mtiny-printf
Target Report Mask(TINY_PRINTF) Target Mask(TINY_PRINTF)
Use a lightweight configuration of printf and puts to reduce code size. For single-threaded applications, not requiring reentrant I/O only. Requires Newlib Nano IO. Use a lightweight configuration of printf and puts to reduce code size. For single-threaded applications, not requiring reentrant I/O only. Requires Newlib Nano IO.
masm-hex masm-hex
@ -11,19 +11,19 @@ Target Mask(ASM_HEX)
Force assembly output to always use hex constants. Force assembly output to always use hex constants.
mmcu= mmcu=
Target Report ToLower Joined RejectNegative Var(target_mcu) Target ToLower Joined RejectNegative Var(target_mcu)
Specify the MCU to build for. Specify the MCU to build for.
mwarn-mcu mwarn-mcu
Target Report Var(msp430_warn_mcu) Init(1) Target Var(msp430_warn_mcu) Init(1)
Warn if an MCU name is unrecognized or conflicts with other options (default: on). Warn if an MCU name is unrecognized or conflicts with other options (default: on).
mwarn-devices-csv mwarn-devices-csv
Target Report Var(msp430_warn_devices_csv) Init(1) Target Var(msp430_warn_devices_csv) Init(1)
Warn if devices.csv is not found or there are problem parsing it (default: on). Warn if devices.csv is not found or there are problem parsing it (default: on).
mcpu= mcpu=
Target Report Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT) Target Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT)
Specify the ISA to build for: msp430, msp430x, msp430xv2. Specify the ISA to build for: msp430, msp430x, msp430xv2.
Enum Enum
@ -48,29 +48,29 @@ EnumValue
Enum(msp430_cpu_types) String(430xv2) Value(MSP430_CPU_MSP430XV2) Enum(msp430_cpu_types) String(430xv2) Value(MSP430_CPU_MSP430XV2)
mlarge mlarge
Target Report Mask(LARGE) RejectNegative Target Mask(LARGE) RejectNegative
Select large model - 20-bit addresses/pointers. Select large model - 20-bit addresses/pointers.
msmall msmall
Target Report InverseMask(LARGE) RejectNegative Target InverseMask(LARGE) RejectNegative
Select small model - 16-bit addresses/pointers (default). Select small model - 16-bit addresses/pointers (default).
mrelax mrelax
Target Report Target
Optimize opcode sizes at link time. Optimize opcode sizes at link time.
mOs mOs
Target Undocumented Mask(OPT_SPACE) Target Undocumented Mask(OPT_SPACE)
minrt minrt
Target Report Mask(MINRT) RejectNegative Target Mask(MINRT) RejectNegative
Use a minimum runtime (no static initializers or ctors) for memory-constrained devices. Use a minimum runtime (no static initializers or ctors) for memory-constrained devices.
HeaderInclude HeaderInclude
config/msp430/msp430-opts.h config/msp430/msp430-opts.h
mhwmult= mhwmult=
Target Joined RejectNegative Report ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(MSP430_HWMULT_AUTO) Target Joined RejectNegative ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(MSP430_HWMULT_AUTO)
Specify the type of hardware multiply to support. Specify the type of hardware multiply to support.
Enum Enum
@ -92,15 +92,15 @@ EnumValue
Enum(msp430_hwmult_types) String(f5series) Value(MSP430_HWMULT_F5SERIES) Enum(msp430_hwmult_types) String(f5series) Value(MSP430_HWMULT_F5SERIES)
mcode-region= mcode-region=
Target Joined RejectNegative Report ToLower Var(msp430_code_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER) Target Joined RejectNegative ToLower Var(msp430_code_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER)
Specify whether functions should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower). Specify whether functions should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower).
mdata-region= mdata-region=
Target Joined RejectNegative Report ToLower Var(msp430_data_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER) Target Joined RejectNegative ToLower Var(msp430_data_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER)
Specify whether variables should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower). Specify whether variables should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower).
muse-lower-region-prefix muse-lower-region-prefix
Target Mask(USE_LOWER_REGION_PREFIX) Report Target Mask(USE_LOWER_REGION_PREFIX)
Add the .lower prefix to section names when compiling with -m{code,data}-region=lower (disabled by default). Add the .lower prefix to section names when compiling with -m{code,data}-region=lower (disabled by default).
Enum Enum
@ -119,20 +119,20 @@ EnumValue
Enum(msp430_regions) String(upper) Value(MSP430_REGION_UPPER) Enum(msp430_regions) String(upper) Value(MSP430_REGION_UPPER)
msilicon-errata= msilicon-errata=
Target Joined RejectNegative Report ToLower Target Joined RejectNegative ToLower
Passes on a request to the assembler to enable fixes for various silicon errata. Passes on a request to the assembler to enable fixes for various silicon errata.
msilicon-errata-warn= msilicon-errata-warn=
Target Joined RejectNegative Report ToLower Target Joined RejectNegative ToLower
Passes on a request to the assembler to warn about various silicon errata. Passes on a request to the assembler to warn about various silicon errata.
mdevices-csv-loc= mdevices-csv-loc=
Target Joined Var(msp430_devices_csv_loc) RejectNegative Report Target Joined Var(msp430_devices_csv_loc) RejectNegative
The path to devices.csv. The GCC driver can normally locate devices.csv itself The path to devices.csv. The GCC driver can normally locate devices.csv itself
and pass this option to the compiler, so the user shouldn't need to pass this. and pass this option to the compiler, so the user shouldn't need to pass this.
mmax-inline-shift= mmax-inline-shift=
Target RejectNegative Joined UInteger IntegerRange(0,65) Var(msp430_max_inline_shift) Init(65) Report Target RejectNegative Joined UInteger IntegerRange(0,65) Var(msp430_max_inline_shift) Init(65)
For shift operations by a constant amount, which require an individual instruction to shift by one For shift operations by a constant amount, which require an individual instruction to shift by one
position, set the maximum number of inline shift instructions (maximum value 64) to emit instead of using the corresponding __mspabi helper function. position, set the maximum number of inline shift instructions (maximum value 64) to emit instead of using the corresponding __mspabi helper function.
The default value is 4. The default value is 4.

40
gcc/config/nds32/nds32.opt
View File

@ -67,11 +67,11 @@ Specify use soft floating point ABI which mean alias to -mabi=2fp+.
; --------------------------------------------------------------- ; ---------------------------------------------------------------
mreduced-regs mreduced-regs
Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS) Target RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
Use reduced-set registers for register allocation. Use reduced-set registers for register allocation.
mfull-regs mfull-regs
Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS) Target RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
Use full-set registers for register allocation. Use full-set registers for register allocation.
; --------------------------------------------------------------- ; ---------------------------------------------------------------
@ -115,43 +115,43 @@ EnumValue
Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE) Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE)
mcmov mcmov
Target Report Mask(CMOV) Target Mask(CMOV)
Generate conditional move instructions. Generate conditional move instructions.
mhw-abs mhw-abs
Target Report Mask(HW_ABS) Target Mask(HW_ABS)
Generate hardware abs instructions. Generate hardware abs instructions.
mext-perf mext-perf
Target Report Mask(EXT_PERF) Target Mask(EXT_PERF)
Generate performance extension instructions. Generate performance extension instructions.
mext-perf2 mext-perf2
Target Report Mask(EXT_PERF2) Target Mask(EXT_PERF2)
Generate performance extension version 2 instructions. Generate performance extension version 2 instructions.
mext-string mext-string
Target Report Mask(EXT_STRING) Target Mask(EXT_STRING)
Generate string extension instructions. Generate string extension instructions.
mext-dsp mext-dsp
Target Report Mask(EXT_DSP) Target Mask(EXT_DSP)
Generate DSP extension instructions. Generate DSP extension instructions.
mv3push mv3push
Target Report Mask(V3PUSH) Target Mask(V3PUSH)
Generate v3 push25/pop25 instructions. Generate v3 push25/pop25 instructions.
m16-bit m16-bit
Target Report Mask(16_BIT) Target Mask(16_BIT)
Generate 16-bit instructions. Generate 16-bit instructions.
mrelax-hint mrelax-hint
Target Report Mask(RELAX_HINT) Target Mask(RELAX_HINT)
Insert relax hint for linker to do relaxation. Insert relax hint for linker to do relaxation.
mvh mvh
Target Report Mask(VH) Condition(!TARGET_LINUX_ABI) Target Mask(VH) Condition(!TARGET_LINUX_ABI)
Enable Virtual Hosting support. Enable Virtual Hosting support.
misr-vector-size= misr-vector-size=
@ -421,27 +421,27 @@ EnumValue
Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W) Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W)
mctor-dtor mctor-dtor
Target Report Target
Enable constructor/destructor feature. Enable constructor/destructor feature.
mrelax mrelax
Target Report Target
Guide linker to relax instructions. Guide linker to relax instructions.
mext-fpu-fma mext-fpu-fma
Target Report Mask(EXT_FPU_FMA) Target Mask(EXT_FPU_FMA)
Generate floating-point multiply-accumulation instructions. Generate floating-point multiply-accumulation instructions.
mext-fpu-sp mext-fpu-sp
Target Report Mask(FPU_SINGLE) Target Mask(FPU_SINGLE)
Generate single-precision floating-point instructions. Generate single-precision floating-point instructions.
mext-fpu-dp mext-fpu-dp
Target Report Mask(FPU_DOUBLE) Target Mask(FPU_DOUBLE)
Generate double-precision floating-point instructions. Generate double-precision floating-point instructions.
mforce-no-ext-dsp mforce-no-ext-dsp
Target Undocumented Report Mask(FORCE_NO_EXT_DSP) Target Undocumented Mask(FORCE_NO_EXT_DSP)
Force disable hardware loop, even use -mext-dsp. Force disable hardware loop, even use -mext-dsp.
msched-prolog-epilog msched-prolog-epilog
@ -457,9 +457,9 @@ Target Var(flag_always_save_lp) Init(0)
Always save $lp in the stack. Always save $lp in the stack.
munaligned-access munaligned-access
Target Report Var(flag_unaligned_access) Init(0) Target Var(flag_unaligned_access) Init(0)
Enable unaligned word and halfword accesses to packed data. Enable unaligned word and halfword accesses to packed data.
minline-asm-r15 minline-asm-r15
Target Report Var(flag_inline_asm_r15) Init(0) Target Var(flag_inline_asm_r15) Init(0)
Allow use r15 for inline ASM. Allow use r15 for inline ASM.

4
gcc/config/nios2/elf.opt
View File

@ -22,7 +22,7 @@
; toolchains. ; toolchains.
msmallc msmallc
Target Report RejectNegative Target RejectNegative
Link with a limited version of the C library. Link with a limited version of the C library.
msys-lib= msys-lib=
@ -34,5 +34,5 @@ Target RejectNegative Joined Var(nios2_sys_crt0_string)
Name of the startfile. Name of the startfile.
mhal mhal
Target Report RejectNegative Target RejectNegative
Link with HAL BSP. Link with HAL BSP.

258
gcc/config/nios2/nios2.opt
View File

@ -31,31 +31,31 @@ TargetSave
int saved_custom_code_index[256] int saved_custom_code_index[256]
mhw-div mhw-div
Target Report Mask(HAS_DIV) Target Mask(HAS_DIV)
Enable DIV, DIVU. Enable DIV, DIVU.
mhw-mul mhw-mul
Target Report Mask(HAS_MUL) Target Mask(HAS_MUL)
Enable MUL instructions. Enable MUL instructions.
mhw-mulx mhw-mulx
Target Report Mask(HAS_MULX) Target Mask(HAS_MULX)
Enable MULX instructions, assume fast shifter. Enable MULX instructions, assume fast shifter.
mfast-sw-div mfast-sw-div
Target Report Mask(FAST_SW_DIV) Target Mask(FAST_SW_DIV)
Use table based fast divide (default at -O3). Use table based fast divide (default at -O3).
mbypass-cache mbypass-cache
Target Report Mask(BYPASS_CACHE) Target Mask(BYPASS_CACHE)
All memory accesses use I/O load/store instructions. All memory accesses use I/O load/store instructions.
mno-cache-volatile mno-cache-volatile
Target Report RejectNegative Mask(BYPASS_CACHE_VOLATILE) Target RejectNegative Mask(BYPASS_CACHE_VOLATILE)
Volatile memory accesses use I/O load/store instructions. Volatile memory accesses use I/O load/store instructions.
mcache-volatile mcache-volatile
Target Report RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE) Target RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE)
Volatile memory accesses do not use I/O load/store instructions. Volatile memory accesses do not use I/O load/store instructions.
mgpopt= mgpopt=
@ -82,19 +82,19 @@ EnumValue
Enum(nios2_gpopt_type) String(all) Value(gpopt_all) Enum(nios2_gpopt_type) String(all) Value(gpopt_all)
mgpopt mgpopt
Target Report RejectNegative Var(nios2_gpopt_option, gpopt_local) Target RejectNegative Var(nios2_gpopt_option, gpopt_local)
Equivalent to -mgpopt=local. Equivalent to -mgpopt=local.
mno-gpopt mno-gpopt
Target Report RejectNegative Var(nios2_gpopt_option, gpopt_none) Target RejectNegative Var(nios2_gpopt_option, gpopt_none)
Equivalent to -mgpopt=none. Equivalent to -mgpopt=none.
meb meb
Target Report RejectNegative Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order. Use big-endian byte order.
mel mel
Target Report RejectNegative InverseMask(BIG_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN)
Use little-endian byte order. Use little-endian byte order.
mcustom-fpu-cfg= mcustom-fpu-cfg=
@ -102,467 +102,467 @@ Target RejectNegative Joined Var(nios2_custom_fpu_cfg_string)
Floating point custom instruction configuration name. Floating point custom instruction configuration name.
mno-custom-ftruncds mno-custom-ftruncds
Target Report RejectNegative Var(nios2_custom_ftruncds, -1) Target RejectNegative Var(nios2_custom_ftruncds, -1)
Do not use the ftruncds custom instruction. Do not use the ftruncds custom instruction.
mcustom-ftruncds= mcustom-ftruncds=
Target Report RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1)
Integer id (N) of ftruncds custom instruction. Integer id (N) of ftruncds custom instruction.
mno-custom-fextsd mno-custom-fextsd
Target Report RejectNegative Var(nios2_custom_fextsd, -1) Target RejectNegative Var(nios2_custom_fextsd, -1)
Do not use the fextsd custom instruction. Do not use the fextsd custom instruction.
mcustom-fextsd= mcustom-fextsd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1)
Integer id (N) of fextsd custom instruction. Integer id (N) of fextsd custom instruction.
mno-custom-fixdu mno-custom-fixdu
Target Report RejectNegative Var(nios2_custom_fixdu, -1) Target RejectNegative Var(nios2_custom_fixdu, -1)
Do not use the fixdu custom instruction. Do not use the fixdu custom instruction.
mcustom-fixdu= mcustom-fixdu=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1)
Integer id (N) of fixdu custom instruction. Integer id (N) of fixdu custom instruction.
mno-custom-fixdi mno-custom-fixdi
Target Report RejectNegative Var(nios2_custom_fixdi, -1) Target RejectNegative Var(nios2_custom_fixdi, -1)
Do not use the fixdi custom instruction. Do not use the fixdi custom instruction.
mcustom-fixdi= mcustom-fixdi=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1)
Integer id (N) of fixdi custom instruction. Integer id (N) of fixdi custom instruction.
mno-custom-fixsu mno-custom-fixsu
Target Report RejectNegative Var(nios2_custom_fixsu, -1) Target RejectNegative Var(nios2_custom_fixsu, -1)
Do not use the fixsu custom instruction. Do not use the fixsu custom instruction.
mcustom-fixsu= mcustom-fixsu=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1)
Integer id (N) of fixsu custom instruction. Integer id (N) of fixsu custom instruction.
mno-custom-fixsi mno-custom-fixsi
Target Report RejectNegative Var(nios2_custom_fixsi, -1) Target RejectNegative Var(nios2_custom_fixsi, -1)
Do not use the fixsi custom instruction. Do not use the fixsi custom instruction.
mcustom-fixsi= mcustom-fixsi=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1)
Integer id (N) of fixsi custom instruction. Integer id (N) of fixsi custom instruction.
mno-custom-floatud mno-custom-floatud
Target Report RejectNegative Var(nios2_custom_floatud, -1) Target RejectNegative Var(nios2_custom_floatud, -1)
Do not use the floatud custom instruction. Do not use the floatud custom instruction.
mcustom-floatud= mcustom-floatud=
Target Report RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1)
Integer id (N) of floatud custom instruction. Integer id (N) of floatud custom instruction.
mno-custom-floatid mno-custom-floatid
Target Report RejectNegative Var(nios2_custom_floatid, -1) Target RejectNegative Var(nios2_custom_floatid, -1)
Do not use the floatid custom instruction. Do not use the floatid custom instruction.
mcustom-floatid= mcustom-floatid=
Target Report RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1)
Integer id (N) of floatid custom instruction. Integer id (N) of floatid custom instruction.
mno-custom-floatus mno-custom-floatus
Target Report RejectNegative Var(nios2_custom_floatus, -1) Target RejectNegative Var(nios2_custom_floatus, -1)
Do not use the floatus custom instruction. Do not use the floatus custom instruction.
mcustom-floatus= mcustom-floatus=
Target Report RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1)
Integer id (N) of floatus custom instruction. Integer id (N) of floatus custom instruction.
mno-custom-floatis mno-custom-floatis
Target Report RejectNegative Var(nios2_custom_floatis, -1) Target RejectNegative Var(nios2_custom_floatis, -1)
Do not use the floatis custom instruction. Do not use the floatis custom instruction.
mcustom-floatis= mcustom-floatis=
Target Report RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1)
Integer id (N) of floatis custom instruction. Integer id (N) of floatis custom instruction.
mno-custom-fcmpned mno-custom-fcmpned
Target Report RejectNegative Var(nios2_custom_fcmpned, -1) Target RejectNegative Var(nios2_custom_fcmpned, -1)
Do not use the fcmpned custom instruction. Do not use the fcmpned custom instruction.
mcustom-fcmpned= mcustom-fcmpned=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1)
Integer id (N) of fcmpned custom instruction. Integer id (N) of fcmpned custom instruction.
mno-custom-fcmpeqd mno-custom-fcmpeqd
Target Report RejectNegative Var(nios2_custom_fcmpeqd, -1) Target RejectNegative Var(nios2_custom_fcmpeqd, -1)
Do not use the fcmpeqd custom instruction. Do not use the fcmpeqd custom instruction.
mcustom-fcmpeqd= mcustom-fcmpeqd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1)
Integer id (N) of fcmpeqd custom instruction. Integer id (N) of fcmpeqd custom instruction.
mno-custom-fcmpged mno-custom-fcmpged
Target Report RejectNegative Var(nios2_custom_fcmpged, -1) Target RejectNegative Var(nios2_custom_fcmpged, -1)
Do not use the fcmpged custom instruction. Do not use the fcmpged custom instruction.
mcustom-fcmpged= mcustom-fcmpged=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1)
Integer id (N) of fcmpged custom instruction. Integer id (N) of fcmpged custom instruction.
mno-custom-fcmpgtd mno-custom-fcmpgtd
Target Report RejectNegative Var(nios2_custom_fcmpgtd, -1) Target RejectNegative Var(nios2_custom_fcmpgtd, -1)
Do not use the fcmpgtd custom instruction. Do not use the fcmpgtd custom instruction.
mcustom-fcmpgtd= mcustom-fcmpgtd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1)
Integer id (N) of fcmpgtd custom instruction. Integer id (N) of fcmpgtd custom instruction.
mno-custom-fcmpled mno-custom-fcmpled
Target Report RejectNegative Var(nios2_custom_fcmpled, -1) Target RejectNegative Var(nios2_custom_fcmpled, -1)
Do not use the fcmpled custom instruction. Do not use the fcmpled custom instruction.
mcustom-fcmpled= mcustom-fcmpled=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1)
Integer id (N) of fcmpled custom instruction. Integer id (N) of fcmpled custom instruction.
mno-custom-fcmpltd mno-custom-fcmpltd
Target Report RejectNegative Var(nios2_custom_fcmpltd, -1) Target RejectNegative Var(nios2_custom_fcmpltd, -1)
Do not use the fcmpltd custom instruction. Do not use the fcmpltd custom instruction.
mcustom-fcmpltd= mcustom-fcmpltd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1)
Integer id (N) of fcmpltd custom instruction. Integer id (N) of fcmpltd custom instruction.
mno-custom-flogd mno-custom-flogd
Target Report RejectNegative Var(nios2_custom_flogd, -1) Target RejectNegative Var(nios2_custom_flogd, -1)
Do not use the flogd custom instruction. Do not use the flogd custom instruction.
mcustom-flogd= mcustom-flogd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1)
Integer id (N) of flogd custom instruction. Integer id (N) of flogd custom instruction.
mno-custom-fexpd mno-custom-fexpd
Target Report RejectNegative Var(nios2_custom_fexpd, -1) Target RejectNegative Var(nios2_custom_fexpd, -1)
Do not use the fexpd custom instruction. Do not use the fexpd custom instruction.
mcustom-fexpd= mcustom-fexpd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1)
Integer id (N) of fexpd custom instruction. Integer id (N) of fexpd custom instruction.
mno-custom-fatand mno-custom-fatand
Target Report RejectNegative Var(nios2_custom_fatand, -1) Target RejectNegative Var(nios2_custom_fatand, -1)
Do not use the fatand custom instruction. Do not use the fatand custom instruction.
mcustom-fatand= mcustom-fatand=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1)
Integer id (N) of fatand custom instruction. Integer id (N) of fatand custom instruction.
mno-custom-ftand mno-custom-ftand
Target Report RejectNegative Var(nios2_custom_ftand, -1) Target RejectNegative Var(nios2_custom_ftand, -1)
Do not use the ftand custom instruction. Do not use the ftand custom instruction.
mcustom-ftand= mcustom-ftand=
Target Report RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1)
Integer id (N) of ftand custom instruction. Integer id (N) of ftand custom instruction.
mno-custom-fsind mno-custom-fsind
Target Report RejectNegative Var(nios2_custom_fsind, -1) Target RejectNegative Var(nios2_custom_fsind, -1)
Do not use the fsind custom instruction. Do not use the fsind custom instruction.
mcustom-fsind= mcustom-fsind=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1)
Integer id (N) of fsind custom instruction. Integer id (N) of fsind custom instruction.
mno-custom-fcosd mno-custom-fcosd
Target Report RejectNegative Var(nios2_custom_fcosd, -1) Target RejectNegative Var(nios2_custom_fcosd, -1)
Do not use the fcosd custom instruction. Do not use the fcosd custom instruction.
mcustom-fcosd= mcustom-fcosd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1)
Integer id (N) of fcosd custom instruction. Integer id (N) of fcosd custom instruction.
mno-custom-fsqrtd mno-custom-fsqrtd
Target Report RejectNegative Var(nios2_custom_fsqrtd, -1) Target RejectNegative Var(nios2_custom_fsqrtd, -1)
Do not use the fsqrtd custom instruction. Do not use the fsqrtd custom instruction.
mcustom-fsqrtd= mcustom-fsqrtd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1)
Integer id (N) of fsqrtd custom instruction. Integer id (N) of fsqrtd custom instruction.
mno-custom-fabsd mno-custom-fabsd
Target Report RejectNegative Var(nios2_custom_fabsd, -1) Target RejectNegative Var(nios2_custom_fabsd, -1)
Do not use the fabsd custom instruction. Do not use the fabsd custom instruction.
mcustom-fabsd= mcustom-fabsd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1)
Integer id (N) of fabsd custom instruction. Integer id (N) of fabsd custom instruction.
mno-custom-fnegd mno-custom-fnegd
Target Report RejectNegative Var(nios2_custom_fnegd, -1) Target RejectNegative Var(nios2_custom_fnegd, -1)
Do not use the fnegd custom instruction. Do not use the fnegd custom instruction.
mcustom-fnegd= mcustom-fnegd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1)
Integer id (N) of fnegd custom instruction. Integer id (N) of fnegd custom instruction.
mno-custom-fmaxd mno-custom-fmaxd
Target Report RejectNegative Var(nios2_custom_fmaxd, -1) Target RejectNegative Var(nios2_custom_fmaxd, -1)
Do not use the fmaxd custom instruction. Do not use the fmaxd custom instruction.
mcustom-fmaxd= mcustom-fmaxd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1)
Integer id (N) of fmaxd custom instruction. Integer id (N) of fmaxd custom instruction.
mno-custom-fmind mno-custom-fmind
Target Report RejectNegative Var(nios2_custom_fmind, -1) Target RejectNegative Var(nios2_custom_fmind, -1)
Do not use the fmind custom instruction. Do not use the fmind custom instruction.
mcustom-fmind= mcustom-fmind=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1)
Integer id (N) of fmind custom instruction. Integer id (N) of fmind custom instruction.
mno-custom-fdivd mno-custom-fdivd
Target Report RejectNegative Var(nios2_custom_fdivd, -1) Target RejectNegative Var(nios2_custom_fdivd, -1)
Do not use the fdivd custom instruction. Do not use the fdivd custom instruction.
mcustom-fdivd= mcustom-fdivd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1)
Integer id (N) of fdivd custom instruction. Integer id (N) of fdivd custom instruction.
mno-custom-fmuld mno-custom-fmuld
Target Report RejectNegative Var(nios2_custom_fmuld, -1) Target RejectNegative Var(nios2_custom_fmuld, -1)
Do not use the fmuld custom instruction. Do not use the fmuld custom instruction.
mcustom-fmuld= mcustom-fmuld=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1)
Integer id (N) of fmuld custom instruction. Integer id (N) of fmuld custom instruction.
mno-custom-fsubd mno-custom-fsubd
Target Report RejectNegative Var(nios2_custom_fsubd, -1) Target RejectNegative Var(nios2_custom_fsubd, -1)
Do not use the fsubd custom instruction. Do not use the fsubd custom instruction.
mcustom-fsubd= mcustom-fsubd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1)
Integer id (N) of fsubd custom instruction. Integer id (N) of fsubd custom instruction.
mno-custom-faddd mno-custom-faddd
Target Report RejectNegative Var(nios2_custom_faddd, -1) Target RejectNegative Var(nios2_custom_faddd, -1)
Do not use the faddd custom instruction. Do not use the faddd custom instruction.
mcustom-faddd= mcustom-faddd=
Target Report RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1)
Integer id (N) of faddd custom instruction. Integer id (N) of faddd custom instruction.
mno-custom-fcmpnes mno-custom-fcmpnes
Target Report RejectNegative Var(nios2_custom_fcmpnes, -1) Target RejectNegative Var(nios2_custom_fcmpnes, -1)
Do not use the fcmpnes custom instruction. Do not use the fcmpnes custom instruction.
mcustom-fcmpnes= mcustom-fcmpnes=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1)
Integer id (N) of fcmpnes custom instruction. Integer id (N) of fcmpnes custom instruction.
mno-custom-fcmpeqs mno-custom-fcmpeqs
Target Report RejectNegative Var(nios2_custom_fcmpeqs, -1) Target RejectNegative Var(nios2_custom_fcmpeqs, -1)
Do not use the fcmpeqs custom instruction. Do not use the fcmpeqs custom instruction.
mcustom-fcmpeqs= mcustom-fcmpeqs=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1)
Integer id (N) of fcmpeqs custom instruction. Integer id (N) of fcmpeqs custom instruction.
mno-custom-fcmpges mno-custom-fcmpges
Target Report RejectNegative Var(nios2_custom_fcmpges, -1) Target RejectNegative Var(nios2_custom_fcmpges, -1)
Do not use the fcmpges custom instruction. Do not use the fcmpges custom instruction.
mcustom-fcmpges= mcustom-fcmpges=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1)
Integer id (N) of fcmpges custom instruction. Integer id (N) of fcmpges custom instruction.
mno-custom-fcmpgts mno-custom-fcmpgts
Target Report RejectNegative Var(nios2_custom_fcmpgts, -1) Target RejectNegative Var(nios2_custom_fcmpgts, -1)
Do not use the fcmpgts custom instruction. Do not use the fcmpgts custom instruction.
mcustom-fcmpgts= mcustom-fcmpgts=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1)
Integer id (N) of fcmpgts custom instruction. Integer id (N) of fcmpgts custom instruction.
mno-custom-fcmples mno-custom-fcmples
Target Report RejectNegative Var(nios2_custom_fcmples, -1) Target RejectNegative Var(nios2_custom_fcmples, -1)
Do not use the fcmples custom instruction. Do not use the fcmples custom instruction.
mcustom-fcmples= mcustom-fcmples=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1)
Integer id (N) of fcmples custom instruction. Integer id (N) of fcmples custom instruction.
mno-custom-fcmplts mno-custom-fcmplts
Target Report RejectNegative Var(nios2_custom_fcmplts, -1) Target RejectNegative Var(nios2_custom_fcmplts, -1)
Do not use the fcmplts custom instruction. Do not use the fcmplts custom instruction.
mcustom-fcmplts= mcustom-fcmplts=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1)
Integer id (N) of fcmplts custom instruction. Integer id (N) of fcmplts custom instruction.
mno-custom-flogs mno-custom-flogs
Target Report RejectNegative Var(nios2_custom_flogs, -1) Target RejectNegative Var(nios2_custom_flogs, -1)
Do not use the flogs custom instruction. Do not use the flogs custom instruction.
mcustom-flogs= mcustom-flogs=
Target Report RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1)
Integer id (N) of flogs custom instruction. Integer id (N) of flogs custom instruction.
mno-custom-fexps mno-custom-fexps
Target Report RejectNegative Var(nios2_custom_fexps, -1) Target RejectNegative Var(nios2_custom_fexps, -1)
Do not use the fexps custom instruction. Do not use the fexps custom instruction.
mcustom-fexps= mcustom-fexps=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1)
Integer id (N) of fexps custom instruction. Integer id (N) of fexps custom instruction.
mno-custom-fatans mno-custom-fatans
Target Report RejectNegative Var(nios2_custom_fatans, -1) Target RejectNegative Var(nios2_custom_fatans, -1)
Do not use the fatans custom instruction. Do not use the fatans custom instruction.
mcustom-fatans= mcustom-fatans=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1)
Integer id (N) of fatans custom instruction. Integer id (N) of fatans custom instruction.
mno-custom-ftans mno-custom-ftans
Target Report RejectNegative Var(nios2_custom_ftans, -1) Target RejectNegative Var(nios2_custom_ftans, -1)
Do not use the ftans custom instruction. Do not use the ftans custom instruction.
mcustom-ftans= mcustom-ftans=
Target Report RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1)
Integer id (N) of ftans custom instruction. Integer id (N) of ftans custom instruction.
mno-custom-fsins mno-custom-fsins
Target Report RejectNegative Var(nios2_custom_fsins, -1) Target RejectNegative Var(nios2_custom_fsins, -1)
Do not use the fsins custom instruction. Do not use the fsins custom instruction.
mcustom-fsins= mcustom-fsins=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1)
Integer id (N) of fsins custom instruction. Integer id (N) of fsins custom instruction.
mno-custom-fcoss mno-custom-fcoss
Target Report RejectNegative Var(nios2_custom_fcoss, -1) Target RejectNegative Var(nios2_custom_fcoss, -1)
Do not use the fcoss custom instruction. Do not use the fcoss custom instruction.
mcustom-fcoss= mcustom-fcoss=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1)
Integer id (N) of fcoss custom instruction. Integer id (N) of fcoss custom instruction.
mno-custom-fsqrts mno-custom-fsqrts
Target Report RejectNegative Var(nios2_custom_fsqrts, -1) Target RejectNegative Var(nios2_custom_fsqrts, -1)
Do not use the fsqrts custom instruction. Do not use the fsqrts custom instruction.
mcustom-fsqrts= mcustom-fsqrts=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1)
Integer id (N) of fsqrts custom instruction. Integer id (N) of fsqrts custom instruction.
mno-custom-fabss mno-custom-fabss
Target Report RejectNegative Var(nios2_custom_fabss, -1) Target RejectNegative Var(nios2_custom_fabss, -1)
Do not use the fabss custom instr. Do not use the fabss custom instr.
mcustom-fabss= mcustom-fabss=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1)
Integer id (N) of fabss custom instruction. Integer id (N) of fabss custom instruction.
mno-custom-fnegs mno-custom-fnegs
Target Report RejectNegative Var(nios2_custom_fnegs, -1) Target RejectNegative Var(nios2_custom_fnegs, -1)
Do not use the fnegs custom instruction. Do not use the fnegs custom instruction.
mcustom-fnegs= mcustom-fnegs=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1)
Integer id (N) of fnegs custom instruction. Integer id (N) of fnegs custom instruction.
mno-custom-fmaxs mno-custom-fmaxs
Target Report RejectNegative Var(nios2_custom_fmaxs, -1) Target RejectNegative Var(nios2_custom_fmaxs, -1)
Do not use the fmaxs custom instruction. Do not use the fmaxs custom instruction.
mcustom-fmaxs= mcustom-fmaxs=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1)
Integer id (N) of fmaxs custom instruction. Integer id (N) of fmaxs custom instruction.
mno-custom-fmins mno-custom-fmins
Target Report RejectNegative Var(nios2_custom_fmins, -1) Target RejectNegative Var(nios2_custom_fmins, -1)
Do not use the fmins custom instruction. Do not use the fmins custom instruction.
mcustom-fmins= mcustom-fmins=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1)
Integer id (N) of fmins custom instruction. Integer id (N) of fmins custom instruction.
mno-custom-fdivs mno-custom-fdivs
Target Report RejectNegative Var(nios2_custom_fdivs, -1) Target RejectNegative Var(nios2_custom_fdivs, -1)
Do not use the fdivs custom instruction. Do not use the fdivs custom instruction.
mcustom-fdivs= mcustom-fdivs=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1)
Integer id (N) of fdivs custom instruction. Integer id (N) of fdivs custom instruction.
mno-custom-fmuls mno-custom-fmuls
Target Report RejectNegative Var(nios2_custom_fmuls, -1) Target RejectNegative Var(nios2_custom_fmuls, -1)
Do not use the fmuls custom instruction. Do not use the fmuls custom instruction.
mcustom-fmuls= mcustom-fmuls=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1)
Integer id (N) of fmuls custom instruction. Integer id (N) of fmuls custom instruction.
mno-custom-fsubs mno-custom-fsubs
Target Report RejectNegative Var(nios2_custom_fsubs, -1) Target RejectNegative Var(nios2_custom_fsubs, -1)
Do not use the fsubs custom instruction. Do not use the fsubs custom instruction.
mcustom-fsubs= mcustom-fsubs=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1)
Integer id (N) of fsubs custom instruction. Integer id (N) of fsubs custom instruction.
mno-custom-fadds mno-custom-fadds
Target Report RejectNegative Var(nios2_custom_fadds, -1) Target RejectNegative Var(nios2_custom_fadds, -1)
Do not use the fadds custom instruction. Do not use the fadds custom instruction.
mcustom-fadds= mcustom-fadds=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1)
Integer id (N) of fadds custom instruction. Integer id (N) of fadds custom instruction.
mno-custom-frdy mno-custom-frdy
Target Report RejectNegative Var(nios2_custom_frdy, -1) Target RejectNegative Var(nios2_custom_frdy, -1)
Do not use the frdy custom instruction. Do not use the frdy custom instruction.
mcustom-frdy= mcustom-frdy=
Target Report RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1)
Integer id (N) of frdy custom instruction. Integer id (N) of frdy custom instruction.
mno-custom-frdxhi mno-custom-frdxhi
Target Report RejectNegative Var(nios2_custom_frdxhi, -1) Target RejectNegative Var(nios2_custom_frdxhi, -1)
Do not use the frdxhi custom instruction. Do not use the frdxhi custom instruction.
mcustom-frdxhi= mcustom-frdxhi=
Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1)
Integer id (N) of frdxhi custom instruction. Integer id (N) of frdxhi custom instruction.
mno-custom-frdxlo mno-custom-frdxlo
Target Report RejectNegative Var(nios2_custom_frdxlo, -1) Target RejectNegative Var(nios2_custom_frdxlo, -1)
Do not use the frdxlo custom instruction. Do not use the frdxlo custom instruction.
mcustom-frdxlo= mcustom-frdxlo=
Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1)
Integer id (N) of frdxlo custom instruction. Integer id (N) of frdxlo custom instruction.
mno-custom-fwry mno-custom-fwry
Target Report RejectNegative Var(nios2_custom_fwry, -1) Target RejectNegative Var(nios2_custom_fwry, -1)
Do not use the fwry custom instruction. Do not use the fwry custom instruction.
mcustom-fwry= mcustom-fwry=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1)
Integer id (N) of fwry custom instruction. Integer id (N) of fwry custom instruction.
mno-custom-fwrx mno-custom-fwrx
Target Report RejectNegative Var(nios2_custom_fwrx, -1) Target RejectNegative Var(nios2_custom_fwrx, -1)
Do not use the fwrx custom instruction. Do not use the fwrx custom instruction.
mcustom-fwrx= mcustom-fwrx=
Target Report RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1)
Integer id (N) of fwrx custom instruction. Integer id (N) of fwrx custom instruction.
mno-custom-round mno-custom-round
Target Report RejectNegative Var(nios2_custom_round, -1) Target RejectNegative Var(nios2_custom_round, -1)
Do not use the round custom instruction. Do not use the round custom instruction.
mcustom-round= mcustom-round=
Target Report RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1) Target RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1)
Integer id (N) of round custom instruction. Integer id (N) of round custom instruction.
march= march=
@ -580,11 +580,11 @@ EnumValue
Enum(nios2_arch_type) String(r2) Value(ARCH_R2) Enum(nios2_arch_type) String(r2) Value(ARCH_R2)
mbmx mbmx
Target Report Mask(HAS_BMX) Target Mask(HAS_BMX)
Enable generation of R2 BMX instructions. Enable generation of R2 BMX instructions.
mcdx mcdx
Target Report Mask(HAS_CDX) Target Mask(HAS_CDX)
Enable generation of R2 CDX instructions. Enable generation of R2 CDX instructions.
mgprel-sec= mgprel-sec=

16
gcc/config/nvptx/nvptx.opt
View File

@ -20,35 +20,35 @@
; It's not clear whether this was ever build/tested/used, so this is no longer ; It's not clear whether this was ever build/tested/used, so this is no longer
; exposed to the user. ; exposed to the user.
;m32 ;m32
;Target Report RejectNegative InverseMask(ABI64) ;Target RejectNegative InverseMask(ABI64)
;Generate code for a 32-bit ABI. ;Generate code for a 32-bit ABI.
m64 m64
Target Report RejectNegative Mask(ABI64) Target RejectNegative Mask(ABI64)
Generate code for a 64-bit ABI. Generate code for a 64-bit ABI.
mmainkernel mmainkernel
Target Report RejectNegative Target RejectNegative
Link in code for a __main kernel. Link in code for a __main kernel.
moptimize moptimize
Target Report Var(nvptx_optimize) Init(-1) Target Var(nvptx_optimize) Init(-1)
Optimize partition neutering. Optimize partition neutering.
msoft-stack msoft-stack
Target Report Mask(SOFT_STACK) Target Mask(SOFT_STACK)
Use custom stacks instead of local memory for automatic storage. Use custom stacks instead of local memory for automatic storage.
msoft-stack-reserve-local= msoft-stack-reserve-local=
Target Report Joined RejectNegative UInteger Var(nvptx_softstack_size) Init(128) Target Joined RejectNegative UInteger Var(nvptx_softstack_size) Init(128)
Specify size of .local memory used for stack when the exact amount is not known. Specify size of .local memory used for stack when the exact amount is not known.
muniform-simt muniform-simt
Target Report Mask(UNIFORM_SIMT) Target Mask(UNIFORM_SIMT)
Generate code that can keep local state uniform across all lanes. Generate code that can keep local state uniform across all lanes.
mgomp mgomp
Target Report Mask(GOMP) Target Mask(GOMP)
Generate code for OpenMP offloading: enables -msoft-stack and -muniform-simt. Generate code for OpenMP offloading: enables -msoft-stack and -muniform-simt.
Enum Enum

26
gcc/config/pa/pa.opt
View File

@ -42,23 +42,23 @@ Target Ignore
Does nothing. Preserved for backward compatibility. Does nothing. Preserved for backward compatibility.
mcaller-copies mcaller-copies
Target Report Mask(CALLER_COPIES) Target Mask(CALLER_COPIES)
Caller copies function arguments passed by hidden reference. Caller copies function arguments passed by hidden reference.
mcoherent-ldcw mcoherent-ldcw
Target Report Var(TARGET_COHERENT_LDCW) Init(1) Target Var(TARGET_COHERENT_LDCW) Init(1)
Use ldcw/ldcd coherent cache-control hint. Use ldcw/ldcd coherent cache-control hint.
mdisable-fpregs mdisable-fpregs
Target Report Mask(DISABLE_FPREGS) Target Mask(DISABLE_FPREGS)
Disable FP regs. Disable FP regs.
mdisable-indexing mdisable-indexing
Target Report Mask(DISABLE_INDEXING) Target Mask(DISABLE_INDEXING)
Disable indexed addressing. Disable indexed addressing.
mfast-indirect-calls mfast-indirect-calls
Target Report Mask(FAST_INDIRECT_CALLS) Target Mask(FAST_INDIRECT_CALLS)
Generate fast indirect calls. Generate fast indirect calls.
mfixed-range= mfixed-range=
@ -66,7 +66,7 @@ Target RejectNegative Joined Var(pa_deferred_options) Defer
Specify range of registers to make fixed. Specify range of registers to make fixed.
mgas mgas
Target Report Mask(GAS) Target Mask(GAS)
Assume code will be assembled by GAS. Assume code will be assembled by GAS.
mjump-in-delay mjump-in-delay
@ -79,11 +79,11 @@ Target RejectNegative
Enable linker optimizations. Enable linker optimizations.
mlong-calls mlong-calls
Target Report Mask(LONG_CALLS) Target Mask(LONG_CALLS)
Always generate long calls. Always generate long calls.
mlong-load-store mlong-load-store
Target Report Mask(LONG_LOAD_STORE) Target Mask(LONG_LOAD_STORE)
Emit long load/store sequences. Emit long load/store sequences.
mnosnake mnosnake
@ -91,11 +91,11 @@ Target RejectNegative
Generate PA1.0 code. Generate PA1.0 code.
mno-space-regs mno-space-regs
Target RejectNegative Report Mask(NO_SPACE_REGS) Target RejectNegative Mask(NO_SPACE_REGS)
Disable space regs. Disable space regs.
mordered mordered
Target Report Var(TARGET_ORDERED) Init(0) Target Var(TARGET_ORDERED) Init(0)
Assume memory references are ordered and barriers are not needed. Assume memory references are ordered and barriers are not needed.
mpa-risc-1-0 mpa-risc-1-0
@ -111,7 +111,7 @@ Target RejectNegative Mask(PA_20)
Generate PA2.0 code (requires binutils 2.10 or later). Generate PA2.0 code (requires binutils 2.10 or later).
mportable-runtime mportable-runtime
Target Report Mask(PORTABLE_RUNTIME) Target Mask(PORTABLE_RUNTIME)
Use portable calling conventions. Use portable calling conventions.
mschedule= mschedule=
@ -140,7 +140,7 @@ EnumValue
Enum(pa_schedule) String(7300) Value(PROCESSOR_7300) Enum(pa_schedule) String(7300) Value(PROCESSOR_7300)
msoft-float msoft-float
Target Report Mask(SOFT_FLOAT) Target Mask(SOFT_FLOAT)
Use software floating point. Use software floating point.
msnake msnake
@ -148,5 +148,5 @@ Target RejectNegative
Generate PA1.1 code. Generate PA1.1 code.
mspace-regs mspace-regs
Target RejectNegative Report InverseMask(NO_SPACE_REGS) Target RejectNegative InverseMask(NO_SPACE_REGS)
Do not disable space regs. Do not disable space regs.

24
gcc/config/pdp11/pdp11.opt
View File

@ -23,49 +23,49 @@ Target RejectNegative
Generate code for an 11/10. Generate code for an 11/10.
m40 m40
Target Report Mask(40) Target Mask(40)
Generate code for an 11/40. Generate code for an 11/40.
m45 m45
Target Report Mask(45) Target Mask(45)
Generate code for an 11/45. Generate code for an 11/45.
mac0 mac0
Target Report Mask(AC0) Target Mask(AC0)
Return floating-point results in ac0 (fr0 in Unix assembler syntax). Return floating-point results in ac0 (fr0 in Unix assembler syntax).
mdec-asm mdec-asm
Target RejectNegative Report Mask(DEC_ASM) Negative(mgnu-asm) Target RejectNegative Mask(DEC_ASM) Negative(mgnu-asm)
Use the DEC assembler syntax. Use the DEC assembler syntax.
mgnu-asm mgnu-asm
Target RejectNegative Report Mask(GNU_ASM) Negative(munix-asm) Target RejectNegative Mask(GNU_ASM) Negative(munix-asm)
Use the GNU assembler syntax. Use the GNU assembler syntax.
mfpu mfpu
Target RejectNegative Report Mask(FPU) Target RejectNegative Mask(FPU)
Use hardware floating point. Use hardware floating point.
mint16 mint16
Target Report InverseMask(INT32, INT16) Target InverseMask(INT32, INT16)
Use 16 bit int. Use 16 bit int.
mint32 mint32
Target Report Mask(INT32) Target Mask(INT32)
Use 32 bit int. Use 32 bit int.
msoft-float msoft-float
Target RejectNegative Report InverseMask(FPU, SOFT_FLOAT) Target RejectNegative InverseMask(FPU, SOFT_FLOAT)
Do not use hardware floating point. Do not use hardware floating point.
msplit msplit
Target Report Mask(SPLIT) Target Mask(SPLIT)
Target has split I&D. Target has split I&D.
munix-asm munix-asm
Target RejectNegative Report Mask(UNIX_ASM) Negative(mdec-asm) Target RejectNegative Mask(UNIX_ASM) Negative(mdec-asm)
Use UNIX assembler syntax. Use UNIX assembler syntax.
mlra mlra
Target Report Mask(LRA) Target Mask(LRA)
Use LRA register allocator. Use LRA register allocator.

6
gcc/config/pru/pru.opt
View File

@ -22,7 +22,7 @@ HeaderInclude
config/pru/pru-opts.h config/pru/pru-opts.h
minrt minrt
Target Report Mask(MINRT) RejectNegative Target Mask(MINRT) RejectNegative
Use a minimum runtime (no static initializers or ctors) for memory-constrained Use a minimum runtime (no static initializers or ctors) for memory-constrained
devices. devices.
@ -31,7 +31,7 @@ Target RejectNegative Joined
-mmcu=MCU Select the target System-On-Chip variant that embeds this PRU. -mmcu=MCU Select the target System-On-Chip variant that embeds this PRU.
mno-relax mno-relax
Target Report RejectNegative Target RejectNegative
Make GCC pass the --no-relax command-line option to the linker instead of Make GCC pass the --no-relax command-line option to the linker instead of
the --relax option. the --relax option.
@ -40,7 +40,7 @@ Target Mask(OPT_LOOP)
Allow (or do not allow) gcc to use the LOOP instruction. Allow (or do not allow) gcc to use the LOOP instruction.
mabi= mabi=
Target RejectNegative Report Joined Enum(pru_abi_t) Var(pru_current_abi) Init(PRU_ABI_GNU) Save Target RejectNegative Joined Enum(pru_abi_t) Var(pru_current_abi) Init(PRU_ABI_GNU) Save
Select target ABI variant. Select target ABI variant.
Enum Enum

22
gcc/config/riscv/riscv.opt
View File

@ -26,11 +26,11 @@ Target RejectNegative Joined UInteger Var(riscv_branch_cost)
-mbranch-cost=N Set the cost of branches to roughly N instructions. -mbranch-cost=N Set the cost of branches to roughly N instructions.
mplt mplt
Target Report Var(TARGET_PLT) Init(1) Target Var(TARGET_PLT) Init(1)
When generating -fpic code, allow the use of PLTs. Ignored for fno-pic. When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
mabi= mabi=
Target Report RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32)
Specify integer and floating-point calling convention. Specify integer and floating-point calling convention.
mpreferred-stack-boundary= mpreferred-stack-boundary=
@ -63,15 +63,15 @@ EnumValue
Enum(abi_type) String(lp64d) Value(ABI_LP64D) Enum(abi_type) String(lp64d) Value(ABI_LP64D)
mfdiv mfdiv
Target Report Mask(FDIV) Target Mask(FDIV)
Use hardware floating-point divide and square root instructions. Use hardware floating-point divide and square root instructions.
mdiv mdiv
Target Report Mask(DIV) Target Mask(DIV)
Use hardware instructions for integer division. Use hardware instructions for integer division.
march= march=
Target Report RejectNegative Joined Target RejectNegative Joined
-march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be
lower-case. lower-case.
@ -88,7 +88,7 @@ Target Joined Separate UInteger Var(g_switch_value) Init(8)
-msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets). -msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets).
msave-restore msave-restore
Target Report Mask(SAVE_RESTORE) Target Mask(SAVE_RESTORE)
Use smaller but slower prologue and epilogue code. Use smaller but slower prologue and epilogue code.
mshorten-memrefs mshorten-memrefs
@ -98,11 +98,11 @@ memory accesses to be generated as compressed instructions. Currently targets
32-bit integer load/stores. 32-bit integer load/stores.
mcmodel= mcmodel=
Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) Target RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL)
Specify the code model. Specify the code model.
mstrict-align mstrict-align
Target Report Mask(STRICT_ALIGN) Save Target Mask(STRICT_ALIGN) Save
Do not generate unaligned memory accesses. Do not generate unaligned memory accesses.
Enum Enum
@ -116,7 +116,7 @@ EnumValue
Enum(code_model) String(medany) Value(CM_MEDANY) Enum(code_model) String(medany) Value(CM_MEDANY)
mexplicit-relocs mexplicit-relocs
Target Report Mask(EXPLICIT_RELOCS) Target Mask(EXPLICIT_RELOCS)
Use %reloc() operators, rather than assembly macros, to load addresses. Use %reloc() operators, rather than assembly macros, to load addresses.
mrelax mrelax
@ -139,7 +139,7 @@ Mask(RVC)
Mask(RVE) Mask(RVE)
mriscv-attribute mriscv-attribute
Target Report Var(riscv_emit_attribute_p) Init(-1) Target Var(riscv_emit_attribute_p) Init(-1)
Emit RISC-V ELF attribute. Emit RISC-V ELF attribute.
malign-data= malign-data=
@ -201,5 +201,5 @@ EnumValue
Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213) Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213)
misa-spec= misa-spec=
Target Report RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC) Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
Set the version of RISC-V ISA spec. Set the version of RISC-V ISA spec.

18
gcc/config/rl78/rl78.opt
View File

@ -23,11 +23,11 @@ HeaderInclude
config/rl78/rl78-opts.h config/rl78/rl78-opts.h
msim msim
Target Report Target
Use the simulator runtime. Use the simulator runtime.
mmul= mmul=
Target RejectNegative Joined Var(rl78_mul_type) Report Tolower Enum(rl78_mul_types) Init(MUL_UNINIT) Target RejectNegative Joined Var(rl78_mul_type) Tolower Enum(rl78_mul_types) Init(MUL_UNINIT)
Selects the type of hardware multiplication and division to use (none/g13/g14). Selects the type of hardware multiplication and division to use (none/g13/g14).
Enum Enum
@ -46,15 +46,15 @@ EnumValue
Enum(rl78_mul_types) String(rl78) Value(MUL_G14) Enum(rl78_mul_types) String(rl78) Value(MUL_G14)
mallregs mallregs
Target Mask(ALLREGS) Report Optimization Target Mask(ALLREGS) Optimization
Use all registers, reserving none for interrupt handlers. Use all registers, reserving none for interrupt handlers.
mrelax mrelax
Target Report Optimization Target Optimization
Enable assembler and linker relaxation. Enabled by default at -Os. Enable assembler and linker relaxation. Enabled by default at -Os.
mcpu= mcpu=
Target RejectNegative Joined Var(rl78_cpu_type) Report ToLower Enum(rl78_cpu_types) Init(CPU_UNINIT) Target RejectNegative Joined Var(rl78_cpu_type) ToLower Enum(rl78_cpu_types) Init(CPU_UNINIT)
Selects the type of RL78 core being targeted (g10/g13/g14). The default is the G14. If set, also selects the hardware multiply support to be used. Selects the type of RL78 core being targeted (g10/g13/g14). The default is the G14. If set, also selects the hardware multiply support to be used.
Enum Enum
@ -73,19 +73,19 @@ EnumValue
Enum(rl78_cpu_types) String(rl78) Value(CPU_G14) Enum(rl78_cpu_types) String(rl78) Value(CPU_G14)
mg10 mg10
Target RejectNegative Report Alias(mcpu=, g10) Target RejectNegative Alias(mcpu=, g10)
Alias for -mcpu=g10. Alias for -mcpu=g10.
mg13 mg13
Target RejectNegative Report Alias(mcpu=, g13) Target RejectNegative Alias(mcpu=, g13)
Alias for -mcpu=g13. Alias for -mcpu=g13.
mg14 mg14
Target RejectNegative Report Alias(mcpu=, g14) Target RejectNegative Alias(mcpu=, g14)
Alias for -mcpu=g14. Alias for -mcpu=g14.
mrl78 mrl78
Target RejectNegative Report Alias(mcpu=, g14) Target RejectNegative Alias(mcpu=, g14)
Alias for -mcpu=g14. Alias for -mcpu=g14.
mes0 mes0

6
gcc/config/rs6000/aix64.opt
View File

@ -20,11 +20,11 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
maix64 maix64
Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Target RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags)
Compile for 64-bit pointers. Compile for 64-bit pointers.
maix32 maix32
Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Target RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags)
Compile for 32-bit pointers. Compile for 32-bit pointers.
mcmodel= mcmodel=
@ -45,7 +45,7 @@ EnumValue
Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE) Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE)
mpe mpe
Target Report RejectNegative Var(internal_nothing_1) Save Target RejectNegative Var(internal_nothing_1) Save
Support message passing with the Parallel Environment. Support message passing with the Parallel Environment.
posix posix

2
gcc/config/rs6000/linux64.opt
View File

@ -20,7 +20,7 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mprofile-kernel mprofile-kernel
Target Report Var(profile_kernel) Save Target Var(profile_kernel) Save
Call mcount for profiling before a function prologue. Call mcount for profiling before a function prologue.
mcmodel= mcmodel=

126
gcc/config/rs6000/rs6000.opt
View File

@ -117,31 +117,31 @@ mpowerpc
Target RejectNegative Undocumented Ignore Target RejectNegative Undocumented Ignore
mpowerpc64 mpowerpc64
Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Target Mask(POWERPC64) Var(rs6000_isa_flags)
Use PowerPC-64 instruction set. Use PowerPC-64 instruction set.
mpowerpc-gpopt mpowerpc-gpopt
Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Target Mask(PPC_GPOPT) Var(rs6000_isa_flags)
Use PowerPC General Purpose group optional instructions. Use PowerPC General Purpose group optional instructions.
mpowerpc-gfxopt mpowerpc-gfxopt
Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Target Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
Use PowerPC Graphics group optional instructions. Use PowerPC Graphics group optional instructions.
mmfcrf mmfcrf
Target Report Mask(MFCRF) Var(rs6000_isa_flags) Target Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction. Use PowerPC V2.01 single field mfcr instruction.
mpopcntb mpopcntb
Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Target Mask(POPCNTB) Var(rs6000_isa_flags)
Use PowerPC V2.02 popcntb instruction. Use PowerPC V2.02 popcntb instruction.
mfprnd mfprnd
Target Report Mask(FPRND) Var(rs6000_isa_flags) Target Mask(FPRND) Var(rs6000_isa_flags)
Use PowerPC V2.02 floating point rounding instructions. Use PowerPC V2.02 floating point rounding instructions.
mcmpb mcmpb
Target Report Mask(CMPB) Var(rs6000_isa_flags) Target Mask(CMPB) Var(rs6000_isa_flags)
Use PowerPC V2.05 compare bytes instruction. Use PowerPC V2.05 compare bytes instruction.
;; This option existed in the past, but now is always off. ;; This option existed in the past, but now is always off.
@ -152,27 +152,27 @@ mmfpgpr
Target RejectNegative Undocumented WarnRemoved Target RejectNegative Undocumented WarnRemoved
maltivec maltivec
Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Target Mask(ALTIVEC) Var(rs6000_isa_flags)
Use AltiVec instructions. Use AltiVec instructions.
mfold-gimple mfold-gimple
Target Report Var(rs6000_fold_gimple) Init(1) Target Var(rs6000_fold_gimple) Init(1)
Enable early gimple folding of builtins. Enable early gimple folding of builtins.
mhard-dfp mhard-dfp
Target Report Mask(DFP) Var(rs6000_isa_flags) Target Mask(DFP) Var(rs6000_isa_flags)
Use decimal floating point instructions. Use decimal floating point instructions.
mmulhw mmulhw
Target Report Mask(MULHW) Var(rs6000_isa_flags) Target Mask(MULHW) Var(rs6000_isa_flags)
Use 4xx half-word multiply instructions. Use 4xx half-word multiply instructions.
mdlmzb mdlmzb
Target Report Mask(DLMZB) Var(rs6000_isa_flags) Target Mask(DLMZB) Var(rs6000_isa_flags)
Use 4xx string-search dlmzb instruction. Use 4xx string-search dlmzb instruction.
mmultiple mmultiple
Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Target Mask(MULTIPLE) Var(rs6000_isa_flags)
Generate load/store multiple instructions. Generate load/store multiple instructions.
;; This option existed in the past, but now is always off. ;; This option existed in the past, but now is always off.
@ -183,19 +183,19 @@ mstring
Target RejectNegative Undocumented WarnRemoved Target RejectNegative Undocumented WarnRemoved
msoft-float msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Target RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
Do not use hardware floating point. Do not use hardware floating point.
mhard-float mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point. Use hardware floating point.
mpopcntd mpopcntd
Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Target Mask(POPCNTD) Var(rs6000_isa_flags)
Use PowerPC V2.06 popcntd instruction. Use PowerPC V2.06 popcntd instruction.
mfriz mfriz
Target Report Var(TARGET_FRIZ) Init(-1) Save Target Var(TARGET_FRIZ) Init(-1) Save
Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
mveclibabi= mveclibabi=
@ -203,11 +203,11 @@ Target RejectNegative Joined Var(rs6000_veclibabi_name)
Vector library ABI to use. Vector library ABI to use.
mvsx mvsx
Target Report Mask(VSX) Var(rs6000_isa_flags) Target Mask(VSX) Var(rs6000_isa_flags)
Use vector/scalar (VSX) instructions. Use vector/scalar (VSX) instructions.
mvsx-align-128 mvsx-align-128
Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save Target Undocumented Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64 ; If -mvsx, set alignment to 128 bits instead of 32/64
mallow-movmisalign mallow-movmisalign
@ -215,74 +215,74 @@ Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
; Allow the movmisalign in DF/DI vectors ; Allow the movmisalign in DF/DI vectors
mefficient-unaligned-vsx mefficient-unaligned-vsx
Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) Target Undocumented Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
; Consider unaligned VSX vector and fp accesses to be efficient ; Consider unaligned VSX vector and fp accesses to be efficient
msched-groups msched-groups
Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save Target Undocumented Var(TARGET_SCHED_GROUPS) Init(-1) Save
; Explicitly set rs6000_sched_groups ; Explicitly set rs6000_sched_groups
malways-hint malways-hint
Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save Target Undocumented Var(TARGET_ALWAYS_HINT) Init(-1) Save
; Explicitly set rs6000_always_hint ; Explicitly set rs6000_always_hint
malign-branch-targets malign-branch-targets
Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save Target Undocumented Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
; Explicitly set rs6000_align_branch_targets ; Explicitly set rs6000_align_branch_targets
mno-update mno-update
Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Target RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
Do not generate load/store with update instructions. Do not generate load/store with update instructions.
mupdate mupdate
Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Target RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
Generate load/store with update instructions. Generate load/store with update instructions.
msingle-pic-base msingle-pic-base
Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) Target Var(TARGET_SINGLE_PIC_BASE) Init(0)
Do not load the PIC register in function prologues. Do not load the PIC register in function prologues.
mavoid-indexed-addresses mavoid-indexed-addresses
Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save Target Var(TARGET_AVOID_XFORM) Init(-1) Save
Avoid generation of indexed load/store instructions when possible. Avoid generation of indexed load/store instructions when possible.
msched-epilog msched-epilog
Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
msched-prolog msched-prolog
Target Report Var(TARGET_SCHED_PROLOG) Save Target Var(TARGET_SCHED_PROLOG) Save
Schedule the start and end of the procedure. Schedule the start and end of the procedure.
maix-struct-return maix-struct-return
Target Report RejectNegative Var(aix_struct_return) Save Target RejectNegative Var(aix_struct_return) Save
Return all structures in memory (AIX default). Return all structures in memory (AIX default).
msvr4-struct-return msvr4-struct-return
Target Report RejectNegative Var(aix_struct_return,0) Save Target RejectNegative Var(aix_struct_return,0) Save
Return small structures in registers (SVR4 default). Return small structures in registers (SVR4 default).
mxl-compat mxl-compat
Target Report Var(TARGET_XL_COMPAT) Save Target Var(TARGET_XL_COMPAT) Save
Conform more closely to IBM XLC semantics. Conform more closely to IBM XLC semantics.
mrecip mrecip
Target Report Target
Generate software reciprocal divide and square root for better throughput. Generate software reciprocal divide and square root for better throughput.
mrecip= mrecip=
Target Report RejectNegative Joined Var(rs6000_recip_name) Target RejectNegative Joined Var(rs6000_recip_name)
Generate software reciprocal divide and square root for better throughput. Generate software reciprocal divide and square root for better throughput.
mrecip-precision mrecip-precision
Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Target Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
Assume that the reciprocal estimate instructions provide more accuracy. Assume that the reciprocal estimate instructions provide more accuracy.
mno-fp-in-toc mno-fp-in-toc
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save Target RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
Do not place floating point constants in TOC. Do not place floating point constants in TOC.
mfp-in-toc mfp-in-toc
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save Target RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
Place floating point constants in TOC. Place floating point constants in TOC.
mno-sum-in-toc mno-sum-in-toc
@ -301,15 +301,15 @@ Place symbol+offset constants in TOC.
; This is at the cost of having 2 extra loads and one extra store per ; This is at the cost of having 2 extra loads and one extra store per
; function, and one less allocable register. ; function, and one less allocable register.
mminimal-toc mminimal-toc
Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Target Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
Use only one TOC entry per procedure. Use only one TOC entry per procedure.
mfull-toc mfull-toc
Target Report Target
Put everything in the regular TOC. Put everything in the regular TOC.
mvrsave mvrsave
Target Report Var(TARGET_ALTIVEC_VRSAVE) Save Target Var(TARGET_ALTIVEC_VRSAVE) Save
Generate VRSAVE instructions when generating AltiVec code. Generate VRSAVE instructions when generating AltiVec code.
mvrsave=no mvrsave=no
@ -321,11 +321,11 @@ Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<
Deprecated option. Use -mvrsave instead. Deprecated option. Use -mvrsave instead.
mblock-move-inline-limit= mblock-move-inline-limit=
Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save Target Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
Max number of bytes to move inline. Max number of bytes to move inline.
mblock-ops-unaligned-vsx mblock-ops-unaligned-vsx
Target Report Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags) Target Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags)
Generate unaligned VSX load/store for inline expansion of memcpy/memmove. Generate unaligned VSX load/store for inline expansion of memcpy/memmove.
mblock-ops-vector-pair mblock-ops-vector-pair
@ -333,19 +333,19 @@ Target Undocumented Mask(BLOCK_OPS_VECTOR_PAIR) Var(rs6000_isa_flags)
Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove. Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove.
mblock-compare-inline-limit= mblock-compare-inline-limit=
Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save Target Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
Max number of bytes to compare without loops. Max number of bytes to compare without loops.
mblock-compare-inline-loop-limit= mblock-compare-inline-loop-limit=
Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save Target Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
Max number of bytes to compare with loops. Max number of bytes to compare with loops.
mstring-compare-inline-limit= mstring-compare-inline-limit=
Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save Target Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
Max number of bytes to compare. Max number of bytes to compare.
misel misel
Target Report Mask(ISEL) Var(rs6000_isa_flags) Target Mask(ISEL) Var(rs6000_isa_flags)
Generate isel instructions. Generate isel instructions.
mdebug= mdebug=
@ -409,7 +409,7 @@ EnumValue
Enum(rs6000_traceback_type) String(no) Value(traceback_none) Enum(rs6000_traceback_type) String(no) Value(traceback_none)
mlongcall mlongcall
Target Report Var(rs6000_default_long_calls) Save Target Var(rs6000_default_long_calls) Save
Avoid all range limits on call instructions. Avoid all range limits on call instructions.
; This option existed in the past, but now is always on. ; This option existed in the past, but now is always on.
@ -456,11 +456,11 @@ Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority
Specify scheduling priority for dispatch slot restricted insns. Specify scheduling priority for dispatch slot restricted insns.
mpointers-to-nested-functions mpointers-to-nested-functions
Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save Target Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use r11 to hold the static link in calls to functions via pointers. Use r11 to hold the static link in calls to functions via pointers.
msave-toc-indirect msave-toc-indirect
Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) Target Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Save the TOC in the prologue for indirect calls rather than inline. Save the TOC in the prologue for indirect calls rather than inline.
; This option existed in the past, but now is always the same as -mvsx. ; This option existed in the past, but now is always the same as -mvsx.
@ -468,7 +468,7 @@ mvsx-timode
Target RejectNegative Undocumented Ignore Target RejectNegative Undocumented Ignore
mpower8-fusion mpower8-fusion
Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) Target Mask(P8_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power8. Fuse certain integer operations together for better performance on power8.
mpower8-fusion-sign mpower8-fusion-sign
@ -476,30 +476,30 @@ Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
Allow sign extension in fusion operations. Allow sign extension in fusion operations.
mpower8-vector mpower8-vector
Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) Target Mask(P8_VECTOR) Var(rs6000_isa_flags)
Use vector and scalar instructions added in ISA 2.07. Use vector and scalar instructions added in ISA 2.07.
mcrypto mcrypto
Target Report Mask(CRYPTO) Var(rs6000_isa_flags) Target Mask(CRYPTO) Var(rs6000_isa_flags)
Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
mdirect-move mdirect-move
Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) WarnRemoved Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) WarnRemoved
mhtm mhtm
Target Report Mask(HTM) Var(rs6000_isa_flags) Target Mask(HTM) Var(rs6000_isa_flags)
Use ISA 2.07 transactional memory (HTM) instructions. Use ISA 2.07 transactional memory (HTM) instructions.
mquad-memory mquad-memory
Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) Target Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
Generate the quad word memory instructions (lq/stq). Generate the quad word memory instructions (lq/stq).
mquad-memory-atomic mquad-memory-atomic
Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) Target Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
Generate the quad word memory atomic instructions (lqarx/stqcx). Generate the quad word memory atomic instructions (lqarx/stqcx).
mcompat-align-parm mcompat-align-parm
Target Report Var(rs6000_compat_align_parm) Init(0) Save Target Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment. Generate aggregate parameter passing code with at most 64-bit alignment.
moptimize-swaps moptimize-swaps
@ -511,11 +511,11 @@ Target Undocumented Var(unroll_only_small_loops) Init(0) Save
; Use conservative small loop unrolling. ; Use conservative small loop unrolling.
mpower9-misc mpower9-misc
Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) Target Undocumented Mask(P9_MISC) Var(rs6000_isa_flags)
Use certain scalar instructions added in ISA 3.0. Use certain scalar instructions added in ISA 3.0.
mpower9-vector mpower9-vector
Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags) Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use vector instructions added in ISA 3.0. Use vector instructions added in ISA 3.0.
mpower9-minmax mpower9-minmax
@ -527,15 +527,15 @@ Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
Fuse medium/large code model toc references with the memory instruction. Fuse medium/large code model toc references with the memory instruction.
mmodulo mmodulo
Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags) Target Undocumented Mask(MODULO) Var(rs6000_isa_flags)
Generate the integer modulo instructions. Generate the integer modulo instructions.
mfloat128 mfloat128
Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags) Target Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
Enable IEEE 128-bit floating point via the __float128 keyword. Enable IEEE 128-bit floating point via the __float128 keyword.
mfloat128-hardware mfloat128-hardware
Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) Target Mask(FLOAT128_HW) Var(rs6000_isa_flags)
Enable using IEEE 128-bit floating point instructions. Enable using IEEE 128-bit floating point instructions.
mfloat128-convert mfloat128-convert
@ -579,15 +579,15 @@ mpower10
Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
mprefixed mprefixed
Target Report Mask(PREFIXED) Var(rs6000_isa_flags) Target Mask(PREFIXED) Var(rs6000_isa_flags)
Generate (do not generate) prefixed memory instructions. Generate (do not generate) prefixed memory instructions.
mpcrel mpcrel
Target Report Mask(PCREL) Var(rs6000_isa_flags) Target Mask(PCREL) Var(rs6000_isa_flags)
Generate (do not generate) pc-relative memory addressing. Generate (do not generate) pc-relative memory addressing.
mmma mmma
Target Report Mask(MMA) Var(rs6000_isa_flags) Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions. Generate (do not generate) MMA instructions.
mrelative-jumptables mrelative-jumptables

32
gcc/config/rs6000/sysv4.opt
View File

@ -28,7 +28,7 @@ Target RejectNegative Joined Var(rs6000_sdata_name)
-msdata=[none,data,sysv,eabi] Select method for sdata handling. -msdata=[none,data,sysv,eabi] Select method for sdata handling.
mreadonly-in-sdata mreadonly-in-sdata
Target Report Var(rs6000_readonly_in_sdata) Init(1) Save Target Var(rs6000_readonly_in_sdata) Init(1) Save
Allow readonly data in sdata. Allow readonly data in sdata.
mtls-size= mtls-size=
@ -48,16 +48,16 @@ EnumValue
Enum(rs6000_tls_size) String(64) Value(64) Enum(rs6000_tls_size) String(64) Value(64)
mbit-align mbit-align
Target Report Var(TARGET_NO_BITFIELD_TYPE) Save Target Var(TARGET_NO_BITFIELD_TYPE) Save
Align to the base type of the bit-field. Align to the base type of the bit-field.
mstrict-align mstrict-align
Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Target Mask(STRICT_ALIGN) Var(rs6000_isa_flags)
Align to the base type of the bit-field. Align to the base type of the bit-field.
Don't assume that unaligned accesses are handled by the system. Don't assume that unaligned accesses are handled by the system.
mrelocatable mrelocatable
Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Target Mask(RELOCATABLE) Var(rs6000_isa_flags)
Produce code relocatable at runtime. Produce code relocatable at runtime.
mrelocatable-lib mrelocatable-lib
@ -65,19 +65,19 @@ Target
Produce code relocatable at runtime. Produce code relocatable at runtime.
mlittle-endian mlittle-endian
Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Target RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce little endian code. Produce little endian code.
mlittle mlittle
Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Target RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce little endian code. Produce little endian code.
mbig-endian mbig-endian
Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Target RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce big endian code. Produce big endian code.
mbig mbig
Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Target RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce big endian code. Produce big endian code.
;; FIXME: This does nothing. What should be done? ;; FIXME: This does nothing. What should be done?
@ -99,11 +99,11 @@ Target RejectNegative
No description yet. No description yet.
meabi meabi
Target Report Mask(EABI) Var(rs6000_isa_flags) Target Mask(EABI) Var(rs6000_isa_flags)
Use EABI. Use EABI.
mbit-word mbit-word
Target Report Var(TARGET_NO_BITFIELD_WORD) Save Target Var(TARGET_NO_BITFIELD_WORD) Save
Allow bit-fields to cross word boundaries. Allow bit-fields to cross word boundaries.
mregnames mregnames
@ -141,11 +141,11 @@ Target RejectNegative
No description yet. No description yet.
m64 m64
Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
Generate 64-bit code. Generate 64-bit code.
m32 m32
Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
Generate 32-bit code. Generate 32-bit code.
mnewlib mnewlib
@ -153,17 +153,17 @@ Target RejectNegative
No description yet. No description yet.
msecure-plt msecure-plt
Target Report RejectNegative Var(secure_plt, 1) Save Target RejectNegative Var(secure_plt, 1) Save
Generate code to use a non-exec PLT and GOT. Generate code to use a non-exec PLT and GOT.
mbss-plt mbss-plt
Target Report RejectNegative Var(secure_plt, 0) Save Target RejectNegative Var(secure_plt, 0) Save
Generate code for old exec BSS PLT. Generate code for old exec BSS PLT.
mpltseq mpltseq
Target Report Var(rs6000_pltseq) Init(1) Save Target Var(rs6000_pltseq) Init(1) Save
Use inline plt sequences to implement long calls and -fno-plt. Use inline plt sequences to implement long calls and -fno-plt.
mgnu-attribute mgnu-attribute
Target Report Var(rs6000_gnu_attr) Init(1) Save Target Var(rs6000_gnu_attr) Init(1) Save
Emit .gnu_attribute tags. Emit .gnu_attribute tags.

2
gcc/config/rx/elf.opt
View File

@ -28,7 +28,7 @@ Use the simulator runtime.
;--------------------------------------------------- ;---------------------------------------------------
mas100-syntax mas100-syntax
Target Mask(AS100_SYNTAX) Report Target Mask(AS100_SYNTAX)
Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatible syntax. Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatible syntax.
;--------------------------------------------------- ;---------------------------------------------------

26
gcc/config/rx/rx.opt
View File

@ -25,11 +25,11 @@ config/rx/rx-opts.h
; The default is -fpu -m32bit-doubles. ; The default is -fpu -m32bit-doubles.
m64bit-doubles m64bit-doubles
Target RejectNegative Mask(64BIT_DOUBLES) Report Target RejectNegative Mask(64BIT_DOUBLES)
Store doubles in 64 bits. Store doubles in 64 bits.
m32bit-doubles m32bit-doubles
Target RejectNegative InverseMask(64BIT_DOUBLES) Report Target RejectNegative InverseMask(64BIT_DOUBLES)
Stores doubles in 32 bits. This is the default. Stores doubles in 32 bits. This is the default.
nofpu nofpu
@ -37,16 +37,16 @@ Target RejectNegative Alias(mnofpu)
Disable the use of RX FPU instructions. Disable the use of RX FPU instructions.
mnofpu mnofpu
Target RejectNegative Mask(NO_USE_FPU) Report Undocumented Target RejectNegative Mask(NO_USE_FPU) Undocumented
fpu fpu
Target RejectNegative InverseMask(NO_USE_FPU) Report Target RejectNegative InverseMask(NO_USE_FPU)
Enable the use of RX FPU instructions. This is the default. Enable the use of RX FPU instructions. This is the default.
;--------------------------------------------------- ;---------------------------------------------------
mcpu= mcpu=
Target RejectNegative Joined Var(rx_cpu_type) Report ToLower Enum(rx_cpu_types) Init(RX600) Target RejectNegative Joined Var(rx_cpu_type) ToLower Enum(rx_cpu_types) Init(RX600)
Specify the target RX cpu type. Specify the target RX cpu type.
Enum Enum
@ -67,11 +67,11 @@ Enum(rx_cpu_types) String(rx100) Value(RX100)
;--------------------------------------------------- ;---------------------------------------------------
mbig-endian-data mbig-endian-data
Target RejectNegative Mask(BIG_ENDIAN_DATA) Report Target RejectNegative Mask(BIG_ENDIAN_DATA)
Data is stored in big-endian format. Data is stored in big-endian format.
mlittle-endian-data mlittle-endian-data
Target RejectNegative InverseMask(BIG_ENDIAN_DATA) Report Target RejectNegative InverseMask(BIG_ENDIAN_DATA)
Data is stored in little-endian format. (Default). Data is stored in little-endian format. (Default).
;--------------------------------------------------- ;---------------------------------------------------
@ -113,33 +113,33 @@ Enables Position-Independent-Data (PID) mode.
;--------------------------------------------------- ;---------------------------------------------------
mwarn-multiple-fast-interrupts mwarn-multiple-fast-interrupts
Target Report Var(rx_warn_multiple_fast_interrupts) Init(1) Warning Target Var(rx_warn_multiple_fast_interrupts) Init(1) Warning
Warn when multiple, different, fast interrupt handlers are in the compilation unit. Warn when multiple, different, fast interrupt handlers are in the compilation unit.
;--------------------------------------------------- ;---------------------------------------------------
mgcc-abi mgcc-abi
Target RejectNegative Report Mask(GCC_ABI) Target RejectNegative Mask(GCC_ABI)
Enable the use of the old, broken, ABI where all stacked function arguments are aligned to 32-bits. Enable the use of the old, broken, ABI where all stacked function arguments are aligned to 32-bits.
mrx-abi mrx-abi
Target RejectNegative Report InverseMask(GCC_ABI) Target RejectNegative InverseMask(GCC_ABI)
Enable the use the standard RX ABI where all stacked function arguments are naturally aligned. This is the default. Enable the use the standard RX ABI where all stacked function arguments are naturally aligned. This is the default.
;--------------------------------------------------- ;---------------------------------------------------
mlra mlra
Target Report Mask(ENABLE_LRA) Target Mask(ENABLE_LRA)
Enable the use of the LRA register allocator. Enable the use of the LRA register allocator.
;--------------------------------------------------- ;---------------------------------------------------
mallow-string-insns mallow-string-insns
Target Report Var(rx_allow_string_insns) Init(1) Target Var(rx_allow_string_insns) Init(1)
Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default. Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default.
;--------------------------------------------------- ;---------------------------------------------------
mjsr mjsr
Target Report Mask(JSR) Target Mask(JSR)
Always use JSR, never BSR, for calls. Always use JSR, never BSR, for calls.

64
gcc/config/s390/s390.opt
View File

@ -44,11 +44,11 @@ Variable
long s390_cost_pointer long s390_cost_pointer
m31 m31
Target Report RejectNegative Negative(m64) InverseMask(64BIT) Target RejectNegative Negative(m64) InverseMask(64BIT)
31 bit ABI. 31 bit ABI.
m64 m64
Target Report RejectNegative Negative(m31) Mask(64BIT) Target RejectNegative Negative(m31) Mask(64BIT)
64 bit ABI. 64 bit ABI.
march= march=
@ -119,27 +119,27 @@ EnumValue
Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
mbackchain mbackchain
Target Report Mask(BACKCHAIN) Save Target Mask(BACKCHAIN) Save
Maintain backchain pointer. Maintain backchain pointer.
mdebug mdebug
Target Report Mask(DEBUG_ARG) Save Target Mask(DEBUG_ARG) Save
Additional debug prints. Additional debug prints.
mesa mesa
Target Report RejectNegative Negative(mzarch) InverseMask(ZARCH) Target RejectNegative Negative(mzarch) InverseMask(ZARCH)
ESA/390 architecture. ESA/390 architecture.
mhard-dfp mhard-dfp
Target Report Mask(HARD_DFP) Save Target Mask(HARD_DFP) Save
Enable decimal floating point hardware support. Enable decimal floating point hardware support.
mhard-float mhard-float
Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) Save Target RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) Save
Enable hardware floating point. Enable hardware floating point.
mhotpatch= mhotpatch=
Target RejectNegative Report Joined Var(s390_deferred_options) Defer Target RejectNegative Joined Var(s390_deferred_options) Defer
Takes two non-negative integer numbers separated by a comma. Takes two non-negative integer numbers separated by a comma.
Prepend the function label with the number of two-byte Nop Prepend the function label with the number of two-byte Nop
instructions indicated by the first. Append Nop instructions instructions indicated by the first. Append Nop instructions
@ -149,31 +149,31 @@ label. Nop instructions of the largest possible size are used
size. Using 0 for both values disables hotpatching. size. Using 0 for both values disables hotpatching.
mlong-double-128 mlong-double-128
Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128) Target RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128)
Use 128-bit long double. Use 128-bit long double.
mlong-double-64 mlong-double-64
Target Report RejectNegative Negative(mlong-double-128) InverseMask(LONG_DOUBLE_128) Target RejectNegative Negative(mlong-double-128) InverseMask(LONG_DOUBLE_128)
Use 64-bit long double. Use 64-bit long double.
mhtm mhtm
Target Report Mask(OPT_HTM) Save Target Mask(OPT_HTM) Save
Use hardware transactional execution instructions. Use hardware transactional execution instructions.
mvx mvx
Target Report Mask(OPT_VX) Save Target Mask(OPT_VX) Save
Use hardware vector facility instructions and enable the vector ABI. Use hardware vector facility instructions and enable the vector ABI.
mpacked-stack mpacked-stack
Target Report Mask(PACKED_STACK) Save Target Mask(PACKED_STACK) Save
Use packed stack layout. Use packed stack layout.
msmall-exec msmall-exec
Target Report Mask(SMALL_EXEC) Save Target Mask(SMALL_EXEC) Save
Use bras for executable < 64k. Use bras for executable < 64k.
msoft-float msoft-float
Target Report RejectNegative Negative(mhard-float) Mask(SOFT_FLOAT) Save Target RejectNegative Negative(mhard-float) Mask(SOFT_FLOAT) Save
Disable hardware floating point. Disable hardware floating point.
mstack-guard= mstack-guard=
@ -197,11 +197,11 @@ Target RejectNegative Joined Enum(processor_type) Var(s390_tune) Init(PROCESSOR_
Schedule code for given CPU. Schedule code for given CPU.
mmvcle mmvcle
Target Report Mask(MVCLE) Save Target Mask(MVCLE) Save
Use the mvcle instruction for block moves. Use the mvcle instruction for block moves.
mzvector mzvector
Target Report Mask(ZVECTOR) Save Target Mask(ZVECTOR) Save
Enable the z vector language extension providing the context-sensitive Enable the z vector language extension providing the context-sensitive
vector macro and enable the Altivec-style builtins in vecintrin.h. vector macro and enable the Altivec-style builtins in vecintrin.h.
@ -214,31 +214,31 @@ Target RejectNegative Joined UInteger Var(s390_warn_framesize) Save
Warn if a single function's framesize exceeds the given framesize. Warn if a single function's framesize exceeds the given framesize.
mzarch mzarch
Target Report RejectNegative Negative(mesa) Mask(ZARCH) Target RejectNegative Negative(mesa) Mask(ZARCH)
z/Architecture. z/Architecture.
mbranch-cost= mbranch-cost=
Target Report Joined RejectNegative UInteger Var(s390_branch_cost) Init(1) Save Target Joined RejectNegative UInteger Var(s390_branch_cost) Init(1) Save
Set the branch costs for conditional branch instructions. Reasonable Set the branch costs for conditional branch instructions. Reasonable
values are small, non-negative integers. The default branch cost is values are small, non-negative integers. The default branch cost is
1. 1.
mlra mlra
Target Report Var(s390_lra_flag) Init(1) Save Target Var(s390_lra_flag) Init(1) Save
Use LRA instead of reload. Use LRA instead of reload.
mpic-data-is-text-relative mpic-data-is-text-relative
Target Report Var(s390_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) Target Var(s390_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE)
Assume data segments are relative to text segment. Assume data segments are relative to text segment.
mindirect-branch= mindirect-branch=
Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch) Init(indirect_branch_keep)
Wrap all indirect branches into execute in order to disable branch Wrap all indirect branches into execute in order to disable branch
prediction. prediction.
mindirect-branch-jump= mindirect-branch-jump=
Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_jump) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_jump) Init(indirect_branch_keep)
Wrap indirect table jumps and computed gotos into execute in order to Wrap indirect table jumps and computed gotos into execute in order to
disable branch prediction. Using thunk or thunk-extern with this disable branch prediction. Using thunk or thunk-extern with this
option requires the thunks to be considered signal handlers to order to option requires the thunks to be considered signal handlers to order to
@ -246,22 +246,22 @@ generate correct CFI. For environments where unwinding (e.g. for
exceptions) is required please use thunk-inline instead. exceptions) is required please use thunk-inline instead.
mindirect-branch-call= mindirect-branch-call=
Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_call) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_call) Init(indirect_branch_keep)
Wrap all indirect calls into execute in order to disable branch prediction. Wrap all indirect calls into execute in order to disable branch prediction.
mfunction-return= mfunction-return=
Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return) Init(indirect_branch_keep)
Wrap all indirect return branches into execute in order to disable branch Wrap all indirect return branches into execute in order to disable branch
prediction. prediction.
mfunction-return-mem= mfunction-return-mem=
Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_mem) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_mem) Init(indirect_branch_keep)
Wrap indirect return branches into execute in order to disable branch Wrap indirect return branches into execute in order to disable branch
prediction. This affects only branches where the return address is prediction. This affects only branches where the return address is
going to be restored from memory. going to be restored from memory.
mfunction-return-reg= mfunction-return-reg=
Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_reg) Init(indirect_branch_keep) Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_reg) Init(indirect_branch_keep)
Wrap indirect return branches into execute in order to disable branch Wrap indirect return branches into execute in order to disable branch
prediction. This affects only branches where the return address prediction. This affects only branches where the return address
doesn't need to be restored from memory. doesn't need to be restored from memory.
@ -283,7 +283,7 @@ EnumValue
Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
mindirect-branch-table mindirect-branch-table
Target Report Var(s390_indirect_branch_table) Init(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE) Target Var(s390_indirect_branch_table) Init(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE)
Generate sections .s390_indirect_jump, .s390_indirect_call, Generate sections .s390_indirect_jump, .s390_indirect_call,
.s390_return_reg, and .s390_return_mem to contain the indirect branch .s390_return_reg, and .s390_return_mem to contain the indirect branch
locations which have been patched as part of using one of the locations which have been patched as part of using one of the
@ -292,21 +292,21 @@ consist of an array of 32 bit elements. Each entry holds the offset
from the entry to the patched location. from the entry to the patched location.
mfentry mfentry
Target Report Var(flag_fentry) Target Var(flag_fentry)
Emit profiling counter call at function entry before prologue. The compiled Emit profiling counter call at function entry before prologue. The compiled
code will require a 64-bit CPU and glibc 2.29 or newer to run. code will require a 64-bit CPU and glibc 2.29 or newer to run.
mrecord-mcount mrecord-mcount
Target Report Var(flag_record_mcount) Target Var(flag_record_mcount)
Generate __mcount_loc section with all _mcount and __fentry__ calls. Generate __mcount_loc section with all _mcount and __fentry__ calls.
mnop-mcount mnop-mcount
Target Report Var(flag_nop_mcount) Target Var(flag_nop_mcount)
Generate mcount/__fentry__ calls as nops. To activate they need to be Generate mcount/__fentry__ calls as nops. To activate they need to be
patched in. patched in.
mvx-long-double-fma mvx-long-double-fma
Target Report Undocumented Var(flag_vx_long_double_fma) Target Undocumented Var(flag_vx_long_double_fma)
Emit fused multiply-add instructions for long doubles in vector registers Emit fused multiply-add instructions for long doubles in vector registers
(wfmaxb, wfmsxb, wfnmaxb, wfnmsxb). Reassociation pass does not handle (wfmaxb, wfmsxb, wfnmaxb, wfnmsxb). Reassociation pass does not handle
fused multiply-adds, therefore code generated by the middle-end is prone to fused multiply-adds, therefore code generated by the middle-end is prone to

14
gcc/config/s390/tpf.opt
View File

@ -19,29 +19,29 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mtpf-trace mtpf-trace
Target Report Mask(TPF_PROFILING) Target Mask(TPF_PROFILING)
Enable TPF-OS tracing code. Enable TPF-OS tracing code.
mtpf-trace-hook-prologue-check= mtpf-trace-hook-prologue-check=
Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_prologue_check) Init(TPF_TRACE_PROLOGUE_CHECK) Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_prologue_check) Init(TPF_TRACE_PROLOGUE_CHECK)
Set the trace check address for prologue tpf hook Set the trace check address for prologue tpf hook
mtpf-trace-hook-prologue-target= mtpf-trace-hook-prologue-target=
Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_prologue_target) Init(TPF_TRACE_PROLOGUE_TARGET) Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_prologue_target) Init(TPF_TRACE_PROLOGUE_TARGET)
Set the trace jump address for prologue tpf hook Set the trace jump address for prologue tpf hook
mtpf-trace-hook-epilogue-check= mtpf-trace-hook-epilogue-check=
Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_epilogue_check) Init(TPF_TRACE_EPILOGUE_CHECK) Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_epilogue_check) Init(TPF_TRACE_EPILOGUE_CHECK)
Set the trace check address for epilogue tpf hook Set the trace check address for epilogue tpf hook
mtpf-trace-hook-epilogue-target= mtpf-trace-hook-epilogue-target=
Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_epilogue_target) Init(TPF_TRACE_EPILOGUE_TARGET) Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_epilogue_target) Init(TPF_TRACE_EPILOGUE_TARGET)
Set the trace jump address for epilogue tpf hook Set the trace jump address for epilogue tpf hook
mtpf-trace-skip mtpf-trace-skip
Target Report Var(s390_tpf_trace_skip) Init(0) Target Var(s390_tpf_trace_skip) Init(0)
Set the prologue and epilogue hook addresses to TPF_TRACE_PROLOGUE_SKIP_TARGET and TPF_TRACE_EPILOGUE_SKIP_TARGET. Equivalent to using -mtpf-trace-hook-prologue-target=TPF_TRACE_PROLOGUE_SKIP_TARGET and -mtpf-trace-hook-epilogue-target=TPF_TRACE_EPILOGUE_SKIP_TARGET Set the prologue and epilogue hook addresses to TPF_TRACE_PROLOGUE_SKIP_TARGET and TPF_TRACE_EPILOGUE_SKIP_TARGET. Equivalent to using -mtpf-trace-hook-prologue-target=TPF_TRACE_PROLOGUE_SKIP_TARGET and -mtpf-trace-hook-epilogue-target=TPF_TRACE_EPILOGUE_SKIP_TARGET
mmain mmain
Target Report Target
Specify main object for TPF-OS. Specify main object for TPF-OS.

38
gcc/config/sh/sh.opt
View File

@ -175,19 +175,19 @@ Target RejectNegative Condition(SUPPORT_SH4AL)
Generate SH4al-dsp code. Generate SH4al-dsp code.
maccumulate-outgoing-args maccumulate-outgoing-args
Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1) Target Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1)
Reserve space for outgoing arguments in the function prologue. Reserve space for outgoing arguments in the function prologue.
mb mb
Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Target RejectNegative InverseMask(LITTLE_ENDIAN)
Generate code in big endian mode. Generate code in big endian mode.
mbigtable mbigtable
Target Report RejectNegative Mask(BIGTABLE) Target RejectNegative Mask(BIGTABLE)
Generate 32-bit offsets in switch tables. Generate 32-bit offsets in switch tables.
mbitops mbitops
Target Report RejectNegative Mask(BITOPS) Target RejectNegative Mask(BITOPS)
Generate bit instructions. Generate bit instructions.
mbranch-cost= mbranch-cost=
@ -195,15 +195,15 @@ Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
Cost to assume for a branch insn. Cost to assume for a branch insn.
mzdcbranch mzdcbranch
Target Report Var(TARGET_ZDCBRANCH) Target Var(TARGET_ZDCBRANCH)
Assume that zero displacement conditional branches are fast. Assume that zero displacement conditional branches are fast.
mcbranch-force-delay-slot mcbranch-force-delay-slot
Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0) Target RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0)
Force the usage of delay slots for conditional branches. Force the usage of delay slots for conditional branches.
mdalign mdalign
Target Report RejectNegative Mask(ALIGN_DOUBLE) Target RejectNegative Mask(ALIGN_DOUBLE)
Align doubles at 64-bit boundaries. Align doubles at 64-bit boundaries.
mdiv= mdiv=
@ -215,7 +215,7 @@ Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
Specify name for 32 bit signed division function. Specify name for 32 bit signed division function.
mfdpic mfdpic
Target Report Var(TARGET_FDPIC) Init(0) Target Var(TARGET_FDPIC) Init(0)
Generate ELF FDPIC code. Generate ELF FDPIC code.
mfmovd mfmovd
@ -227,7 +227,7 @@ Target RejectNegative Joined Var(sh_fixed_range_str)
Specify range of registers to make fixed. Specify range of registers to make fixed.
mhitachi mhitachi
Target Report RejectNegative Mask(HITACHI) Target RejectNegative Mask(HITACHI)
Follow Renesas (formerly Hitachi) / SuperH calling conventions. Follow Renesas (formerly Hitachi) / SuperH calling conventions.
mieee mieee
@ -235,33 +235,33 @@ Target Var(TARGET_IEEE)
Increase the IEEE compliance for floating-point comparisons. Increase the IEEE compliance for floating-point comparisons.
minline-ic_invalidate minline-ic_invalidate
Target Report Var(TARGET_INLINE_IC_INVALIDATE) Target Var(TARGET_INLINE_IC_INVALIDATE)
Inline code to invalidate instruction cache entries after setting up nested function trampolines. Inline code to invalidate instruction cache entries after setting up nested function trampolines.
misize misize
Target Report RejectNegative Mask(DUMPISIZE) Target RejectNegative Mask(DUMPISIZE)
Annotate assembler instructions with estimated addresses. Annotate assembler instructions with estimated addresses.
ml ml
Target Report RejectNegative Mask(LITTLE_ENDIAN) Target RejectNegative Mask(LITTLE_ENDIAN)
Generate code in little endian mode. Generate code in little endian mode.
mnomacsave mnomacsave
Target Report RejectNegative Mask(NOMACSAVE) Target RejectNegative Mask(NOMACSAVE)
Mark MAC register as call-clobbered. Mark MAC register as call-clobbered.
;; ??? This option is not useful, but is retained in case there are people ;; ??? This option is not useful, but is retained in case there are people
;; who are still relying on it. It may be deleted in the future. ;; who are still relying on it. It may be deleted in the future.
mpadstruct mpadstruct
Target Report RejectNegative Mask(PADSTRUCT) Target RejectNegative Mask(PADSTRUCT)
Make structs a multiple of 4 bytes (warning: ABI altered). Make structs a multiple of 4 bytes (warning: ABI altered).
mprefergot mprefergot
Target Report RejectNegative Mask(PREFERGOT) Target RejectNegative Mask(PREFERGOT)
Emit function-calls using global offset table when generating PIC. Emit function-calls using global offset table when generating PIC.
mrelax mrelax
Target Report RejectNegative Mask(RELAX) Target RejectNegative Mask(RELAX)
Shorten address references during linking. Shorten address references during linking.
mrenesas mrenesas
@ -269,11 +269,11 @@ Target Mask(HITACHI)
Follow Renesas (formerly Hitachi) / SuperH calling conventions. Follow Renesas (formerly Hitachi) / SuperH calling conventions.
matomic-model= matomic-model=
Target Report RejectNegative Joined Var(sh_atomic_model_str) Target RejectNegative Joined Var(sh_atomic_model_str)
Specify the model for atomic operations. Specify the model for atomic operations.
mtas mtas
Target Report RejectNegative Var(TARGET_ENABLE_TAS) Target RejectNegative Var(TARGET_ENABLE_TAS)
Use tas.b instruction for __atomic_test_and_set. Use tas.b instruction for __atomic_test_and_set.
multcost= multcost=
@ -299,5 +299,5 @@ Target Var(TARGET_FSRRA)
Enable the use of the fsrra instruction. Enable the use of the fsrra instruction.
mlra mlra
Target Report Var(sh_lra_flag) Init(0) Save Target Var(sh_lra_flag) Init(0) Save
Use LRA instead of reload (transitional). Use LRA instead of reload (transitional).

4
gcc/config/sol2.opt
View File

@ -28,11 +28,11 @@ Ym,
Driver Joined Driver Joined
mclear-hwcap mclear-hwcap
Target Report Target
Clear hardware capabilities when linking. Clear hardware capabilities when linking.
mimpure-text mimpure-text
Target Report Target
Pass -z text to linker. Pass -z text to linker.
pthread pthread

4
gcc/config/sparc/long-double-switch.opt
View File

@ -19,9 +19,9 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mlong-double-128 mlong-double-128
Target Report RejectNegative Mask(LONG_DOUBLE_128) Target RejectNegative Mask(LONG_DOUBLE_128)
Use 128-bit long double. Use 128-bit long double.
mlong-double-64 mlong-double-64
Target Report RejectNegative InverseMask(LONG_DOUBLE_128) Target RejectNegative InverseMask(LONG_DOUBLE_128)
Use 64-bit long double. Use 64-bit long double.

60
gcc/config/sparc/sparc.opt
View File

@ -26,7 +26,7 @@ TargetVariable
unsigned int sparc_debug unsigned int sparc_debug
mfpu mfpu
Target Report Mask(FPU) Target Mask(FPU)
Use hardware FP. Use hardware FP.
mhard-float mhard-float
@ -38,95 +38,95 @@ Target RejectNegative InverseMask(FPU)
Do not use hardware FP. Do not use hardware FP.
mflat mflat
Target Report Mask(FLAT) Target Mask(FLAT)
Use flat register window model. Use flat register window model.
munaligned-doubles munaligned-doubles
Target Report Mask(UNALIGNED_DOUBLES) Target Mask(UNALIGNED_DOUBLES)
Assume possible double misalignment. Assume possible double misalignment.
mapp-regs mapp-regs
Target Report Mask(APP_REGS) Target Mask(APP_REGS)
Use ABI reserved registers. Use ABI reserved registers.
mhard-quad-float mhard-quad-float
Target Report RejectNegative Mask(HARD_QUAD) Target RejectNegative Mask(HARD_QUAD)
Use hardware quad FP instructions. Use hardware quad FP instructions.
msoft-quad-float msoft-quad-float
Target Report RejectNegative InverseMask(HARD_QUAD) Target RejectNegative InverseMask(HARD_QUAD)
Do not use hardware quad fp instructions. Do not use hardware quad fp instructions.
mlra mlra
Target Report Mask(LRA) Target Mask(LRA)
Enable Local Register Allocation. Enable Local Register Allocation.
mv8plus mv8plus
Target Report Mask(V8PLUS) Target Mask(V8PLUS)
Compile for V8+ ABI. Compile for V8+ ABI.
mvis mvis
Target Report Mask(VIS) Target Mask(VIS)
Use UltraSPARC Visual Instruction Set version 1.0 extensions. Use UltraSPARC Visual Instruction Set version 1.0 extensions.
mvis2 mvis2
Target Report Mask(VIS2) Target Mask(VIS2)
Use UltraSPARC Visual Instruction Set version 2.0 extensions. Use UltraSPARC Visual Instruction Set version 2.0 extensions.
mvis3 mvis3
Target Report Mask(VIS3) Target Mask(VIS3)
Use UltraSPARC Visual Instruction Set version 3.0 extensions. Use UltraSPARC Visual Instruction Set version 3.0 extensions.
mvis4 mvis4
Target Report Mask(VIS4) Target Mask(VIS4)
Use UltraSPARC Visual Instruction Set version 4.0 extensions. Use UltraSPARC Visual Instruction Set version 4.0 extensions.
mvis4b mvis4b
Target Report Mask(VIS4B) Target Mask(VIS4B)
Use additional VIS instructions introduced in OSA2017. Use additional VIS instructions introduced in OSA2017.
mcbcond mcbcond
Target Report Mask(CBCOND) Target Mask(CBCOND)
Use UltraSPARC Compare-and-Branch extensions. Use UltraSPARC Compare-and-Branch extensions.
mfmaf mfmaf
Target Report Mask(FMAF) Target Mask(FMAF)
Use UltraSPARC Fused Multiply-Add extensions. Use UltraSPARC Fused Multiply-Add extensions.
mfsmuld mfsmuld
Target Report Mask(FSMULD) Target Mask(FSMULD)
Use Floating-point Multiply Single to Double (FsMULd) instruction. Use Floating-point Multiply Single to Double (FsMULd) instruction.
mpopc mpopc
Target Report Mask(POPC) Target Mask(POPC)
Use UltraSPARC Population-Count instruction. Use UltraSPARC Population-Count instruction.
msubxc msubxc
Target Report Mask(SUBXC) Target Mask(SUBXC)
Use UltraSPARC Subtract-Extended-with-Carry instruction. Use UltraSPARC Subtract-Extended-with-Carry instruction.
mptr64 mptr64
Target Report RejectNegative Mask(PTR64) Target RejectNegative Mask(PTR64)
Pointers are 64-bit. Pointers are 64-bit.
mptr32 mptr32
Target Report RejectNegative InverseMask(PTR64) Target RejectNegative InverseMask(PTR64)
Pointers are 32-bit. Pointers are 32-bit.
m64 m64
Target Report RejectNegative Mask(64BIT) Target RejectNegative Mask(64BIT)
Use 64-bit ABI. Use 64-bit ABI.
m32 m32
Target Report RejectNegative InverseMask(64BIT) Target RejectNegative InverseMask(64BIT)
Use 32-bit ABI. Use 32-bit ABI.
mstack-bias mstack-bias
Target Report Mask(STACK_BIAS) Target Mask(STACK_BIAS)
Use stack bias. Use stack bias.
mfaster-structs mfaster-structs
Target Report Mask(FASTER_STRUCTS) Target Mask(FASTER_STRUCTS)
Use structs on stronger alignment for double-word copies. Use structs on stronger alignment for double-word copies.
mrelax mrelax
@ -134,7 +134,7 @@ Target
Optimize tail call instructions in assembler and linker. Optimize tail call instructions in assembler and linker.
muser-mode muser-mode
Target Report InverseMask(SV_MODE) Target InverseMask(SV_MODE)
Do not generate code that can only run in supervisor mode (default). Do not generate code that can only run in supervisor mode (default).
mcpu= mcpu=
@ -247,24 +247,24 @@ Target RejectNegative Joined Undocumented Var(sparc_debug_string)
Enable debug output. Enable debug output.
mstd-struct-return mstd-struct-return
Target Report Var(sparc_std_struct_return) Target Var(sparc_std_struct_return)
Enable strict 32-bit psABI struct return checking. Enable strict 32-bit psABI struct return checking.
mfix-at697f mfix-at697f
Target Report RejectNegative Var(sparc_fix_at697f) Target RejectNegative Var(sparc_fix_at697f)
Enable workaround for single erratum of AT697F processor Enable workaround for single erratum of AT697F processor
(corresponding to erratum #13 of AT697E processor). (corresponding to erratum #13 of AT697E processor).
mfix-ut699 mfix-ut699
Target Report RejectNegative Var(sparc_fix_ut699) Target RejectNegative Var(sparc_fix_ut699)
Enable workarounds for the errata of the UT699 processor. Enable workarounds for the errata of the UT699 processor.
mfix-ut700 mfix-ut700
Target Report RejectNegative Var(sparc_fix_ut700) Target RejectNegative Var(sparc_fix_ut700)
Enable workarounds for the errata of the UT699E/UT700 processor. Enable workarounds for the errata of the UT699E/UT700 processor.
mfix-gr712rc mfix-gr712rc
Target Report RejectNegative Var(sparc_fix_gr712rc) Target RejectNegative Var(sparc_fix_gr712rc)
Enable workarounds for the errata of the GR712RC processor. Enable workarounds for the errata of the GR712RC processor.
;; Enable workaround for back-to-back store errata ;; Enable workaround for back-to-back store errata

8
gcc/config/tilegx/tilegx.opt
View File

@ -33,19 +33,19 @@ EnumValue
Enum(tilegx_cpu) String(tilegx) Value(0) Enum(tilegx_cpu) String(tilegx) Value(0)
m32 m32
Target Report RejectNegative Negative(m64) Mask(32BIT) Target RejectNegative Negative(m64) Mask(32BIT)
Compile with 32 bit longs and pointers. Compile with 32 bit longs and pointers.
m64 m64
Target Report RejectNegative Negative(m32) InverseMask(32BIT, 64BIT) Target RejectNegative Negative(m32) InverseMask(32BIT, 64BIT)
Compile with 64 bit longs and pointers. Compile with 64 bit longs and pointers.
mbig-endian mbig-endian
Target Report RejectNegative Mask(BIG_ENDIAN) Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order. Use big-endian byte order.
mlittle-endian mlittle-endian
Target Report RejectNegative InverseMask(BIG_ENDIAN) Target RejectNegative InverseMask(BIG_ENDIAN)
Use little-endian byte order. Use little-endian byte order.
mcmodel= mcmodel=

2
gcc/config/tilepro/tilepro.opt
View File

@ -19,7 +19,7 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
m32 m32
Target Report RejectNegative Target RejectNegative
Compile with 32 bit longs and pointers, which is the only supported Compile with 32 bit longs and pointers, which is the only supported
behavior and thus the flag is ignored. behavior and thus the flag is ignored.

48
gcc/config/v850/v850.opt
View File

@ -25,34 +25,34 @@ Variable
int small_memory_max[(int)SMALL_MEMORY_max] = { 0, 0, 0 } int small_memory_max[(int)SMALL_MEMORY_max] = { 0, 0, 0 }
mapp-regs mapp-regs
Target Report Mask(APP_REGS) Target Mask(APP_REGS)
Use registers r2 and r5. Use registers r2 and r5.
mbig-switch mbig-switch
Target Report Mask(BIG_SWITCH) Target Mask(BIG_SWITCH)
Use 4 byte entries in switch tables. Use 4 byte entries in switch tables.
mdebug mdebug
Target Report Mask(DEBUG) Target Mask(DEBUG)
Enable backend debugging. Enable backend debugging.
mdisable-callt mdisable-callt
Target Report Mask(DISABLE_CALLT) Target Mask(DISABLE_CALLT)
Do not use the callt instruction (default). Do not use the callt instruction (default).
mep mep
Target Report Mask(EP) Target Mask(EP)
Reuse r30 on a per function basis. Reuse r30 on a per function basis.
mghs mghs
Target RejectNegative InverseMask(GCC_ABI) MaskExists Target RejectNegative InverseMask(GCC_ABI) MaskExists
mlong-calls mlong-calls
Target Report Mask(LONG_CALLS) Target Mask(LONG_CALLS)
Prohibit PC relative function calls. Prohibit PC relative function calls.
mprolog-function mprolog-function
Target Report Mask(PROLOG_FUNCTION) Target Mask(PROLOG_FUNCTION)
Use stubs for function prologues. Use stubs for function prologues.
msda= msda=
@ -63,7 +63,7 @@ msda-
Target RejectNegative Joined Undocumented Alias(msda=) Target RejectNegative Joined Undocumented Alias(msda=)
msmall-sld msmall-sld
Target Report Mask(SMALL_SLD) Target Mask(SMALL_SLD)
Enable the use of the short load instructions. Enable the use of the short load instructions.
mspace mspace
@ -78,22 +78,22 @@ mtda-
Target RejectNegative Joined Undocumented Alias(mtda=) Target RejectNegative Joined Undocumented Alias(mtda=)
mno-strict-align mno-strict-align
Target Report Mask(NO_STRICT_ALIGN) Target Mask(NO_STRICT_ALIGN)
Do not enforce strict alignment. Do not enforce strict alignment.
mjump-tables-in-data-section mjump-tables-in-data-section
Target Report Mask(JUMP_TABLES_IN_DATA_SECTION) Target Mask(JUMP_TABLES_IN_DATA_SECTION)
Put jump tables for switch statements into the .data section rather than the .code section. Put jump tables for switch statements into the .data section rather than the .code section.
mUS-bit-set mUS-bit-set
Target Report Mask(US_BIT_SET) Target Mask(US_BIT_SET)
mv850 mv850
Target Report RejectNegative Mask(V850) Target RejectNegative Mask(V850)
Compile for the v850 processor. Compile for the v850 processor.
mv850e mv850e
Target Report RejectNegative Mask(V850E) Target RejectNegative Mask(V850E)
Compile for the v850e processor. Compile for the v850e processor.
mv850e1 mv850e1
@ -105,22 +105,22 @@ Target RejectNegative Mask(V850E1)
Compile for the v850es variant of the v850e1. Compile for the v850es variant of the v850e1.
mv850e2 mv850e2
Target Report RejectNegative Mask(V850E2) Target RejectNegative Mask(V850E2)
Compile for the v850e2 processor. Compile for the v850e2 processor.
mv850e2v3 mv850e2v3
Target Report RejectNegative Mask(V850E2V3) Target RejectNegative Mask(V850E2V3)
Compile for the v850e2v3 processor. Compile for the v850e2v3 processor.
mv850e3v5 mv850e3v5
Target Report RejectNegative Mask(V850E3V5) Target RejectNegative Mask(V850E3V5)
Compile for the v850e3v5 processor. Compile for the v850e3v5 processor.
mv850e2v4 mv850e2v4
Target RejectNegative Mask(V850E3V5) MaskExists Target RejectNegative Mask(V850E3V5) MaskExists
mloop mloop
Target Report Mask(LOOP) Target Mask(LOOP)
Enable v850e3v5 loop instructions. Enable v850e3v5 loop instructions.
mzda= mzda=
@ -131,29 +131,29 @@ mzda-
Target RejectNegative Joined Undocumented Alias(mzda=) Target RejectNegative Joined Undocumented Alias(mzda=)
mrelax mrelax
Target Report Mask(RELAX) Target Mask(RELAX)
Enable relaxing in the assembler. Enable relaxing in the assembler.
mlong-jumps mlong-jumps
Target Report Mask(BIG_SWITCH) MaskExists Target Mask(BIG_SWITCH) MaskExists
Prohibit PC relative jumps. Prohibit PC relative jumps.
msoft-float msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT) Target RejectNegative Mask(SOFT_FLOAT)
Inhibit the use of hardware floating point instructions. Inhibit the use of hardware floating point instructions.
mhard-float mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT) MaskExists Target RejectNegative InverseMask(SOFT_FLOAT) MaskExists
Allow the use of hardware floating point instructions for V850E2V3 and up. Allow the use of hardware floating point instructions for V850E2V3 and up.
mrh850-abi mrh850-abi
Target RejectNegative Report InverseMask(GCC_ABI) MaskExists Target RejectNegative InverseMask(GCC_ABI) MaskExists
Enable support for the RH850 ABI. This is the default. Enable support for the RH850 ABI. This is the default.
mgcc-abi mgcc-abi
Target RejectNegative Report Mask(GCC_ABI) Target RejectNegative Mask(GCC_ABI)
Enable support for the old GCC ABI. Enable support for the old GCC ABI.
m8byte-align m8byte-align
Target Report Mask(8BYTE_ALIGN) Target Mask(8BYTE_ALIGN)
Support alignments of up to 64-bits. Support alignments of up to 64-bits.

6
gcc/config/visium/visium.opt
View File

@ -29,7 +29,7 @@ Target RejectNegative
Link with libc.a and libsim.a. Link with libc.a and libsim.a.
mfpu mfpu
Target Report Mask(FPU) Target Mask(FPU)
Use hardware FP (default). Use hardware FP (default).
mhard-float mhard-float
@ -61,11 +61,11 @@ EnumValue
Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6) Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6)
msv-mode msv-mode
Target RejectNegative Report Mask(SV_MODE) Target RejectNegative Mask(SV_MODE)
Generate code for the supervisor mode (default). Generate code for the supervisor mode (default).
muser-mode muser-mode
Target RejectNegative Report InverseMask(SV_MODE) Target RejectNegative InverseMask(SV_MODE)
Generate code for the user mode. Generate code for the user mode.
menable-trampolines menable-trampolines

6
gcc/config/vms/vms.opt
View File

@ -23,7 +23,7 @@ map
Target RejectNegative Target RejectNegative
mmalloc64 mmalloc64
Target Report Var(flag_vms_malloc64) Init(1) Target Var(flag_vms_malloc64) Init(1)
Malloc data into P2 space. Malloc data into P2 space.
mdebug-main= mdebug-main=
@ -31,11 +31,11 @@ Target RejectNegative Joined Var(vms_debug_main)
Set name of main routine for the debugger. Set name of main routine for the debugger.
mvms-return-codes mvms-return-codes
Target Report Var(flag_vms_return_codes) Target Var(flag_vms_return_codes)
Use VMS exit codes instead of posix ones. Use VMS exit codes instead of posix ones.
mpointer-size= mpointer-size=
Target Joined Report RejectNegative Enum(vms_pointer_size) Var(flag_vms_pointer_size) Init(VMS_POINTER_SIZE_NONE) Target Joined RejectNegative Enum(vms_pointer_size) Var(flag_vms_pointer_size) Init(VMS_POINTER_SIZE_NONE)
-mpointer-size=[no,32,short,64,long] Set the default pointer size. -mpointer-size=[no,32,short,64,long] Set the default pointer size.
Enum Enum

2
gcc/config/vxworks.opt
View File

@ -32,7 +32,7 @@ Xbind-now
Driver Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) Driver Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL)
mrtp mrtp
Target Report RejectNegative Mask(VXWORKS_RTP) Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) Target RejectNegative Mask(VXWORKS_RTP) Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL)
Assume the VxWorks RTP environment. Assume the VxWorks RTP environment.
; VxWorks AE has two modes: kernel mode and vThreads mode. In ; VxWorks AE has two modes: kernel mode and vThreads mode. In

12
gcc/config/xtensa/xtensa.opt
View File

@ -19,11 +19,11 @@
; <http://www.gnu.org/licenses/>. ; <http://www.gnu.org/licenses/>.
mconst16 mconst16
Target Report Mask(CONST16) Target Mask(CONST16)
Use CONST16 instruction to load constants. Use CONST16 instruction to load constants.
mforce-no-pic mforce-no-pic
Target Report Mask(FORCE_NO_PIC) Target Mask(FORCE_NO_PIC)
Disable position-independent code (PIC) for use in OS kernel code. Disable position-independent code (PIC) for use in OS kernel code.
mlongcalls mlongcalls
@ -39,20 +39,20 @@ Target
Intersperse literal pools with code in the text section. Intersperse literal pools with code in the text section.
mauto-litpools mauto-litpools
Target Report Mask(AUTO_LITPOOLS) Target Mask(AUTO_LITPOOLS)
Relax literals in assembler and place them automatically in the text section. Relax literals in assembler and place them automatically in the text section.
mserialize-volatile mserialize-volatile
Target Report Mask(SERIALIZE_VOLATILE) Target Mask(SERIALIZE_VOLATILE)
-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions. -mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions.
TargetVariable TargetVariable
int xtensa_windowed_abi = -1 int xtensa_windowed_abi = -1
mabi=call0 mabi=call0
Target Report RejectNegative Var(xtensa_windowed_abi, 0) Target RejectNegative Var(xtensa_windowed_abi, 0)
Use call0 ABI. Use call0 ABI.
mabi=windowed mabi=windowed
Target Report RejectNegative Var(xtensa_windowed_abi, 1) Target RejectNegative Var(xtensa_windowed_abi, 1)
Use windowed registers ABI. Use windowed registers ABI.

6
gcc/lto/lang.opt
View File

@ -49,12 +49,12 @@ EnumValue
Enum(lto_linker_output) String(exec) Value(LTO_LINKER_OUTPUT_EXEC) Enum(lto_linker_output) String(exec) Value(LTO_LINKER_OUTPUT_EXEC)
flinker-output= flinker-output=
LTO Report Driver Joined RejectNegative Enum(lto_linker_output) Var(flag_lto_linker_output) Init(LTO_LINKER_OUTPUT_UNKNOWN) LTO Driver Joined RejectNegative Enum(lto_linker_output) Var(flag_lto_linker_output) Init(LTO_LINKER_OUTPUT_UNKNOWN)
Set linker output type (used internally during LTO optimization). Set linker output type (used internally during LTO optimization).
fltrans fltrans
LTO Report Var(flag_ltrans) LTO Var(flag_ltrans)
Run the link-time optimizer in local transformation (LTRANS) mode. Run the link-time optimizer in local transformation (LTRANS) mode.
fltrans-output-list= fltrans-output-list=
@ -62,7 +62,7 @@ LTO Joined Var(ltrans_output_list)
Specify a file to which a list of files output by LTRANS is written. Specify a file to which a list of files output by LTRANS is written.
fwpa fwpa
LTO Driver Report LTO Driver
Run the link-time optimizer in whole program analysis (WPA) mode. Run the link-time optimizer in whole program analysis (WPA) mode.
fwpa= fwpa=