RISC-V Port: Regenerate gcc/configure
From-SVN: r245225
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@ -31,6 +31,7 @@
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* doc/install.texi: Add RISC-V entries.
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* doc/invoke.texi: Add RISC-V options section.
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* doc/md.texi: Add RISC-V constraints section.
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* configure: Regenerated.
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2017-02-06 Michael Meissner <meissner@linux.vnet.ibm.com>
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15
gcc/configure
vendored
15
gcc/configure
vendored
@ -24156,6 +24156,17 @@ x3: .space 4
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tls_first_minor=14
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tls_as_opt="-a32 --fatal-warnings"
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;;
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riscv*-*-*)
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conftest_s='
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.section .tdata,"awT",@progbits
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x: .word 2
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.text
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la.tls.gd a0,x
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call __tls_get_addr'
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tls_first_major=2
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tls_first_minor=21
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tls_as_opt='--fatal-warnings'
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;;
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s390-*-*)
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conftest_s='
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.section ".tdata","awT",@progbits
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@ -27516,8 +27527,8 @@ esac
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# version to the per-target configury.
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case "$cpu_type" in
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aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
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| mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
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| visium | xstormy16 | xtensa)
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| mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
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| tilepro | visium | xstormy16 | xtensa)
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insn="nop"
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;;
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ia64 | s390)
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