[arm] Early expansion of usubvdi4.
This patch adds early expansion of usubvdi4, allowing us to handle some constants in place, which previously we were unable to do. * config/arm/arm.md (usubvdi4): Allow registers or integers for incoming operands. Early split the calculation into SImode operations. (usubvsi3_borrow): New insn pattern. (usubvsi3_borrow_imm): Likewise. From-SVN: r277188
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Richard Earnshaw
Richard Earnshaw
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a79048f625
commit
eff5ce0a95
@ -1,3 +1,11 @@
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm.md (usubvdi4): Allow registers or integers for
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incoming operands. Early split the calculation into SImode
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operations.
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(usubvsi3_borrow): New insn pattern.
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(usubvsi3_borrow_imm): Likewise.
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2019-10-18 Richard Earnshaw <rearnsha@arm.com>
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* config/arm/arm.md (usubv<mode>4): Delete expansion.
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@ -1390,13 +1390,81 @@
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(define_expand "usubvdi4"
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[(match_operand:DI 0 "s_register_operand")
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(match_operand:DI 1 "s_register_operand")
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(match_operand:DI 2 "s_register_operand")
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(match_operand:DI 1 "reg_or_int_operand")
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(match_operand:DI 2 "reg_or_int_operand")
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(match_operand 3 "")]
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"TARGET_32BIT"
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{
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emit_insn (gen_subdi3_compare1 (operands[0], operands[1], operands[2]));
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arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
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rtx lo_result, hi_result;
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rtx lo_op1, hi_op1, lo_op2, hi_op2;
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lo_result = gen_lowpart (SImode, operands[0]);
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hi_result = gen_highpart (SImode, operands[0]);
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machine_mode mode = CCmode;
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if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2]))
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{
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/* If both operands are constants we can decide the result statically. */
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wi::overflow_type overflow;
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wide_int val = wi::sub (rtx_mode_t (operands[1], DImode),
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rtx_mode_t (operands[2], DImode),
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UNSIGNED, &overflow);
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emit_move_insn (operands[0], GEN_INT (val.to_shwi ()));
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if (overflow != wi::OVF_NONE)
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emit_jump_insn (gen_jump (operands[3]));
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DONE;
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}
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else if (CONST_INT_P (operands[1]))
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{
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arm_decompose_di_binop (operands[2], operands[1], &lo_op2, &hi_op2,
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&lo_op1, &hi_op1);
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if (const_ok_for_arm (INTVAL (lo_op1)))
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{
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emit_insn (gen_rsb_imm_compare (lo_result, lo_op1, lo_op2,
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GEN_INT (~UINTVAL (lo_op1))));
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/* We could potentially use RSC here in Arm state, but not
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in Thumb, so it's probably not worth the effort of handling
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this. */
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hi_op1 = force_reg (SImode, hi_op1);
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mode = CC_RSBmode;
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goto highpart;
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}
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operands[1] = force_reg (DImode, operands[1]);
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}
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arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
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&lo_op2, &hi_op2);
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if (lo_op2 == const0_rtx)
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{
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emit_move_insn (lo_result, lo_op1);
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if (!arm_add_operand (hi_op2, SImode))
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hi_op2 = force_reg (SImode, hi_op2);
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emit_insn (gen_usubvsi4 (hi_result, hi_op1, hi_op2, operands[3]));
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DONE;
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}
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if (CONST_INT_P (lo_op2) && !arm_addimm_operand (lo_op2, SImode))
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lo_op2 = force_reg (SImode, lo_op2);
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if (CONST_INT_P (lo_op2))
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emit_insn (gen_cmpsi2_addneg (lo_result, lo_op1, lo_op2,
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GEN_INT (-INTVAL (lo_op2))));
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else
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emit_insn (gen_subsi3_compare1 (lo_result, lo_op1, lo_op2));
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highpart:
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if (!arm_not_operand (hi_op2, SImode))
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hi_op2 = force_reg (SImode, hi_op2);
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rtx ccreg = gen_rtx_REG (mode, CC_REGNUM);
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if (CONST_INT_P (hi_op2))
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emit_insn (gen_usubvsi3_borrow_imm (hi_result, hi_op1, hi_op2,
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GEN_INT (UINTVAL (hi_op2) & 0xffffffff),
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gen_rtx_LTU (SImode, ccreg, const0_rtx),
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gen_rtx_LTU (DImode, ccreg,
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const0_rtx)));
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else
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emit_insn (gen_usubvsi3_borrow (hi_result, hi_op1, hi_op2,
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gen_rtx_LTU (SImode, ccreg, const0_rtx),
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gen_rtx_LTU (DImode, ccreg, const0_rtx)));
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arm_gen_unlikely_cbranch (LTU, CC_Bmode, operands[3]);
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DONE;
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})
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@ -1825,6 +1893,43 @@
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(set_attr "type" "alus_imm")]
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)
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(define_insn "usubvsi3_borrow"
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[(set (reg:CC_B CC_REGNUM)
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(compare:CC_B
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(zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))
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(plus:DI (match_operand:DI 4 "arm_borrow_operation" "")
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(zero_extend:DI
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(match_operand:SI 2 "s_register_operand" "l,r")))))
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(set (match_operand:SI 0 "s_register_operand" "=l,r")
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(minus:SI (match_dup 1)
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(plus:SI (match_operand:SI 3 "arm_borrow_operation" "")
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(match_dup 2))))]
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"TARGET_32BIT"
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"sbcs%?\\t%0, %1, %2"
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[(set_attr "conds" "set")
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(set_attr "arch" "t2,*")
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(set_attr "length" "2,4")]
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)
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(define_insn "usubvsi3_borrow_imm"
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[(set (reg:CC_B CC_REGNUM)
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(compare:CC_B
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(zero_extend:DI (match_operand:SI 1 "s_register_operand" "r,r"))
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(plus:DI (match_operand:DI 5 "arm_borrow_operation" "")
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(match_operand:DI 3 "const_int_operand" "n,n"))))
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(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(minus:SI (match_dup 1)
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(plus:SI (match_operand:SI 4 "arm_borrow_operation" "")
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(match_operand:SI 2 "arm_adcimm_operand" "I,K"))))]
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"TARGET_32BIT
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&& (UINTVAL (operands[2]) & 0xffffffff) == UINTVAL (operands[3])"
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"@
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sbcs%?\\t%0, %1, %2
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adcs%?\\t%0, %1, #%B2"
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[(set_attr "conds" "set")
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(set_attr "type" "alus_imm")]
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)
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(define_expand "subsf3"
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[(set (match_operand:SF 0 "s_register_operand")
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(minus:SF (match_operand:SF 1 "s_register_operand")
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