OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

arm.c (is_load_address): Rename to...

Browse Source 
* config/arm/arm.c (is_load_address): Rename to... (arm_memory_load_p) ... this
and make it check for SUBREGs and constant loads that will be converted into
loads from the minipool.
(is_cirrus_insn): Rename to ... (arm_cirrus_insn_p): ... this, for consistency.
Replace test of CIRRUS_NO with CIRRUS_NOT.
(cirrus_reorg): Use renamed functions.
(note_invalid_constants): Change from a void function to bool.  Add an extra
parameter, saying whether the fixups should be pushed.  Return true if fixups
are needed.
(arm_reorg): Use renamed functions.  Use INSN_P.  Replace test of CIRRUS_NO
with CIRRUS_NOT.
* config/arm/arm.h (FLOAT_WORDS_BIG_ENDIAN): Mention that other floating point
co-processors can also affect this.
* config/arm/arm.md ("type" attribute): Add mav_farith and mav_dmult.  Replace
references to "cirrus_type" attribute with "type".
* config/arm/cirrus.md ("cirrus_fpu" attribute): Delete.
("cirrus_type" attribute): Delete - use "type" instead.
("cirrus" attribute): Replace 'no' with 'not' and 'yes' with 'normal'.

From-SVN: r63466
This commit is contained in:
Nick Clifton 2003-02-26 11:26:37 +00:00 committed by Nick Clifton
parent 0d446150c2
commit f0375c6680
5 changed files with 182 additions and 181 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
gcc/ChangeLog
View File

@ -1,3 +1,28 @@
2003-02-26 Nick Clifton <nickc@redhat.com>
* config/arm/arm.c (is_load_address): Rename to...
(arm_memory_load_p) ... this and make it check for SUBREGs and
constant loads that will be converted into loads from the
minipool.
(is_cirrus_insn): Rename to ...
(arm_cirrus_insn_p): ... this, for consistency. Replace test
of CIRRUS_NO with CIRRUS_NOT.
(cirrus_reorg): Use renamed functions.
(note_invalid_constants): Change from a void function to bool.
Add an extra parameter, saying whether the fixups should be
pushed. Return true if fixups are needed.
(arm_reorg): Use renamed functions. Use INSN_P. Replace test
of CIRRUS_NO with CIRRUS_NOT.
* config/arm/arm.h (FLOAT_WORDS_BIG_ENDIAN): Mention that
other floating point co-processors can also affect this.
* config/arm/arm.md ("type" attribute): Add mav_farith and
mav_dmult. Replace references to "cirrus_type" attribute with
"type".
* config/arm/cirrus.md ("cirrus_fpu" attribute): Delete.
("cirrus_type" attribute): Delete - use "type" instead.
("cirrus" attribute): Replace 'no' with 'not' and 'yes' with
'normal'.
Tue Feb 25 22:46:27 CET 2003 Jan Hubicka <jh@suse.cz>
* objc-act.c: Include cgraph.h

151
gcc/config/arm/arm.c
View File

@ -75,11 +75,8 @@ static void arm_add_gc_roots PARAMS ((void));
static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
static unsigned bit_count PARAMS ((Ulong));
static int arm_address_register_rtx_p PARAMS ((rtx, int));
static int arm_legitimate_index_p PARAMS ((enum machine_mode,
rtx, int));
static int thumb_base_register_rtx_p PARAMS ((rtx,
enum machine_mode,
int));
static int arm_legitimate_index_p PARAMS ((Mmode, rtx, int));
static int thumb_base_register_rtx_p PARAMS ((rtx, Mmode, int));
inline static int thumb_index_register_rtx_p PARAMS ((rtx, int));
static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
static int eliminate_lr2ip PARAMS ((rtx *));
@ -116,7 +113,7 @@ static int arm_barrier_cost PARAMS ((rtx));
static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
static void push_minipool_barrier PARAMS ((rtx, Hint));
static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
static void note_invalid_constants PARAMS ((rtx, Hint));
static bool note_invalid_constants PARAMS ((rtx, Hint, bool));
static int current_file_function_operand PARAMS ((rtx));
static Ulong arm_compute_save_reg0_reg12_mask PARAMS ((void));
static Ulong arm_compute_save_reg_mask PARAMS ((void));
@ -128,31 +125,28 @@ static void arm_output_function_epilogue PARAMS ((FILE *, Hint));
static void arm_output_function_prologue PARAMS ((FILE *, Hint));
static void thumb_output_function_prologue PARAMS ((FILE *, Hint));
static int arm_comp_type_attributes PARAMS ((tree, tree));
static void arm_set_default_type_attributes PARAMS ((tree));
static void arm_set_default_type_attributes PARAMS ((tree));
static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int));
static int count_insns_for_constant PARAMS ((HOST_WIDE_INT, int));
static int count_insns_for_constant PARAMS ((Hint, int));
static int arm_get_strip_length PARAMS ((int));
static bool arm_function_ok_for_sibcall PARAMS ((tree, tree));
static void arm_internal_label PARAMS ((FILE *, Ccstar, Ulong));
static void arm_output_mi_thunk PARAMS ((FILE *, tree, Hint, Hint, tree));
static int arm_rtx_costs_1 PARAMS ((rtx, enum rtx_code, enum rtx_code));
static bool arm_rtx_costs PARAMS ((rtx, int, int, int *));
static int arm_address_cost PARAMS ((rtx));
static bool arm_memory_load_p PARAMS ((rtx));
static bool arm_cirrus_insn_p PARAMS ((rtx));
static void cirrus_reorg PARAMS ((rtx));
#ifdef OBJECT_FORMAT_ELF
static void arm_elf_asm_named_section PARAMS ((const char *, unsigned int));
static void arm_elf_asm_named_section PARAMS ((Ccstar, unsigned int));
#endif
#ifndef ARM_PE
static void arm_encode_section_info PARAMS ((tree, int));
#endif
#ifdef AOF_ASSEMBLER
static void aof_globalize_label PARAMS ((FILE *, const char *));
static void aof_globalize_label PARAMS ((FILE *, Ccstar));
#endif
static void arm_internal_label PARAMS ((FILE *, const char *, unsigned long));
static void arm_output_mi_thunk PARAMS ((FILE *, tree,
HOST_WIDE_INT,
HOST_WIDE_INT, tree));
static int arm_rtx_costs_1 PARAMS ((rtx, enum rtx_code,
enum rtx_code));
static bool arm_rtx_costs PARAMS ((rtx, int, int, int*));
static int arm_address_cost PARAMS ((rtx));
static int is_load_address PARAMS ((rtx));
static int is_cirrus_insn PARAMS ((rtx));
static void cirrus_reorg PARAMS ((rtx));
#undef Hint
#undef Mmode
@ -3984,38 +3978,47 @@ cirrus_shift_const (op, mode)
&& INTVAL (op) < 64);
}
/* Return nonzero if INSN is an LDR R0,ADDR instruction. */
/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
Use by the Cirrus Maverick code which has to workaround
a hardware bug triggered by such instructions. */
static int
is_load_address (insn)
static bool
arm_memory_load_p (insn)
rtx insn;
{
rtx body, lhs, rhs;;
if (!insn)
return 0;
if (GET_CODE (insn) != INSN)
return 0;
if (insn == NULL_RTX || GET_CODE (insn) != INSN)
return false;
body = PATTERN (insn);
if (GET_CODE (body) != SET)
return 0;
return false;
lhs = XEXP (body, 0);
rhs = XEXP (body, 1);
return (GET_CODE (lhs) == REG
&& REGNO_REG_CLASS (REGNO (lhs)) == GENERAL_REGS
&& (GET_CODE (rhs) == MEM
|| GET_CODE (rhs) == SYMBOL_REF));
lhs = REG_OR_SUBREG_RTX (lhs);
/* If the destination is not a general purpose
register we do not have to worry. */
if (GET_CODE (lhs) != REG
|| REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
return false;
/* As well as loads from memory we also have to react
to loads of invalid constants which will be turned
into loads from the minipool. */
return (GET_CODE (rhs) == MEM
|| GET_CODE (rhs) == SYMBOL_REF
|| note_invalid_constants (insn, -1, false));
}
/* Return nonzero if INSN is a Cirrus instruction. */
/* Return TRUE if INSN is a Cirrus instruction. */
static int
is_cirrus_insn (insn)
static bool
arm_cirrus_insn_p (insn)
rtx insn;
{
enum attr_cirrus attr;
@ -4029,7 +4032,7 @@ is_cirrus_insn (insn)
attr = get_attr_cirrus (insn);
return attr != CIRRUS_NO;
return attr != CIRRUS_NOT;
}
/* Cirrus reorg for invalid instruction combinations. */
@ -4049,10 +4052,10 @@ cirrus_reorg (first)
nops = 0;
t = next_nonnote_insn (first);
if (is_cirrus_insn (t))
if (arm_cirrus_insn_p (t))
++ nops;
if (is_cirrus_insn (next_nonnote_insn (t)))
if (arm_cirrus_insn_p (next_nonnote_insn (t)))
++ nops;
while (nops --)
@ -4073,12 +4076,12 @@ cirrus_reorg (first)
be followed by a non Cirrus insn. */
if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
{
if (is_cirrus_insn (next_nonnote_insn (first)))
if (arm_cirrus_insn_p (next_nonnote_insn (first)))
emit_insn_after (gen_nop (), first);
return;
}
else if (is_load_address (first))
else if (arm_memory_load_p (first))
{
unsigned int arm_regno;
@ -4102,7 +4105,7 @@ cirrus_reorg (first)
/* Next insn. */
first = next_nonnote_insn (first);
if (!is_cirrus_insn (first))
if (! arm_cirrus_insn_p (first))
return;
body = PATTERN (first);
@ -4140,10 +4143,10 @@ cirrus_reorg (first)
t = next_nonnote_insn (first);
if (is_cirrus_insn (t))
if (arm_cirrus_insn_p (t))
++ nops;
if (is_cirrus_insn (next_nonnote_insn (t)))
if (arm_cirrus_insn_p (next_nonnote_insn (t)))
++ nops;
while (nops --)
@ -6910,13 +6913,19 @@ push_minipool_fix (insn, address, loc, mode, value)
minipool_fix_tail = fix;
}
/* Scan INSN and note any of its operands that need fixing. */
/* Scan INSN and note any of its operands that need fixing.
If DO_PUSHES is false we do not actually push any of the fixups
needed. The function returns TRUE is any fixups were needed/pushed.
This is used by arm_memory_load_p() which needs to know about loads
of constants that will be converted into minipool loads. */
static void
note_invalid_constants (insn, address)
static bool
note_invalid_constants (insn, address, do_pushes)
rtx insn;
HOST_WIDE_INT address;
bool do_pushes;
{
bool result = false;
int opno;
extract_insn (insn);
@ -6924,8 +6933,7 @@ note_invalid_constants (insn, address)
if (!constrain_operands (1))
fatal_insn_not_found (insn);
/* Fill in recog_op_alt with information about the constraints of this
insn. */
/* Fill in recog_op_alt with information about the constraints of this insn. */
preprocess_constraints ();
for (opno = 0; opno < recog_data.n_operands; opno++)
@ -6943,27 +6951,27 @@ note_invalid_constants (insn, address)
rtx op = recog_data.operand[opno];
if (CONSTANT_P (op))
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno], op);
#if 0
/* RWE: Now we look correctly at the operands for the insn,
this shouldn't be needed any more. */
#ifndef AOF_ASSEMBLER
/* XXX Is this still needed? */
else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno],
XVECEXP (op, 0, 0));
#endif
#endif
{
if (do_pushes)
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno], op);
result = true;
}
else if (GET_CODE (op) == MEM
&& GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno],
get_pool_constant (XEXP (op, 0)));
{
if (do_pushes)
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno],
get_pool_constant (XEXP (op, 0)));
result = true;
}
}
}
return result;
}
void
@ -6985,19 +6993,18 @@ arm_reorg (first)
for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
{
if (TARGET_CIRRUS_FIX_INVALID_INSNS
&& (is_cirrus_insn (insn)
&& (arm_cirrus_insn_p (insn)
|| GET_CODE (insn) == JUMP_INSN
|| is_load_address (insn)))
|| arm_memory_load_p (insn)))
cirrus_reorg (insn);
if (GET_CODE (insn) == BARRIER)
push_minipool_barrier (insn, address);
else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
|| GET_CODE (insn) == JUMP_INSN)
else if (INSN_P (insn))
{
rtx table;
note_invalid_constants (insn, address);
note_invalid_constants (insn, address, true);
address += get_attr_length (insn);
/* If the insn is a vector jump, add the size of the table
@ -10134,7 +10141,7 @@ arm_final_prescan_insn (insn)
instructions to be safe. */
if (GET_CODE (scanbody) != USE
&& GET_CODE (scanbody) != CLOBBER
&& get_attr_cirrus (this_insn) != CIRRUS_NO)
&& get_attr_cirrus (this_insn) != CIRRUS_NOT)
fail = TRUE;
break;

4
gcc/config/arm/arm.h
View File

@ -698,8 +698,8 @@ extern int arm_is_6_or_7;
#endif
/* Define this if most significant word of doubles is the lowest numbered.
The rules are different based on whether or not we use FPA-format or
VFP-format doubles. */
The rules are different based on whether or not we use FPA-format,
VFP-format or some other floating point co-processor's format doubles. */
#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
#define UNITS_PER_WORD 4

27
gcc/config/arm/arm.md
View File

@ -167,9 +167,12 @@
; store2 store 2 words
; store3 store 3 words
; store4 store 4 words
; Additions for Cirrus Maverick co-processor:
; mav_farith Floating point arithmetic (4 cycle)
; mav_dmult Double multiplies (7 cycle)
;
(define_attr "type"
"normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4"
"normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4,mav_farith,mav_dmult"
(const_string "normal"))
; Load scheduling, set from the arm_ld_sched variable
@ -5576,11 +5579,6 @@
(set_attr "type" "f_2_r")]
)
;; There is no CCFPE or CCFP modes in the code below so we can have
;; one pattern to match either one. Besides, we're pretty sure we
;; have either CCFPE or CCFP because we made the patterns
;; (arm_gen_compare_reg).
;; Cirrus SF compare instruction
(define_insn "*cirrus_cmpsf"
[(set (reg:CCFP CC_REGNUM)
@ -5588,7 +5586,7 @@
(match_operand:SF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcmps%?\\tr15, %V0, %V1"
[(set_attr "cirrus_type" "farith")
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "compare")]
)
@ -5599,7 +5597,7 @@
(match_operand:DF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcmpd%?\\tr15, %V0, %V1"
[(set_attr "cirrus_type" "farith")
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "compare")]
)
@ -5620,18 +5618,7 @@
(match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcmp64%?\\tr15, %V0, %V1"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "compare")]
)
;; Cirrus SI compare instruction
(define_insn "*cirrus_cmpsi_1"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "cirrus_fp_register" "v")
(match_operand:SI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfcmp32%?\\tr15, %V0, %V1"
[(set_attr "cirrus_type" "farith")
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "compare")]
)

156
gcc/config/arm/cirrus.md
View File

@ -21,32 +21,14 @@
;; Boston, MA 02111-1307, USA.
(define_attr "cirrus_fpu" "fpa,fpe2,fpe3,yes" (const (symbol_ref "arm_fpu_attr")))
; Classification of each insn
; farith Floating point arithmetic (4 cycle)
; dmult Double multiplies (7 cycle)
(define_attr "cirrus_type" "normal,farith,dmult" (const_string "normal"))
; Cirrus types for invalid insn combinations
; no Not a cirrus insn
; yes Cirrus insn
; not Not a cirrus insn
; normal Any Cirrus insn not covered by the special cases below
; double cfldrd, cfldr64, cfstrd, cfstr64
; compare cfcmps, cfcmpd, cfcmp32, cfcmp64
; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
(define_attr "cirrus" "no,yes,double,compare,move" (const_string "no"))
(define_function_unit "cirrus_fpa" 1 0
(and (eq_attr "cirrus_fpu" "yes")
(eq_attr "cirrus_type" "farith")) 4 1)
(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))
(define_function_unit "cirrus_fpa" 1 0
(and (eq_attr "cirrus_fpu" "yes")
(eq_attr "cirrus_type" "dmult")) 7 4)
(define_function_unit "cirrus_fpa" 1 0
(and (eq_attr "cirrus_fpu" "yes")
(eq_attr "cirrus_type" "normal")) 1 1)
(define_insn "cirrus_adddi3"
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
@ -54,8 +36,8 @@
(match_operand:DI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfadd64%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_addsi3"
@ -64,8 +46,8 @@
(match_operand:SI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfadd32%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
;; define_insn replaced by define_expand and define_insn
@ -86,8 +68,8 @@
(match_operand:SF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfadds%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
;; define_insn replaced by define_expand and define_insn
@ -108,8 +90,8 @@
(match_operand:DF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfaddd%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_subdi3"
@ -118,8 +100,8 @@
(match_operand:DI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsub64%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_subsi3_insn"
@ -128,8 +110,8 @@
(match_operand:SI 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfsub32%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_expand "subsf3"
@ -153,8 +135,8 @@
(match_operand:SF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsubs%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_expand "subdf3"
@ -178,8 +160,8 @@
(match_operand:DF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsubd%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_mulsi3"
@ -188,8 +170,8 @@
(match_operand:SI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfmul32%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_insn "muldi3"
@ -198,8 +180,8 @@
(match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfmul64%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "dmult")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_dmult")
(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_mulsi3addsi"
@ -210,8 +192,8 @@
(match_operand:SI 3 "cirrus_fp_register" "0")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfmac32%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
;; Cirrus SI multiply-subtract
@ -223,8 +205,8 @@
(match_operand:SI 3 "cirrus_fp_register" "v"))))]
"0 && TARGET_ARM && TARGET_CIRRUS"
"cfmsc32%?\\t%V0, %V2, %V3"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_expand "mulsf3"
@ -244,8 +226,8 @@
(match_operand:SF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfmuls%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "farith")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
)
(define_expand "muldf3"
@ -265,8 +247,8 @@
(match_operand:DF 2 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfmuld%?\\t%V0, %V1, %V2"
[(set_attr "cirrus_type" "dmult")
(set_attr "cirrus" "yes")]
[(set_attr "type" "mav_dmult")
(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashl_const"
@ -275,7 +257,7 @@
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfsh32%?\\t%V0, %V1, #%s2"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashiftrt_const"
@ -284,7 +266,7 @@
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfsh32%?\\t%V0, %V1, #-%s2"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashlsi3"
@ -293,7 +275,7 @@
(match_operand:SI 2 "register_operand" "r")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfrshl32%?\\t%V1, %V0, %s2"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "ashldi3_cirrus"
@ -302,7 +284,7 @@
(match_operand:SI 2 "register_operand" "r")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfrshl64%?\\t%V1, %V0, %s2"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashldi_const"
@ -311,7 +293,7 @@
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsh64%?\\t%V0, %V1, #%s2"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "cirrus_ashiftrtdi_const"
@ -320,7 +302,7 @@
(match_operand:SI 2 "cirrus_shift_const" "")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfsh64%?\\t%V0, %V1, #-%s2"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_absdi2"
@ -328,7 +310,7 @@
(abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfabs64%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
;; This doesn't really clobber ``cc''. Fixme: aldyh.
@ -338,7 +320,7 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && TARGET_CIRRUS"
"cfneg64%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_negsi2"
@ -346,7 +328,7 @@
(neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfneg32%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_expand "negsf2"
@ -361,7 +343,7 @@
(neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfnegs%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_expand "negdf2"
@ -375,7 +357,7 @@
(neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfnegd%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_expand "abssi2"
@ -393,7 +375,7 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM && TARGET_CIRRUS && 0"
"cfabs32%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_expand "abssf2"
@ -407,7 +389,7 @@
(abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfabss%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_expand "absdf2"
@ -421,7 +403,7 @@
(abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfabsd%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_expand "floatsisf2"
@ -474,14 +456,14 @@
(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvt64s%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")])
[(set_attr "cirrus" "normal")])
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvt64d%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")])
[(set_attr "cirrus" "normal")])
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
@ -506,7 +488,7 @@
"TARGET_ARM && TARGET_CIRRUS"
"cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
[(set_attr "length" "8")
(set_attr "cirrus" "yes")]
(set_attr "cirrus" "normal")]
)
(define_expand "fix_truncdfsi2"
@ -546,7 +528,7 @@
(match_operand:DF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvtds%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_extendsfdf2"
@ -554,7 +536,7 @@
(float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))]
"TARGET_ARM && TARGET_CIRRUS"
"cfcvtsd%?\\t%V0, %V1"
[(set_attr "cirrus" "yes")]
[(set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_arm_movdi"
@ -582,11 +564,11 @@
default: abort ();
}
}"
[(set_attr "length" "8,8,8,8,8,4,4,4")
(set_attr "type" "*,load,store2,*,*,load,store2,*")
(set_attr "pool_range" "*,1020,*,*,*,*,*,*")
(set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")
(set_attr "cirrus" "no,no,no,move,yes,double,double,yes")]
[(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
(set_attr "type" " *,load,store2, *, *, load,store2, *")
(set_attr "pool_range" " *,1020, *, *, *, *, *, *")
(set_attr "neg_pool_range" " *,1012, *, *, *, *, *, *")
(set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
)
;; Cirrus SI values have been outlawed. Look in arm.h for the comment
@ -608,10 +590,10 @@
cfldr32%?\\t%V0, %1
cfstr32%?\\t%V1, %0
cfsh32%?\\t%V0, %V1, #0"
[(set_attr "type" "*,*,load,store1,*,*,load,store1,*")
(set_attr "pool_range" "*,*,4096,*,*,*,1024,*,*")
(set_attr "neg_pool_range" "*,*,4084,*,*,*,1012,*,*")
(set_attr "cirrus" "no,no,no,no,move,yes,yes,yes,yes")]
[(set_attr "type" "*, *, load,store1, *, *, load,store1, *")
(set_attr "pool_range" "*, *, 4096, *, *, *, 1024, *, *")
(set_attr "neg_pool_range" "*, *, 4084, *, *, *, 1012, *, *")
(set_attr "cirrus" "not,not, not, not,move,normal,normal,normal,normal")]
)
(define_insn "*cirrus_movsf_hard_insn"
@ -629,11 +611,11 @@
mov%?\\t%0, %1
ldr%?\\t%0, %1\\t%@ float
str%?\\t%1, %0\\t%@ float"
[(set_attr "length" "*,*,*,*,*,4,4,4")
(set_attr "type" "*,load,*,*,store1,*,load,store1")
(set_attr "pool_range" "*,*,*,*,*,*,4096,*")
(set_attr "neg_pool_range" "*,*,*,*,*,*,4084,*")
(set_attr "cirrus" "yes,yes,move,yes,yes,no,no,no")]
[(set_attr "length" " *, *, *, *, *, 4, 4, 4")
(set_attr "type" " *, load, *, *,store1, *,load,store1")
(set_attr "pool_range" " *, *, *, *, *, *,4096, *")
(set_attr "neg_pool_range" " *, *, *, *, *, *,4084, *")
(set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
)
(define_insn "*cirrus_movdf_hard_insn"
@ -658,10 +640,10 @@
default: abort ();
}
}"
[(set_attr "type" "load,store2,*,store2,load,*,load,*,*,store2")
(set_attr "length" "4,4,8,8,8,4,4,8,8,4")
(set_attr "pool_range" "*,*,*,*,252,*,*,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,244,*,*,*,*,*")
(set_attr "cirrus" "no,no,no,no,no,yes,double,move,yes,double")]
[(set_attr "type" "load,store2, *,store2,load, *, load, *, *,store2")
(set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
(set_attr "pool_range" " *, *, *, *, 252, *, *, *, *, *")
(set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *, *, *")
(set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
)