alpha.h (TARGET_SUPPORTS_WIDE_INT): New define.
* config/alpha/alpha.h (TARGET_SUPPORTS_WIDE_INT): New define. * config/alpha/alpha.c (alpha_rtx_costs): Handle CONST_WIDE_INT. (alpha_extract_integer): Ditto. (alpha_legitimate_constant_p): Ditto. (alpha_split_tmode_pair): Ditto. (alpha_preferred_reload_class): Add CONST_WIDE_INT. (alpha_expand_mov): Ditto. (print_operand): Remove handling of 'H' modifier. <case 'm'>: Remove CONST_DOUBLE handling. (summarize_insn): Handle CONST_WIDE_INT. * config/alpha/alpha.md (*andsi_internal): Remove H constraint. (anddi3): Ditto. (movti): Handle CONST_WIDE_INT. * config/alpha/constraints.md ('H'): Remove constraint definition. ('G'): Do not match MODE_FLOAT class. * config/alpha/predicates.md (const0_operand): Also match const_wide_int. (non_add_const_operand): Ditto. (non_zero_const_operand): Ditto. (some_operand): Ditto. (input_operand): Ditto. Handle CONST_WIDE_INT. (and_operand): Do not match const_double. * config/alpha/sync.md (fetchop_constr): Remove H constraint. From-SVN: r223097
This commit is contained in:
parent
46b35980b8
commit
f06ed65044
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@ -1,3 +1,29 @@
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2015-05-12 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.h (TARGET_SUPPORTS_WIDE_INT): New define.
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* config/alpha/alpha.c (alpha_rtx_costs): Handle CONST_WIDE_INT.
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(alpha_extract_integer): Ditto.
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(alpha_legitimate_constant_p): Ditto.
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(alpha_split_tmode_pair): Ditto.
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(alpha_preferred_reload_class): Add CONST_WIDE_INT.
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(alpha_expand_mov): Ditto.
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(print_operand): Remove handling of 'H' modifier.
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<case 'm'>: Remove CONST_DOUBLE handling.
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(summarize_insn): Handle CONST_WIDE_INT.
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* config/alpha/alpha.md (*andsi_internal): Remove H constraint.
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(anddi3): Ditto.
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(movti): Handle CONST_WIDE_INT.
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* config/alpha/constraints.md ('H'): Remove constraint definition.
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('G'): Do not match MODE_FLOAT class.
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* config/alpha/predicates.md (const0_operand): Also match
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const_wide_int.
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(non_add_const_operand): Ditto.
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(non_zero_const_operand): Ditto.
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(some_operand): Ditto.
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(input_operand): Ditto. Handle CONST_WIDE_INT.
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(and_operand): Do not match const_double.
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* config/alpha/sync.md (fetchop_constr): Remove H constraint.
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2015-05-12 Andrew MacLeod <amacleod@redhat.com>
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PR target/65697
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@ -1412,6 +1412,7 @@ alpha_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
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/* FALLTHRU */
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case CONST_DOUBLE:
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case CONST_WIDE_INT:
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if (x == CONST0_RTX (mode))
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*total = 0;
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else if ((outer_code == PLUS && add_operand (x, VOIDmode))
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@ -1647,6 +1648,7 @@ alpha_preferred_reload_class(rtx x, enum reg_class rclass)
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/* These sorts of constants we can easily drop to memory. */
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if (CONST_INT_P (x)
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|| GET_CODE (x) == CONST_WIDE_INT
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|| GET_CODE (x) == CONST_DOUBLE
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|| GET_CODE (x) == CONST_VECTOR)
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{
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@ -2104,8 +2106,8 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
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return target;
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}
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/* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
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the low 64 bits. */
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/* Given an integral CONST_INT, CONST_WIDE_INT, CONST_DOUBLE,
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or CONST_VECTOR, return the low 64 bits. */
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static void
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alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
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@ -2115,18 +2117,15 @@ alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
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if (GET_CODE (x) == CONST_VECTOR)
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x = simplify_subreg (DImode, x, GET_MODE (x), 0);
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if (CONST_INT_P (x))
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{
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i0 = INTVAL (x);
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i1 = -(i0 < 0);
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}
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i0 = INTVAL (x);
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else if (CONST_WIDE_INT_P (x))
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i0 = CONST_WIDE_INT_ELT (x, 0);
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else
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{
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i0 = CONST_DOUBLE_LOW (x);
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i1 = -(i0 < 0);
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}
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i0 = CONST_DOUBLE_LOW (x);
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i1 = -(i0 < 0);
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*p0 = i0;
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*p1 = i1;
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}
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@ -2163,12 +2162,15 @@ alpha_legitimate_constant_p (machine_mode mode, rtx x)
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/* TLS symbols are never valid. */
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return SYMBOL_REF_TLS_MODEL (x) == 0;
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case CONST_WIDE_INT:
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if (x == CONST0_RTX (mode))
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return true;
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goto do_integer;
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case CONST_DOUBLE:
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if (x == CONST0_RTX (mode))
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return true;
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if (FLOAT_MODE_P (mode))
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return false;
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goto do_integer;
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return false;
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case CONST_VECTOR:
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if (x == CONST0_RTX (mode))
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@ -2249,6 +2251,7 @@ alpha_expand_mov (machine_mode mode, rtx *operands)
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/* Split large integers. */
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if (CONST_INT_P (operands[1])
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|| GET_CODE (operands[1]) == CONST_WIDE_INT
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|| GET_CODE (operands[1]) == CONST_DOUBLE
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|| GET_CODE (operands[1]) == CONST_VECTOR)
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{
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@ -3291,6 +3294,7 @@ alpha_split_tmode_pair (rtx operands[4], machine_mode mode,
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break;
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case CONST_INT:
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case CONST_WIDE_INT:
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case CONST_DOUBLE:
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gcc_assert (operands[1] == CONST0_RTX (mode));
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operands[2] = operands[3] = const0_rtx;
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@ -5151,13 +5155,6 @@ print_operand (FILE *file, rtx x, int code)
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fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
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break;
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case 'H':
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if (GET_CODE (x) == HIGH)
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output_addr_const (file, XEXP (x, 0));
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else
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output_operand_lossage ("invalid %%H value");
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break;
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case 'J':
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{
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const char *lituse;
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@ -5254,27 +5251,7 @@ print_operand (FILE *file, rtx x, int code)
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case 'm':
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/* Write mask for ZAP insn. */
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if (GET_CODE (x) == CONST_DOUBLE)
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{
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HOST_WIDE_INT mask = 0;
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HOST_WIDE_INT value;
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value = CONST_DOUBLE_LOW (x);
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for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
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i++, value >>= 8)
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if (value & 0xff)
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mask |= (1 << i);
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value = CONST_DOUBLE_HIGH (x);
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for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
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i++, value >>= 8)
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if (value & 0xff)
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mask |= (1 << (i + sizeof (int)));
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
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}
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else if (CONST_INT_P (x))
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if (CONST_INT_P (x))
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{
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HOST_WIDE_INT mask = 0, value = INTVAL (x);
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summarize_insn (XEXP (x, 0), sum, 0);
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break;
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case CONST_INT: case CONST_DOUBLE:
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case SYMBOL_REF: case LABEL_REF: case CONST:
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case CONST_INT: case CONST_WIDE_INT: case CONST_DOUBLE:
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case SYMBOL_REF: case LABEL_REF: case CONST:
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case SCRATCH: case ASM_INPUT:
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break;
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@ -1066,3 +1066,5 @@ extern long alpha_auto_offset;
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/* The system headers under Alpha systems are generally C++-aware. */
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#define NO_IMPLICIT_EXTERN_C
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#define TARGET_SUPPORTS_WIDE_INT 1
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(define_insn "*andsi_internal"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
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(match_operand:SI 2 "and_operand" "rI,N,MH")))]
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(match_operand:SI 2 "and_operand" "rI,N,M")))]
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""
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"@
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and %r1,%2,%0
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(define_insn "anddi3"
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[(set (match_operand:DI 0 "register_operand" "=r,r,r")
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(and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
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(match_operand:DI 2 "and_operand" "rI,N,MH")))]
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(match_operand:DI 2 "and_operand" "rI,N,M")))]
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""
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"@
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and %r1,%2,%0
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32-bit constants in TImode and rely on the splitter, but
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this doesn't seem to be worth the pain. */
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else if (CONST_INT_P (operands[1])
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|| GET_CODE (operands[1]) == CONST_WIDE_INT
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|| GET_CODE (operands[1]) == CONST_DOUBLE)
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{
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rtx in[2], out[2], target;
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@ -18,7 +18,7 @@
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;; <http://www.gnu.org/licenses/>.
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;;; Unused letters:
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;;; ABCDEF V YZ
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;;; ABCDEF H V YZ
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;;; de ghijkl pq tu wxyz
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;; Integer register constraints.
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(and (match_code "const_int")
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(match_test "ival == 1 || ival == 2 || ival == 3")))
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(define_constraint "H"
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"A valid operand of a ZAP insn, when building with 32-bit HOST_WIDE_INT"
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(and (match_code "const_double")
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(match_test "mode == VOIDmode && zap_mask (hval) && zap_mask (lval)")))
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;; Floating-point constant constraints.
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(define_constraint "G"
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"The floating point zero constant"
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(and (match_code "const_double")
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(match_test "GET_MODE_CLASS (mode) == MODE_FLOAT
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&& op == CONST0_RTX (mode)")))
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(match_test "op == CONST0_RTX (mode)")))
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;; "Extra" constraints.
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(define_constraint "Q"
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;; Return 1 if OP is the zero constant for MODE.
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(define_predicate "const0_operand"
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(and (match_code "const_int,const_double,const_vector")
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(and (match_code "const_int,const_wide_int,const_double,const_vector")
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(match_test "op == CONST0_RTX (mode)")))
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;; Returns true if OP is either the constant zero or a register.
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;; Return 1 if the operand is a non-symbolic constant operand that
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;; does not satisfy add_operand.
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(define_predicate "non_add_const_operand"
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(and (match_code "const_int,const_double,const_vector")
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(and (match_code "const_int,const_wide_int,const_double,const_vector")
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(not (match_operand 0 "add_operand"))))
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;; Return 1 if the operand is a non-symbolic, nonzero constant operand.
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(define_predicate "non_zero_const_operand"
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(and (match_code "const_int,const_double,const_vector")
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(and (match_code "const_int,const_wide_int,const_double,const_vector")
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(match_test "op != CONST0_RTX (mode)")))
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;; Return 1 if OP is the constant 4 or 8.
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(match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
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|| (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
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|| zap_mask (INTVAL (op))")
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(if_then_else (match_code "const_double")
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(match_test "GET_MODE (op) == VOIDmode
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&& zap_mask (CONST_DOUBLE_LOW (op))
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&& zap_mask (CONST_DOUBLE_HIGH (op))")
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(match_operand 0 "register_operand"))))
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(match_operand 0 "register_operand")))
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;; Return 1 if OP is a valid first operand to an IOR or XOR insn.
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(define_predicate "or_operand"
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@ -155,7 +151,7 @@
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;; Return 1 if OP is something that can be reloaded into a register;
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;; if it is a MEM, it need not be valid.
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(define_predicate "some_operand"
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(ior (match_code "reg,mem,const_int,const_double,const_vector,
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(ior (match_code "reg,mem,const_int,const_wide_int,const_double,const_vector,
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label_ref,symbol_ref,const,high")
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(and (match_code "subreg")
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(match_test "some_operand (SUBREG_REG (op), VOIDmode)"))))
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;; Return 1 if OP is a valid operand for the source of a move insn.
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(define_predicate "input_operand"
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(match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
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const_double,const_vector,const_int")
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const_double,const_vector,const_int,const_wide_int")
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{
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switch (GET_CODE (op))
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{
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@ -205,6 +201,7 @@
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return ((TARGET_BWX || (mode != HImode && mode != QImode))
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&& general_operand (op, mode));
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case CONST_WIDE_INT:
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case CONST_DOUBLE:
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return op == CONST0_RTX (mode);
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@ -24,7 +24,7 @@
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[(plus "add_operand") (minus "reg_or_8bit_operand")
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(ior "or_operand") (xor "or_operand") (and "and_operand")])
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(define_code_attr fetchop_constr
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[(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNHM")])
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[(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNM")])
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(define_expand "memory_barrier"
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