From f13d510e361b10bc0c83e211671f158c6665cd8e Mon Sep 17 00:00:00 2001 From: Kelvin Nilsen Date: Thu, 1 Dec 2016 22:52:07 +0000 Subject: [PATCH] re PR target/78577 (Fix define_insn operand types for vexturhlx, vexturhrx, vextuwlx, and vextuwrx patterns) gcc/ChangeLog: 2016-12-01 Kelvin Nilsen PR target/78577 * config/rs6000/vsx.md (vextuhlx): Revise mode of operand 2. (vextuhrx): Likewise. (vextuwlx): Likewise. (vextuwrx): Likewise. From-SVN: r243141 --- gcc/ChangeLog | 8 ++++++++ gcc/config/rs6000/vsx.md | 8 ++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b23481f457e..7f9dd0e2ed2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2016-12-01 Kelvin Nilsen + + PR target/78577 + * config/rs6000/vsx.md (vextuhlx): Revise mode of operand 2. + (vextuhrx): Likewise. + (vextuwlx): Likewise. + (vextuwrx): Likewise. + 2016-12-01 David Malcolm * dwarf2out.c (dwarf2out_c_finalize): Reset early_dwarf and diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 01d275d168e..1801bc05906 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3648,7 +3648,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V8HI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUHLX))] "TARGET_P9_VECTOR" "vextuhlx %0,%1,%2" @@ -3659,7 +3659,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V8HI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUHRX))] "TARGET_P9_VECTOR" "vextuhrx %0,%1,%2" @@ -3670,7 +3670,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V4SI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUWLX))] "TARGET_P9_VECTOR" "vextuwlx %0,%1,%2" @@ -3681,7 +3681,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:V16QI 2 "altivec_register_operand" "v")] + (match_operand:V4SI 2 "altivec_register_operand" "v")] UNSPEC_VEXTUWRX))] "TARGET_P9_VECTOR" "vextuwrx %0,%1,%2"