reduce conditional compilation for LOAD_EXTEND_OP
Provide a default in files where that is possible, so that everything else there can be unconditionally compiled. However rtlanal.c and reload.c do tricky things that break providing a global default, so we can't do that yet. gcc/ChangeLog: 2015-07-08 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * combine.c (try_combine): Don't check if LOAD_EXTEND_OP is defined. (simplify_set): Likewise. * cse.c (cse_insn): Likewise. * fold-const.c (fold_single_bit_test): Likewise. (fold_unary_loc): Likewise. * postreload.c (reload_cse_simplify_set): Likewise. (reload_cse_simplify_operands): Likewise. From-SVN: r225591
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@ -1,3 +1,14 @@
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2015-07-08 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
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* combine.c (try_combine): Don't check if LOAD_EXTEND_OP is
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defined.
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(simplify_set): Likewise.
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* cse.c (cse_insn): Likewise.
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* fold-const.c (fold_single_bit_test): Likewise.
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(fold_unary_loc): Likewise.
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* postreload.c (reload_cse_simplify_set): Likewise.
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(reload_cse_simplify_operands): Likewise.
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2015-07-08 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64.c (aarch64_unspec_may_trap_p): New function.
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@ -113,6 +113,10 @@ along with GCC; see the file COPYING3. If not see
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#include "obstack.h"
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#include "rtl-iter.h"
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#ifndef LOAD_EXTEND_OP
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#define LOAD_EXTEND_OP(M) UNKNOWN
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#endif
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/* Number of attempts to combine instructions in this function. */
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static int combine_attempts;
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@ -3744,7 +3748,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
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be written as a ZERO_EXTEND. */
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if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
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{
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#ifdef LOAD_EXTEND_OP
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/* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
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what it really is. */
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if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
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@ -3752,7 +3755,6 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
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SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
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SUBREG_REG (*split)));
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else
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#endif
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SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
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SUBREG_REG (*split)));
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}
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@ -6772,7 +6774,6 @@ simplify_set (rtx x)
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}
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}
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#ifdef LOAD_EXTEND_OP
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/* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
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would require a paradoxical subreg. Replace the subreg with a
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zero_extend to avoid the reload that would otherwise be required. */
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@ -6790,7 +6791,6 @@ simplify_set (rtx x)
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src = SET_SRC (x);
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}
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#endif
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/* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
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are comparing an item known to be 0 or -1 against 0, use a logical
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@ -51,6 +51,10 @@ along with GCC; see the file COPYING3. If not see
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#include "dbgcnt.h"
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#include "rtl-iter.h"
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#ifndef LOAD_EXTEND_OP
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#define LOAD_EXTEND_OP(M) UNKNOWN
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#endif
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/* The basic idea of common subexpression elimination is to go
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through the code, keeping a record of expressions that would
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have the same value at the current scan point, and replacing
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@ -4867,7 +4871,6 @@ cse_insn (rtx_insn *insn)
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}
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}
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#ifdef LOAD_EXTEND_OP
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/* See if a MEM has already been loaded with a widening operation;
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if it has, we can use a subreg of that. Many CISC machines
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also have such operations, but this is only likely to be
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@ -4913,7 +4916,6 @@ cse_insn (rtx_insn *insn)
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break;
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}
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}
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#endif /* LOAD_EXTEND_OP */
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/* Try to express the constant using a register+offset expression
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derived from a constant anchor. */
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@ -77,6 +77,10 @@ along with GCC; see the file COPYING3. If not see
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#include "generic-match.h"
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#include "optabs.h"
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#ifndef LOAD_EXTEND_OP
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#define LOAD_EXTEND_OP(M) UNKNOWN
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#endif
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/* Nonzero if we are folding constants inside an initializer; zero
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otherwise. */
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int folding_initializer = 0;
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@ -6646,12 +6650,8 @@ fold_single_bit_test (location_t loc, enum tree_code code,
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/* If we are going to be able to omit the AND below, we must do our
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operations as unsigned. If we must use the AND, we have a choice.
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Normally unsigned is faster, but for some machines signed is. */
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#ifdef LOAD_EXTEND_OP
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ops_unsigned = (LOAD_EXTEND_OP (operand_mode) == SIGN_EXTEND
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&& !flag_syntax_only) ? 0 : 1;
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#else
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ops_unsigned = 1;
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#endif
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signed_type = lang_hooks.types.type_for_mode (operand_mode, 0);
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unsigned_type = lang_hooks.types.type_for_mode (operand_mode, 1);
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@ -7815,7 +7815,6 @@ fold_unary_loc (location_t loc, enum tree_code code, tree type, tree op0)
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cst &= HOST_WIDE_INT_M1U
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<< (TYPE_PRECISION (TREE_TYPE (and1)) - 1);
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change = (cst == 0);
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#ifdef LOAD_EXTEND_OP
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if (change
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&& !flag_syntax_only
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&& (LOAD_EXTEND_OP (TYPE_MODE (TREE_TYPE (and0)))
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@ -7825,7 +7824,6 @@ fold_unary_loc (location_t loc, enum tree_code code, tree type, tree op0)
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and0 = fold_convert_loc (loc, uns, and0);
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and1 = fold_convert_loc (loc, uns, and1);
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}
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#endif
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}
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if (change)
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{
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@ -54,6 +54,10 @@ along with GCC; see the file COPYING3. If not see
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#include "tree-pass.h"
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#include "dbgcnt.h"
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#ifndef LOAD_EXTEND_OP
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#define LOAD_EXTEND_OP(M) UNKNOWN
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#endif
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static int reload_cse_noop_set_p (rtx);
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static bool reload_cse_simplify (rtx_insn *, rtx);
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static void reload_cse_regs_1 (void);
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@ -254,9 +258,7 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
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int old_cost;
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cselib_val *val;
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struct elt_loc_list *l;
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#ifdef LOAD_EXTEND_OP
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enum rtx_code extend_op = UNKNOWN;
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#endif
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bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
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dreg = true_regnum (SET_DEST (set));
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@ -269,7 +271,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
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dclass = REGNO_REG_CLASS (dreg);
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#ifdef LOAD_EXTEND_OP
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/* When replacing a memory with a register, we need to honor assumptions
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that combine made wrt the contents of sign bits. We'll do this by
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generating an extend instruction instead of a reg->reg copy. Thus
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@ -279,7 +280,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
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&& (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
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&& !REG_P (SET_DEST (set)))
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return 0;
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#endif
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val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
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if (! val)
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@ -301,7 +301,6 @@ reload_cse_simplify_set (rtx set, rtx_insn *insn)
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if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
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{
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#ifdef LOAD_EXTEND_OP
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if (extend_op != UNKNOWN)
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{
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wide_int result;
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}
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this_rtx = immed_wide_int_const (result, word_mode);
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}
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#endif
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this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed);
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}
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else if (REG_P (this_rtx))
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{
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#ifdef LOAD_EXTEND_OP
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if (extend_op != UNKNOWN)
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{
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this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
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this_cost = set_src_cost (this_rtx, word_mode, speed);
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}
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else
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#endif
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this_cost = register_move_cost (GET_MODE (this_rtx),
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REGNO_REG_CLASS (REGNO (this_rtx)),
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dclass);
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&& REG_P (this_rtx)
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&& !REG_P (SET_SRC (set))))
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{
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#ifdef LOAD_EXTEND_OP
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if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
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&& extend_op != UNKNOWN
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#ifdef CANNOT_CHANGE_MODE_CLASS
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ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
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validate_change (insn, &SET_DEST (set), wide_dest, 1);
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}
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#endif
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validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
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old_cost = this_cost, did_change = 1;
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continue;
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op = recog_data.operand[i];
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#ifdef LOAD_EXTEND_OP
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if (MEM_P (op)
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&& GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
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&& LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
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safe to optimize, but is it worth the trouble? */
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continue;
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}
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#endif /* LOAD_EXTEND_OP */
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if (side_effects_p (op))
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continue;
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v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
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