re PR target/17245 (ICE compiling gsl-1.5 statistics/lag1.c)
PR target/17245 * config/sparc/sparc.c (legitimate_address_p): Remove 'imm2'. Revert 2004-10-08 patch. Reject TFmode LO_SUM in 32-bit mode. From-SVN: r97713
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@ -1,3 +1,9 @@
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2005-04-06 Eric Botcazou <ebotcazou@libertysurf.fr>
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PR target/17245
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* config/sparc/sparc.c (legitimate_address_p): Remove 'imm2'.
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Revert 2004-10-08 patch. Reject TFmode LO_SUM in 32-bit mode.
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2005-04-06 Kelley Cook <kcook@gcc.gnu.org>
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2005-04-06 Kelley Cook <kcook@gcc.gnu.org>
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* Makefile.in (LIBGCC2_CFLAGS): Revert -pipe change.
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* Makefile.in (LIBGCC2_CFLAGS): Revert -pipe change.
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@ -3500,7 +3500,7 @@ legitimate_pic_operand_p (rtx x)
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int
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int
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legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
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legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
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{
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{
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rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
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rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
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if (REG_P (addr) || GET_CODE (addr) == SUBREG)
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if (REG_P (addr) || GET_CODE (addr) == SUBREG)
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rs1 = addr;
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rs1 = addr;
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@ -3564,7 +3564,6 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
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&& ! TARGET_CM_MEDMID
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&& ! TARGET_CM_MEDMID
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&& RTX_OK_FOR_OLO10_P (rs2))
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&& RTX_OK_FOR_OLO10_P (rs2))
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{
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{
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imm2 = rs2;
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rs2 = NULL;
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rs2 = NULL;
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imm1 = XEXP (rs1, 1);
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imm1 = XEXP (rs1, 1);
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rs1 = XEXP (rs1, 0);
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rs1 = XEXP (rs1, 0);
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@ -3580,25 +3579,10 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
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if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
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if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
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return 0;
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return 0;
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if (USE_AS_OFFSETABLE_LO10)
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/* We can't allow TFmode in 32-bit mode, because an offset greater
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{
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than the alignment (8) may cause the LO_SUM to overflow. */
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/* We can't allow TFmode, because an offset greater than or equal to
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if (mode == TFmode && !TARGET_64BIT)
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the alignment (8) may cause the LO_SUM to overflow if !v9. */
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return 0;
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if (mode == TFmode && ! TARGET_V9)
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return 0;
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}
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else
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{
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/* We prohibit LO_SUM for TFmode when there are no quad move insns
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and we consequently need to split. We do this because LO_SUM
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is not an offsettable address. If we get the situation in reload
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where source and destination of a movtf pattern are both MEMs with
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LO_SUM address, then only one of them gets converted to an
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offsettable address. */
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if (mode == TFmode
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&& ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
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return 0;
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}
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}
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}
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else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
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else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
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return 1;
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return 1;
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