diff --git a/gcc/builtins.c b/gcc/builtins.c index 1201f1c1cbd..764a4aa711c 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -242,9 +242,9 @@ get_pointer_alignment (tree exp, unsigned int max_align) way, because it could contain a zero byte in the middle. TREE_STRING_LENGTH is the size of the character array, not the string. - ONLY_VALUE should be non-zero if the result is not going to be emitted + ONLY_VALUE should be nonzero if the result is not going to be emitted into the instruction stream and zero if it is going to be expanded. - E.g. with i++ ? "foo" : "bar", if ONLY_VALUE is non-zero, constant 3 + E.g. with i++ ? "foo" : "bar", if ONLY_VALUE is nonzero, constant 3 is returned, otherwise NULL, since len = c_strlen (src, 1); if (len) expand_expr (len, ...); would not evaluate the side-effects. diff --git a/gcc/cgraph.c b/gcc/cgraph.c index ffc33123028..d8908afb407 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -373,7 +373,7 @@ cgraph_varpool_hash_node (const PTR p) (((struct cgraph_varpool_node *) p)->decl)); } -/* Returns non-zero if P1 and P2 are equal. */ +/* Returns nonzero if P1 and P2 are equal. */ static int eq_cgraph_varpool_node (const PTR p1, const PTR p2) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c0ee99ed8c3..c02e7be901a 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2094,7 +2094,7 @@ arm_va_arg (tree valist, tree type) TREE_SIDE_EFFECTS (t) = 1; expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); - /* This is to stop the combine pass optimising + /* This is to stop the combine pass optimizing away the alignment adjustment. */ mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); } diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index 5f3fd7bf17f..f9ef5211e2f 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -185,7 +185,7 @@ (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) ;; This pattern should not be needed. It is to match a -;; wierd case generated by GCC when no optimisations are +;; wierd case generated by GCC when no optimizations are ;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/ ;; compile/simd-5.c at -O0). The mode for operands[1] is ;; deliberately omitted. diff --git a/gcc/config/c4x/c4x-modes.def b/gcc/config/c4x/c4x-modes.def index 50798069cc6..be536e05645 100644 --- a/gcc/config/c4x/c4x-modes.def +++ b/gcc/config/c4x/c4x-modes.def @@ -25,7 +25,7 @@ On the C4x, we have a "no-overflow" mode which is used when an ADD, SUB, NEG, or MPY insn is used to set the condition code. This is - to prevent the combiner from optimising away a following CMP of the + to prevent the combiner from optimizing away a following CMP of the result with zero when a signed conditional branch or load insn follows. diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c index 5d097cc0cda..bc677832f93 100644 --- a/gcc/config/c4x/c4x.c +++ b/gcc/config/c4x/c4x.c @@ -1692,7 +1692,7 @@ c4x_legitimize_address (orig, mode) /* Provide the costs of an addressing mode that contains ADDR. If ADDR is not a valid address, its cost is irrelevant. - This is used in cse and loop optimisation to determine + This is used in cse and loop optimization to determine if it is worthwhile storing a common address into a register. Unfortunately, the C4x address cost depends on other operands. */ @@ -2437,7 +2437,7 @@ c4x_rptb_insert (insn) /* We need to use direct addressing for large constants and addresses that cannot fit within an instruction. We must check for these - after after the final jump optimisation pass, since this may + after after the final jump optimization pass, since this may introduce a local_move insn for a SYMBOL_REF. This pass must come before delayed branch slot filling since it can generate additional instructions. @@ -3642,7 +3642,7 @@ c4x_address_conflict (op0, op1, store0, store1) cause problems except when writing to a hardware device such as a FIFO since the second write will be lost. The user should flag the hardware location as being volatile so that - we don't do this optimisation. While it is unlikely that we + we don't do this optimization. While it is unlikely that we have an aliased address if both locations are not marked volatile, it is probably safer to flag a potential conflict if either location is volatile. */ @@ -4034,7 +4034,7 @@ legitimize_operands (code, operands, mode) /* During RTL generation, force constants into pseudos so that they can get hoisted out of loops. This will tie up an extra register but can save an extra cycle. Only do this if loop - optimisation enabled. (We cannot pull this trick for add and + optimization enabled. (We cannot pull this trick for add and sub instructions since the flow pass won't find autoincrements etc.) This allows us to generate compare instructions like CMPI R0, *AR0++ where R0 = 42, say, instead diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h index fb3622bb313..3fa2d91ef6e 100644 --- a/gcc/config/c4x/c4x.h +++ b/gcc/config/c4x/c4x.h @@ -775,7 +775,7 @@ enum reg_class is defined since the MPY|ADD insns require the classes R0R1_REGS and R2R3_REGS which are used by the function return registers (R0,R1) and the register arguments (R2,R3), respectively. I'm reluctant to define - this macro since it stomps on many potential optimisations. Ideally + this macro since it stomps on many potential optimizations. Ideally it should have a register class argument so that not all the register classes gets penalised for the sake of a naughty few... For long double arithmetic we need two additional registers that we can use as diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index 07e140b0506..0957fe9ef70 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -3127,9 +3127,9 @@ ; Unfortunately the C40 doesn't allow cmpi3 7, *ar0++ so the next best ; thing would be to get the small constant loaded into a register (say r0) ; so that it could be hoisted out of the loop so that we only -; would need to do cmpi3 *ar0++, r0. Now the loop optimisation pass +; would need to do cmpi3 *ar0++, r0. Now the loop optimization pass ; comes before the flow pass (which finds autoincrements) so we're stuck. -; Ideally, GCC requires another loop optimisation pass (preferably after +; Ideally, GCC requires another loop optimization pass (preferably after ; reload) so that it can hoist invariants out of loops. ; The current solution modifies legitimize_operands () so that small ; constants are forced into a pseudo register. diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h index c58d07ba787..4d5e202c16a 100644 --- a/gcc/config/i386/i386-interix.h +++ b/gcc/config/i386/i386-interix.h @@ -236,7 +236,7 @@ Boston, MA 02111-1307, USA. */ #define TARGET_NOP_FUN_DLLIMPORT 1 #define drectve_section() /* nothing */ -/* Objective C has its own packing rules... +/* Objective-C has its own packing rules... Objc tries to parallel the code in stor-layout.c at runtime (see libobjc/encoding.c). This (compile-time) packing info isn't available at runtime, so it's hopeless to try. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 40ea4df9364..6325d9534a9 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -3166,7 +3166,7 @@ typedef struct mips_args { /* The cost of loading values from the constant pool. It should be - larger than the cost of any constant we want to synthesise in-line. */ + larger than the cost of any constant we want to synthesize in-line. */ #define CONSTANT_POOL_COST COSTS_N_INSNS (8) diff --git a/gcc/cpplex.c b/gcc/cpplex.c index 6933e75035b..c536c768813 100644 --- a/gcc/cpplex.c +++ b/gcc/cpplex.c @@ -746,7 +746,7 @@ _cpp_get_fresh_line (cpp_reader *pfile) get diagnostics pointing to the correct location. Does not handle issues such as token lookahead, multiple-include - optimisation, directives, skipping etc. This function is only + optimization, directives, skipping etc. This function is only suitable for use by _cpp_lex_token, and in special cases like lex_expansion_token which doesn't care for any of these issues.