sh.c (register_sh_passes, [...]): Remove TARGET_SH1 checks.
gcc/ * config/sh/sh.c (register_sh_passes, sh_option_override, sh_print_operand, prepare_move_operands, sh_can_follow_jump): Remove TARGET_SH1 checks. * config/sh/sh.h (TARGET_VARARGS_PRETEND_ARGS, VALID_REGISTER_P, PROMOTE_MODE): Likewise. * config/sh/sh.md (adddi3, addsi3, subdi3, subsi3, andsi3, movdi): Likewise. From-SVN: r235674
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85e051a3c4
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@ -1,3 +1,13 @@
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2016-04-30 Oleg Endo <olegendo@gcc.gnu.org>
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* config/sh/sh.c (register_sh_passes, sh_option_override,
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sh_print_operand, prepare_move_operands,
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sh_can_follow_jump): Remove TARGET_SH1 checks.
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* config/sh/sh.h (TARGET_VARARGS_PRETEND_ARGS, VALID_REGISTER_P,
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PROMOTE_MODE): Likewise.
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* config/sh/sh.md (adddi3, addsi3, subdi3, subsi3, andsi3,
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movdi): Likewise.
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2016-04-30 Alan Modra <amodra@gmail.com>
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* config/rs6000/rs6000.c (rs6000_savres_strategy): Force inline
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@ -772,9 +772,6 @@ extern opt_pass* make_pass_sh_optimize_sett_clrt (gcc::context* ctx,
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static void
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register_sh_passes (void)
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{
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if (!TARGET_SH1)
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return;
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/* Running the sh_treg_combine pass after ce1 generates better code when
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comparisons are combined and reg-reg moves are introduced, because
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reg-reg moves will be eliminated afterwards. However, there are quite
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@ -848,36 +845,31 @@ sh_option_override (void)
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if (!TARGET_SH3 && TARGET_USERMODE)
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TARGET_USERMODE = false;
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if (TARGET_SH1)
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if (! strcmp (sh_div_str, "call-div1"))
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sh_div_strategy = SH_DIV_CALL_DIV1;
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else if (! strcmp (sh_div_str, "call-fp") && TARGET_FPU_ANY)
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sh_div_strategy = SH_DIV_CALL_FP;
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else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT)
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sh_div_strategy = SH_DIV_CALL_TABLE;
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else
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{
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if (! strcmp (sh_div_str, "call-div1"))
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sh_div_strategy = SH_DIV_CALL_DIV1;
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else if (! strcmp (sh_div_str, "call-fp")
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&& (TARGET_FPU_DOUBLE || TARGET_FPU_SINGLE_ONLY
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|| TARGET_FPU_ANY))
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sh_div_strategy = SH_DIV_CALL_FP;
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else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT)
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sh_div_strategy = SH_DIV_CALL_TABLE;
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else
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/* Pick one that makes most sense for the target in general.
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It is not much good to use different functions depending
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on -Os, since then we'll end up with two different functions
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when some of the code is compiled for size, and some for
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speed. */
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/* Pick one that makes most sense for the target in general.
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It is not much good to use different functions depending on -Os,
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since then we'll end up with two different functions when some of
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the code is compiled for size, and some for speed. */
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/* SH4 tends to emphasize speed. */
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if (TARGET_HARD_SH4)
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sh_div_strategy = SH_DIV_CALL_TABLE;
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/* These have their own way of doing things. */
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else if (TARGET_SH2A)
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sh_div_strategy = SH_DIV_INTRINSIC;
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/* SH1 .. SH3 cores often go into small-footprint systems, so
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default to the smallest implementation available. */
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else
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sh_div_strategy = SH_DIV_CALL_DIV1;
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/* SH4 tends to emphasize speed. */
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if (TARGET_HARD_SH4)
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sh_div_strategy = SH_DIV_CALL_TABLE;
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/* These have their own way of doing things. */
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else if (TARGET_SH2A)
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sh_div_strategy = SH_DIV_INTRINSIC;
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/* SH1 .. SH3 cores often go into small-footprint systems, so
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default to the smallest implementation available. */
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else
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sh_div_strategy = SH_DIV_CALL_DIV1;
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}
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if (!TARGET_SH1)
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TARGET_PRETEND_CMOVE = 0;
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if (sh_divsi3_libfunc[0])
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; /* User supplied - leave it alone. */
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else if (TARGET_DIVIDE_CALL_FP)
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@ -1443,8 +1435,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
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break;
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default:
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if (TARGET_SH1)
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fputc ('#', stream);
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fputc ('#', stream);
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output_addr_const (stream, x);
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break;
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}
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@ -1618,8 +1609,7 @@ prepare_move_operands (rtx operands[], machine_mode mode)
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of a library call to the target. Reject `st r0,@(rX,rY)' because
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reload will fail to find a spill register for rX, since r0 is already
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being used for the source. */
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else if (TARGET_SH1
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&& refers_to_regno_p (R0_REG, operands[1])
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else if (refers_to_regno_p (R0_REG, operands[1])
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&& MEM_P (operands[0])
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&& GET_CODE (XEXP (operands[0], 0)) == PLUS
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&& REG_P (XEXP (XEXP (operands[0], 0), 1)))
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@ -1639,7 +1629,7 @@ prepare_move_operands (rtx operands[], machine_mode mode)
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case. We can pre-allocate R0 for that index term to avoid
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the issue. See PR target/66591. */
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else if (sh_lra_p ()
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&& TARGET_SH1 && ! TARGET_SH2A
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&& ! TARGET_SH2A
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&& ((REG_P (operands[0]) && MEM_P (operands[1]))
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|| (REG_P (operands[1]) && MEM_P (operands[0]))))
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{
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@ -9590,8 +9580,7 @@ sh_can_follow_jump (const rtx_insn *branch1, const rtx_insn *branch2)
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{
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/* Don't follow if BRANCH2 is possible to be a jump crossing between
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hot and cold partitions. */
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if (TARGET_SH1
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&& flag_reorder_blocks_and_partition
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if (flag_reorder_blocks_and_partition
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&& simplejump_p (branch2)
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&& CROSSING_JUMP_P (branch2))
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return false;
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@ -77,7 +77,7 @@ extern int code_for_indirect_jump_scratch;
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/* This is not used by the SH2E calling convention */
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#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
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(TARGET_SH1 && ! TARGET_SH2E \
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(! TARGET_SH2E \
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&& ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
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#ifndef TARGET_CPU_DEFAULT
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@ -636,7 +636,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
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|| XD_REGISTER_P (REGNO) \
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|| (REGNO) == AP_REG || (REGNO) == RAP_REG \
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|| (REGNO) == FRAME_POINTER_REGNUM \
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|| (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
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|| ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
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|| (TARGET_SH2E && (REGNO) == FPUL_REG))
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/* The mode that should be generally used to store a register by
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@ -1879,8 +1879,7 @@ extern int current_function_interrupt;
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#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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if (GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
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(UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
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(MODE) = (TARGET_SH1 ? SImode : DImode);
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(UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode;
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#define MAX_FIXED_MODE_SIZE (64)
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@ -1529,12 +1529,9 @@
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(match_operand:DI 2 "arith_operand")))]
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""
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{
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if (TARGET_SH1)
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{
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operands[2] = force_reg (DImode, operands[2]);
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emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
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DONE;
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}
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operands[2] = force_reg (DImode, operands[2]);
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emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn_and_split "adddi3_compact"
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(match_operand:SI 2 "arith_or_int_operand")))]
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""
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{
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if (TARGET_SH1 && !arith_operand (operands[2], SImode))
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if (!arith_operand (operands[2], SImode))
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{
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if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1]))
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{
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@ -1935,12 +1932,9 @@
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(match_operand:DI 2 "arith_reg_operand" "")))]
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""
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{
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if (TARGET_SH1)
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{
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operands[1] = force_reg (DImode, operands[1]);
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emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
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DONE;
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}
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operands[1] = force_reg (DImode, operands[1]);
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emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn_and_split "subdi3_compact"
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(match_operand:SI 2 "arith_reg_operand" "")))]
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""
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{
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if (TARGET_SH1 && CONST_INT_P (operands[1]))
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if (CONST_INT_P (operands[1]))
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{
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emit_insn (gen_negsi2 (operands[0], operands[2]));
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emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
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Ideally the splitter of *andsi_compact would be enough, if redundant
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zero extensions were detected after the combine pass, which does not
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happen at the moment. */
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if (TARGET_SH1)
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if (satisfies_constraint_Jmb (operands[2]))
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{
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if (satisfies_constraint_Jmb (operands[2]))
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{
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emit_insn (gen_zero_extendqisi2 (operands[0],
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gen_lowpart (QImode, operands[1])));
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DONE;
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}
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else if (satisfies_constraint_Jmw (operands[2]))
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{
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emit_insn (gen_zero_extendhisi2 (operands[0],
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gen_lowpart (HImode, operands[1])));
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DONE;
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}
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emit_insn (gen_zero_extendqisi2 (operands[0],
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gen_lowpart (QImode, operands[1])));
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DONE;
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}
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else if (satisfies_constraint_Jmw (operands[2]))
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{
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emit_insn (gen_zero_extendhisi2 (operands[0],
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gen_lowpart (HImode, operands[1])));
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DONE;
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}
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})
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""
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{
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prepare_move_operands (operands, DImode);
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if (TARGET_SH1)
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/* When the dest operand is (R0, R1) register pair, split it to
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two movsi of which dest is R1 and R0 so as to lower R0-register
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pressure on the first movsi. Apply only for simple source not
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to make complex rtl here. */
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if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG
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&& REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
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{
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/* When the dest operand is (R0, R1) register pair, split it to
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two movsi of which dest is R1 and R0 so as to lower R0-register
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pressure on the first movsi. Apply only for simple source not
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to make complex rtl here. */
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if (REG_P (operands[0])
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&& REGNO (operands[0]) == R0_REG
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&& REG_P (operands[1])
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&& REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
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{
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emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
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gen_rtx_SUBREG (SImode, operands[1], 4)));
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emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
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gen_rtx_SUBREG (SImode, operands[1], 0)));
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DONE;
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}
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emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
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gen_rtx_SUBREG (SImode, operands[1], 4)));
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emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
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gen_rtx_SUBREG (SImode, operands[1], 0)));
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DONE;
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}
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})
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