re PR rtl-optimization/13145 (bootstrap failure on mips-linux)
PR bootstrap/13145 * config/mips/mips.h (FIRST_PSEUDO_REGISTER): Adjust comment. * config/mips/mips.c (mips_reg_names, mips_sw_reg_names): Add $fcall. (mips_load_got): Always create a constant MEM. (mips_expand_call): Use load_callsi and load_calldi. * config/mips/mips.md (UNSPEC_LOAD_CALL, FAKE_CALL_REGNO): New consts. (load_callsi, load_calldi): New patterns. From-SVN: r74323
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
b00b4b8855
commit
f24e76ebc6
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@ -1,3 +1,13 @@
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2003-12-05 Richard Sandiford <rsandifo@redhat.com>
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PR bootstrap/13145
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* config/mips/mips.h (FIRST_PSEUDO_REGISTER): Adjust comment.
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* config/mips/mips.c (mips_reg_names, mips_sw_reg_names): Add $fcall.
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(mips_load_got): Always create a constant MEM.
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(mips_expand_call): Use load_callsi and load_calldi.
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* config/mips/mips.md (UNSPEC_LOAD_CALL, FAKE_CALL_REGNO): New consts.
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(load_callsi, load_calldi): New patterns.
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2003-12-05 Peter Gerwinski <peter@gerwinski.de>
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* tree.def (PLACEHOLDER_EXPR): Clarify commentary.
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@ -569,7 +569,7 @@ char mips_reg_names[][8] =
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"$fcc5","$fcc6","$fcc7","", "", "", "", "",
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"$fcc5","$fcc6","$fcc7","", "", "", "", "$fakec",
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"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
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"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
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"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
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@ -598,7 +598,7 @@ char mips_sw_reg_names[][8] =
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
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"$fcc5","$fcc6","$fcc7","$rap", "", "", "", "$fakec",
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"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
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"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
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"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
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@ -1658,14 +1658,10 @@ mips_load_got (rtx base, rtx addr, enum mips_symbol_type symbol_type)
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mem = gen_rtx_MEM (ptr_mode, gen_rtx_LO_SUM (Pmode, base, offset));
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set_mem_alias_set (mem, mips_got_alias_set);
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/* GOT references can't trap. */
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/* GOT entries are constant and references to them can't trap. */
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RTX_UNCHANGING_P (mem) = 1;
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MEM_NOTRAP_P (mem) = 1;
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/* If we allow a function's address to be lazily bound, its entry
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may change after the first call. Other entries are constant. */
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if (symbol_type != SYMBOL_GOTOFF_CALL)
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RTX_UNCHANGING_P (mem) = 1;
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return mem;
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}
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@ -3193,11 +3189,19 @@ mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
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{
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if (TARGET_EXPLICIT_RELOCS && global_got_operand (addr, VOIDmode))
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{
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rtx high = mips_unspec_offset_high (pic_offset_table_rtx,
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addr, SYMBOL_GOTOFF_CALL);
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addr = mips_load_got (high, addr, SYMBOL_GOTOFF_CALL);
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rtx high, lo_sum_symbol;
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high = mips_unspec_offset_high (pic_offset_table_rtx,
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addr, SYMBOL_GOTOFF_CALL);
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lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
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addr = gen_reg_rtx (Pmode);
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if (Pmode == SImode)
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emit_insn (gen_load_callsi (addr, high, lo_sum_symbol));
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else
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emit_insn (gen_load_calldi (addr, high, lo_sum_symbol));
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}
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addr = force_reg (Pmode, addr);
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else
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addr = force_reg (Pmode, addr);
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}
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if (TARGET_MIPS16
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@ -1468,7 +1468,8 @@ extern const struct mips_cpu_info *mips_tune_info;
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- 8 condition code registers
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- 2 accumulator registers (hi and lo)
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- 32 registers each for coprocessors 0, 2 and 3
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- 6 dummy entries that were used at various times in the past. */
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- FAKE_CALL_REGNO (see the comment above load_callsi for details)
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- 5 dummy entries that were used at various times in the past. */
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#define FIRST_PSEUDO_REGISTER 176
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@ -54,8 +54,11 @@
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(UNSPEC_SDL 24)
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(UNSPEC_SDR 25)
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(UNSPEC_LOADGP 26)
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(UNSPEC_LOAD_CALL 27)
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(UNSPEC_ADDRESS_FIRST 100)])
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(UNSPEC_ADDRESS_FIRST 100)
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(FAKE_CALL_REGNO 79)])
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;; ....................
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;;
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@ -8331,6 +8334,42 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j\t%2%/"
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;;
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;; ....................
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;; Instructions to load a call address from the GOT. The address might
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;; point to a function or to a lazy binding stub. In the latter case,
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;; the stub will use the dynamic linker to resolve the function, which
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;; in turn will change the GOT entry to point to the function's real
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;; address.
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;;
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;; This means that every call, even pure and constant ones, can
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;; potentially modify the GOT entry. And once a stub has been called,
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;; we must not call it again.
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;;
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;; We represent this restriction using an imaginary fixed register that
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;; acts like a GOT version number. By making the register call-clobbered,
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;; we tell the target-independent code that the address could be changed
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;; by any call insn.
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(define_insn "load_callsi"
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[(set (match_operand:SI 0 "register_operand" "=c")
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(unspec:SI [(match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "immediate_operand" "")
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(reg:SI FAKE_CALL_REGNO)]
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UNSPEC_LOAD_CALL))]
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"TARGET_ABICALLS"
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"lw\t%0,%R2(%1)"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn "load_calldi"
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[(set (match_operand:DI 0 "register_operand" "=c")
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(unspec:DI [(match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "immediate_operand" "")
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(reg:DI FAKE_CALL_REGNO)]
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UNSPEC_LOAD_CALL))]
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"TARGET_ABICALLS"
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"ld\t%0,%R2(%1)"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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;; Sibling calls. All these patterns use jump instructions.
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;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
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