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[AArch64] Fix PR 64263: Do not try to split constants when destination is SIMD reg 

PR target/64263
	* config/aarch64/aarch64.md (*movsi_aarch64): Don't split if the
	destination is not a GP reg.
	(*movdi_aarch64): Likewise.

	* gcc.target/aarch64/pr64263_1.c: New test.

Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

From-SVN: r219745
This commit is contained in:
Kyrylo Tkachov 2015-01-16 14:50:39 +00:00 committed by Kyrylo Tkachov
parent e989e68d93
commit f2a03a7264
4 changed files with 40 additions and 2 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2015-01-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/64263
* config/aarch64/aarch64.md (*movsi_aarch64): Don't split if the
destination is not a GP reg.
(*movdi_aarch64): Likewise.
2015-01-16 David Edelsohn <dje.gcc@gmail.com>
PR target/64623

6
gcc/config/aarch64/aarch64.md
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@ -859,7 +859,8 @@
fmov\\t%s0, %w1
fmov\\t%w0, %s1
fmov\\t%s0, %s1"
"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)"
"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)
&& GP_REGNUM_P (REGNO (operands[0]))"
[(const_int 0)]
"{
aarch64_expand_mov_immediate (operands[0], operands[1]);
@ -891,7 +892,8 @@
fmov\\t%x0, %d1
fmov\\t%d0, %d1
movi\\t%d0, %1"
"(CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode))"
"(CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode))
&& GP_REGNUM_P (REGNO (operands[0]))"
[(const_int 0)]
"{
aarch64_expand_mov_immediate (operands[0], operands[1]);

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2015-01-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/64263
* gcc.target/aarch64/pr64263_1.c: New test.
2015-01-16 Yuri Rumyantsev <ysrumyan@gmail.com>
PR tree-optimization/64434

23
gcc/testsuite/gcc.target/aarch64/pr64263_1.c Normal file
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@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-options "-O1" } */
#include "arm_neon.h"
extern long int vget_lane_s64_1 (int64x1_t, const int);
void
foo ()
{
int8x8_t val14;
int8x8_t val15;
uint8x8_t val16;
uint32x4_t val40;
val14 = vcreate_s8 (0xff0080f6807f807fUL);
val15 = vcreate_s8 (0x10807fff7f808080UL);
val16 = vcgt_s8 (val14, val15);
val40 = vreinterpretq_u32_u64 (
vdupq_n_u64 (
vget_lane_s64_1 (
vreinterpret_s64_u8 (val16), 0)
));
}