i386.md (lshlv16qi3): Remove expander.
* config/i386/i386.md (lshlv16qi3): Remove expander. (lshrv16qi3): New expander. (<shift_insn>v16qi3): Macroize expander from ashrv16qi3 and lshrv16qi3 using any_shiftrt code iterator. Cleanup. (ashlv16qi3): Cleanup. (ashrv2di3): Ditto. From-SVN: r180657
This commit is contained in:
Uros Bizjak
parent
d1fecc879e
commit
f327a48e6e
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@ -1,7 +1,17 @@
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2011-10-29 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (lshlv16qi3): Remove expander.
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(lshrv16qi3): New expander.
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(<shift_insn>v16qi3): Macroize expander from ashrv16qi3 and lshrv16qi3
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using any_shiftrt code iterator. Cleanup.
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(ashlv16qi3): Cleanup.
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(ashrv2di3): Ditto.
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2011-10-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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PR target/50691
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config/pa/pa.c (emit_move_sequence): Legitimize TLS symbol references.
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* config/pa/pa.c (emit_move_sequence): Legitimize TLS symbol
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references.
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(pa_legitimate_constant_p): Return false for TLS_MODEL_GLOBAL_DYNAMIC
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and TLS_MODEL_LOCAL_DYNAMIC symbol references.
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@ -94,7 +104,7 @@
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* Makefile.in (MOSTLYCLEANFILES): Add gcc-ar/nm/ranlib.
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(native): Add gcc-ar, gcc-nm, gcc-ranlib.
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(AR_LIBS, gcc-ar, gcc-ar.o, gcc-ranlib, gcc-ranlib.o,
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gcc-nm, gcc-nm.o, gcc-ranlib.c, gcc-nm.c): Add.
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gcc-nm, gcc-nm.o, gcc-ranlib.c, gcc-nm.c): Add.
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(install): Depend on install-gcc-ar.
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(install-gcc-ar): Add.
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(uninstall): Uninstall gcc-ar, gcc-nm, gcc-ranlib.
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@ -5940,8 +5940,9 @@
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(define_expand "<code><mode>3"
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[(set (match_operand:VI8_AVX2 0 "register_operand" "")
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(maxmin:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "")
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(match_operand:VI8_AVX2 2 "register_operand" "")))]
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(maxmin:VI8_AVX2
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(match_operand:VI8_AVX2 1 "register_operand" "")
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(match_operand:VI8_AVX2 2 "register_operand" "")))]
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"TARGET_SSE4_2"
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{
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enum rtx_code code;
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@ -5974,8 +5975,9 @@
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(define_expand "<code><mode>3"
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[(set (match_operand:VI124_128 0 "register_operand" "")
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(smaxmin:VI124_128 (match_operand:VI124_128 1 "nonimmediate_operand" "")
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(match_operand:VI124_128 2 "nonimmediate_operand" "")))]
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(smaxmin:VI124_128
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(match_operand:VI124_128 1 "nonimmediate_operand" "")
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(match_operand:VI124_128 2 "nonimmediate_operand" "")))]
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"TARGET_SSE2"
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{
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if (TARGET_SSE4_1 || <MODE>mode == V8HImode)
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@ -6043,8 +6045,9 @@
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(define_expand "<code><mode>3"
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[(set (match_operand:VI124_128 0 "register_operand" "")
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(umaxmin:VI124_128 (match_operand:VI124_128 1 "nonimmediate_operand" "")
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(match_operand:VI124_128 2 "nonimmediate_operand" "")))]
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(umaxmin:VI124_128
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(match_operand:VI124_128 1 "nonimmediate_operand" "")
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(match_operand:VI124_128 2 "nonimmediate_operand" "")))]
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"TARGET_SSE2"
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{
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if (TARGET_SSE4_1 || <MODE>mode == V16QImode)
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@ -11382,7 +11385,7 @@
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(set_attr "prefix_extra" "2")
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(set_attr "mode" "TI")])
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;; SSE2 doesn't have some shift varients, so define versions for XOP
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;; SSE2 doesn't have some shift variants, so define versions for XOP
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(define_expand "ashlv16qi3"
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[(set (match_operand:V16QI 0 "register_operand" "")
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(ashift:V16QI
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@ -11390,65 +11393,52 @@
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(match_operand:SI 2 "nonmemory_operand" "")))]
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"TARGET_XOP"
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{
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rtvec vs = rtvec_alloc (16);
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rtx par = gen_rtx_PARALLEL (V16QImode, vs);
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rtx reg = gen_reg_rtx (V16QImode);
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rtx par;
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int i;
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par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
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for (i = 0; i < 16; i++)
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RTVEC_ELT (vs, i) = operands[2];
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XVECEXP (par, 0, i) = operands[2];
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emit_insn (gen_vec_initv16qi (reg, par));
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emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg));
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DONE;
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})
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(define_expand "lshlv16qi3"
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[(match_operand:V16QI 0 "register_operand" "")
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")]
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"TARGET_XOP"
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{
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rtvec vs = rtvec_alloc (16);
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rtx par = gen_rtx_PARALLEL (V16QImode, vs);
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rtx reg = gen_reg_rtx (V16QImode);
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int i;
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for (i = 0; i < 16; i++)
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RTVEC_ELT (vs, i) = operands[2];
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emit_insn (gen_vec_initv16qi (reg, par));
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emit_insn (gen_xop_lshlv16qi3 (operands[0], operands[1], reg));
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DONE;
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})
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(define_expand "ashrv16qi3"
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(define_expand "<shift_insn>v16qi3"
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[(set (match_operand:V16QI 0 "register_operand" "")
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(ashiftrt:V16QI
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(any_shiftrt:V16QI
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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"TARGET_XOP"
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{
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rtvec vs = rtvec_alloc (16);
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rtx par = gen_rtx_PARALLEL (V16QImode, vs);
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rtx reg = gen_reg_rtx (V16QImode);
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rtx par;
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bool negate = false;
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rtx (*shift_insn)(rtx, rtx, rtx);
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int i;
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rtx ele = ((CONST_INT_P (operands[2]))
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? GEN_INT (- INTVAL (operands[2]))
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: operands[2]);
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if (CONST_INT_P (operands[2]))
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operands[2] = GEN_INT (-INTVAL (operands[2]));
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else
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negate = true;
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par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
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for (i = 0; i < 16; i++)
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RTVEC_ELT (vs, i) = ele;
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XVECEXP (par, 0, i) = operands[2];
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emit_insn (gen_vec_initv16qi (reg, par));
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if (!CONST_INT_P (operands[2]))
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{
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rtx neg = gen_reg_rtx (V16QImode);
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emit_insn (gen_negv16qi2 (neg, reg));
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emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], neg));
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}
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else
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emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg));
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if (negate)
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emit_insn (gen_negv16qi2 (reg, reg));
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if (<CODE> == LSHIFTRT)
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shift_insn = gen_xop_lshlv16qi3;
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else
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shift_insn = gen_xop_ashlv16qi3;
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emit_insn (shift_insn (operands[0], operands[1], reg));
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DONE;
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})
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@ -11459,29 +11449,25 @@
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(match_operand:DI 2 "nonmemory_operand" "")))]
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"TARGET_XOP"
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{
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rtvec vs = rtvec_alloc (2);
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rtx par = gen_rtx_PARALLEL (V2DImode, vs);
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rtx reg = gen_reg_rtx (V2DImode);
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rtx ele;
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rtx par;
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bool negate = false;
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int i;
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if (CONST_INT_P (operands[2]))
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ele = GEN_INT (- INTVAL (operands[2]));
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else if (GET_MODE (operands[2]) != DImode)
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{
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rtx move = gen_reg_rtx (DImode);
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ele = gen_reg_rtx (DImode);
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convert_move (move, operands[2], false);
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emit_insn (gen_negdi2 (ele, move));
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}
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operands[2] = GEN_INT (-INTVAL (operands[2]));
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else
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{
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ele = gen_reg_rtx (DImode);
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emit_insn (gen_negdi2 (ele, operands[2]));
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}
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negate = true;
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par = gen_rtx_PARALLEL (V2DImode, rtvec_alloc (2));
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for (i = 0; i < 2; i++)
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XVECEXP (par, 0, i) = operands[2];
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RTVEC_ELT (vs, 0) = ele;
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RTVEC_ELT (vs, 1) = ele;
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emit_insn (gen_vec_initv2di (reg, par));
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if (negate)
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emit_insn (gen_negv2di2 (reg, reg));
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emit_insn (gen_xop_ashlv2di3 (operands[0], operands[1], reg));
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DONE;
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})
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