rs6000: Merge lshrsi3 and lshrdi3
For this create a new mode_attr "hH". Also change "i" constraints on the shift amount to "n", which better describes what it really is (GCC takes the integer value of these operands and does arithmetic on them; symbolic constants will not work here). Also merge the "dot" insns with the corresponding splitters. To do this, don't allow the dot insns for CBE non-microcode mode at all (it previously would just split it back always). From-SVN: r211876
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
1a2443af3a
commit
f39a447c2d
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@ -1,3 +1,12 @@
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2014-06-22 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md ("hH"): New define_mode_attr.
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(lshrsi3, two anonymous define_insns and define_splits,
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lshrdi3, *lshrdi3_internal1, *lshrdi3_internal2 and split,
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*lshrdi3_internal3 and split): Delete, merge into...
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(lshr<mode>3, lshr<mode>3_dot, lshr<mode>3_dot2): New.
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(*lshrsi3_64): Fix formatting. Replace "i" by "n".
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2014-06-22 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (lshrsi3, and its two dot patterns):
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@ -438,6 +438,9 @@
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;; ISEL/ISEL64 target selection
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(define_mode_attr sel [(SI "") (DI "64")])
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;; Bitmask for shift instructions
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(define_mode_attr hH [(SI "h") (DI "H")])
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;; Suffix for reload patterns
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(define_mode_attr ptrsize [(SI "32bit")
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(DI "64bit")])
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@ -4542,92 +4545,82 @@
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(const_int 0)))]
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"")
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(define_insn "lshrsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
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(define_insn "lshr<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "r,n")))]
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""
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"@
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srw %0,%1,%2
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srwi %0,%1,%h2"
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sr<wd> %0,%1,%2
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sr<wd>i %0,%1,%<hH>2"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*lshrsi3_64"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(zero_extend:DI
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(zero_extend:DI
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(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
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(match_operand:SI 2 "reg_or_cint_operand" "r,n"))))]
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"TARGET_POWERPC64"
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"@
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srw %0,%1,%2
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srwi %0,%1,%h2"
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srw %0,%1,%2
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srwi %0,%1,%h2"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r,r,r"))]
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"TARGET_32BIT"
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"@
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srw. %3,%1,%2
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srwi. %3,%1,%h2
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3)
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(lshiftrt:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn ""
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(define_insn_and_split "*lshr<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
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(compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(lshiftrt:SI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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(clobber (match_scratch:GPR 0 "=r,r,r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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srw. %0,%1,%2
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srwi. %0,%1,%h2
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sr<wd>. %0,%1,%2
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sr<wd>i. %0,%1,%<hH>2
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
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(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(lshiftrt:SI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT && reload_completed"
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"&& reload_completed"
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[(set (match_dup 0)
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(lshiftrt:SI (match_dup 1) (match_dup 2)))
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(lshiftrt:GPR (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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""
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_insn_and_split "*lshr<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
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(lshiftrt:GPR (match_dup 1)
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(match_dup 2)))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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sr<wd>. %0,%1,%2
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sr<wd>i. %0,%1,%<hH>2
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#
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#"
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"&& reload_completed"
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[(set (match_dup 0)
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(lshiftrt:GPR (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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@ -7901,88 +7894,6 @@
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(const_int 0)))]
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"")
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(define_expand "lshrdi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" "")))]
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"TARGET_POWERPC64"
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"")
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(define_insn "*lshrdi3_internal1"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
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"TARGET_POWERPC64"
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"@
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srd %0,%1,%2
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srdi %0,%1,%H2"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*lshrdi3_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
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(const_int 0)))
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(clobber (match_scratch:DI 3 "=r,r,r,r"))]
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"TARGET_64BIT "
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"@
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srd. %3,%1,%2
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srdi. %3,%1,%H2
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:DI 3 ""))]
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"TARGET_POWERPC64 && reload_completed"
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[(set (match_dup 3)
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(lshiftrt:DI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn "*lshrdi3_internal3"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
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(const_int 0)))
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(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
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(lshiftrt:DI (match_dup 1) (match_dup 2)))]
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"TARGET_64BIT"
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"@
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srd. %0,%1,%2
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srdi. %0,%1,%H2
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#
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#"
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no,yes,no")
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(set_attr "dot" "yes")
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(set_attr "length" "4,4,8,8")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(set (match_operand:DI 0 "gpc_reg_operand" "")
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(lshiftrt:DI (match_dup 1) (match_dup 2)))]
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"TARGET_POWERPC64 && reload_completed"
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[(set (match_dup 0)
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(lshiftrt:DI (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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(define_expand "ashrdi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
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